Searched refs:I915_READ (Results 1 - 25 of 30) sorted by relevance

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/solaris-x11-s11/open-src/kernel/i915/src/
H A Di915_ums.c48 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
70 array[i] = I915_READ(reg + (i << 2));
101 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
102 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
103 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
104 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
105 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
106 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
108 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
111 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTRO
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H A Di915_suspend.c78 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
79 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
80 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
81 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
204 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
215 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
216 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
217 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
218 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
219 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL
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H A Dintel_sideband.c42 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
53 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
60 *val = I915_READ(VLV_IOSF_DATA);
127 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
141 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
147 return I915_READ(SBI_DATA);
157 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
172 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
H A Di915_irq.c183 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
185 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
204 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
206 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
321 u32 pipestat = I915_READ(reg) & 0x7fff0000;
336 u32 pipestat = I915_READ(reg) & 0x7fff0000;
367 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
396 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
397 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
398 high2 = I915_READ(high_fram
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H A Dintel_crt.c77 tmp = I915_READ(crt->adpa_reg);
97 tmp = I915_READ(crt->adpa_reg);
121 temp = I915_READ(crt->adpa_reg);
300 save_adpa = adpa = I915_READ(crt->adpa_reg);
309 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
320 adpa = I915_READ(crt->adpa_reg);
339 save_adpa = adpa = I915_READ(crt->adpa_reg);
346 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
353 adpa = I915_READ(crt->adpa_reg);
398 hotplug_en = orig = I915_READ(PORT_HOTPLUG_E
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H A Dintel_ddi.c154 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
236 temp = I915_READ(_FDI_RXA_MISC);
244 temp = I915_READ(DP_TP_STATUS(PORT_E));
258 temp = I915_READ(DDI_BUF_CTL(PORT_E));
264 temp = I915_READ(DP_TP_CTL(PORT_E));
277 temp = I915_READ(_FDI_RXA_MISC);
376 val = I915_READ(SPLL_CTL);
386 val = I915_READ(WRPLL_CTL1);
396 val = I915_READ(WRPLL_CTL2);
692 if(I915_READ(re
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H A Dintel_pm.c64 fbc_ctl = I915_READ(FBC_CONTROL);
72 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
127 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
152 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
163 dpfc_ctl = I915_READ(DPFC_CONTROL);
176 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
186 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
211 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
243 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
251 I915_READ(ILK_DSPCLK_GATE_
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H A Dintel_ringbuffer.h54 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
57 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
60 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
63 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
66 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
69 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
70 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
71 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
H A Di915_gem_debug.c361 #define ring_read(ring, reg) I915_READ(ring->mmio + reg)
595 while (count++ < 50 && (I915_READ(FORCEWAKE_ACK) & 1))
602 while (count++ < 50 && (I915_READ(FORCEWAKE_ACK) & 1) == 0)
717 stats_high = I915_READ(stats_regs[i] + 4);
718 stats_low = I915_READ(stats_regs[i]);
719 stats_high_2 = I915_READ(stats_regs[i] + 4);
744 instdone = I915_READ(INST_DONE_I965);
745 instdone1 = I915_READ(INST_DONE_1);
747 instdone = I915_READ(INST_DONE);
775 stats_high = I915_READ(stats_reg
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H A Dintel_display.c69 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
77 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
742 frame = I915_READ(frame_reg);
780 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
783 if (wait_for(I915_READ(pipestat_reg) &
816 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
831 last_line = I915_READ(reg) & line_mask;
833 } while (((I915_READ(reg) & line_mask) != last_line) &&
882 return I915_READ(SDEISR) & bit;
899 val = I915_READ(re
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H A Dintel_sprite.c56 sprctl = I915_READ(SPCNTR(pipe, plane));
150 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
175 sprctl = I915_READ(SPCNTR(pipe, plane));
197 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
198 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
199 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
201 sprctl = I915_READ(SPCNTR(pipe, plane));
224 sprctl = I915_READ(SPRCTL(pipe));
328 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
361 sprctl = I915_READ(SPRCT
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H A Dintel_panel.c323 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
326 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
339 val = I915_READ(BLC_PWM_PCH_CTL2);
347 val = I915_READ(BLC_PWM_CTL);
352 I915_READ(BLC_PWM_CTL2);
414 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
416 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
439 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
469 tmp = I915_READ(BLC_PWM_CTL);
533 I915_WRITE(reg, I915_READ(re
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H A Dintel_dvo.c133 tmp = I915_READ(intel_dvo->dev.dvo_reg);
150 tmp = I915_READ(intel_dvo->dev.dvo_reg);
168 u32 temp = I915_READ(dvo_reg);
172 I915_READ(dvo_reg);
180 u32 temp = I915_READ(dvo_reg);
183 I915_READ(dvo_reg);
308 dvo_val = I915_READ(dvo_reg) &
321 I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED);
424 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
H A Dintel_dp.c197 clkcfg = I915_READ(CLKCFG);
227 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
237 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
256 I915_READ(pp_stat_reg),
257 I915_READ(pp_ctrl_reg));
348 I915_READ(ch_ctl));
375 status = I915_READ(ch_ctl);
426 unpack_aux(I915_READ(ch_data + i),
804 dpa_ctl = I915_READ(DP_A);
856 intel_dp->DP = I915_READ(intel_d
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H A Dintel_lvds.c76 tmp = I915_READ(lvds_encoder->reg);
101 tmp = I915_READ(lvds_reg);
115 tmp = I915_READ(PFIT_CONTROL);
136 temp = I915_READ(lvds_encoder->reg);
206 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
208 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
210 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
233 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
234 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
237 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encode
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H A Dintel_hdmi.c56 if (I915_READ(intel_hdmi->hdmi_reg) & enabled_bits)
147 u32 val = I915_READ(VIDEO_DIP_CTL);
188 u32 val = I915_READ(reg);
228 u32 val = I915_READ(reg);
271 u32 val = I915_READ(reg);
312 u32 val = I915_READ(ctl_reg);
392 u32 val = I915_READ(reg);
457 u32 val = I915_READ(reg);
517 u32 val = I915_READ(reg);
552 u32 val = I915_READ(re
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H A Dintel_overlay.c282 tmp = I915_READ(DOVSTA);
406 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
831 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
841 u32 pfit_control = I915_READ(PFIT_CONTROL);
849 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
852 ratio = I915_READ(PFIT_AUTO_RATIOS);
854 ratio = I915_READ(PFIT_PGM_RATIOS);
1014 pfit_control = I915_READ(PFIT_CONTROL);
1252 attrs->gamma0 = I915_READ(OGAMC0);
1253 attrs->gamma1 = I915_READ(OGAMC
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H A Di915_gem_tiling.c103 dimm_c0 = I915_READ(MAD_DIMM_C0);
104 dimm_c1 = I915_READ(MAD_DIMM_C1);
142 dcc = I915_READ(DCC);
H A Di915_gem_gtt.c246 ecobits = I915_READ(GAC_ECO_BITS);
250 gab_ctl = I915_READ(GAB_CTL);
253 ecochk = I915_READ(GAM_ECOCHK);
260 ecobits = I915_READ(GAC_ECO_BITS);
263 ecochk = I915_READ(GAM_ECOCHK);
979 pgetbl_ctl2 = I915_READ(I965_PGETBL_CTL2);
984 pgetbl_ctl = I915_READ(I810_PGETBL_CTL);
1017 pgetbl_ctl = I915_READ(I810_PGETBL_CTL);
H A Dintel_tv.c849 u32 tmp = I915_READ(TV_CTL);
865 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
874 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
955 tv_ctl = I915_READ(TV_CTL);
1096 int pipeconf = I915_READ(pipeconf_reg);
1097 int dspcntr = I915_READ(dspcntr_reg);
1143 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
1195 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1196 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1233 tv_dac = I915_READ(TV_DA
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H A Dintel_i2c.c80 val = I915_READ(DSPCLK_GATE_D);
251 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset))
315 val = I915_READ(GMBUS3 + reg_offset);
H A Ddvo_ns2501.c109 ns->dvoc = I915_READ(DVO_C);
110 ns->pll_a = I915_READ(_DPLL_A);
111 ns->srcdim = I915_READ(DVOC_SRCDIM);
112 ns->fw_blc = I915_READ(FW_BLC);
H A Di915_drv.c648 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
665 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
711 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
715 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
720 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
724 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
1435 reg->val = I915_READ(reg->offset);
H A Di915_gem_context.c118 reg = I915_READ(CXT_SIZE);
122 reg = I915_READ(GEN7_CXT_SIZE);
H A Dintel_sdvo.c247 I915_READ(intel_sdvo->sdvo_reg);
252 cval = I915_READ(GEN3_SDVOC);
254 bval = I915_READ(GEN3_SDVOB);
264 I915_READ(GEN3_SDVOB);
266 I915_READ(GEN3_SDVOC);
1236 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1297 tmp = I915_READ(intel_sdvo->sdvo_reg);
1351 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1390 temp = I915_READ(intel_sdvo->sdvo_reg);
1431 temp = I915_READ(intel_sdv
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