Lines Matching refs:I915_READ
56 sprctl = I915_READ(SPCNTR(pipe, plane));
150 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
175 sprctl = I915_READ(SPCNTR(pipe, plane));
197 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
198 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
199 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
201 sprctl = I915_READ(SPCNTR(pipe, plane));
224 sprctl = I915_READ(SPRCTL(pipe));
328 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
361 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
384 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
385 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
386 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
389 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
414 dvscntr = I915_READ(DVSCNTR(pipe));
492 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
514 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
528 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
550 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
573 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
574 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
575 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
578 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
658 if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) {