1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright 2008, 2013, (c) Intel Corporation 1450N/A * Jesse Barnes <jbarnes@virtuousgeek.org> 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the 1450N/A * "Software"), to deal in the Software without restriction, including 1450N/A * without limitation the rights to use, copy, modify, merge, publish, 1450N/A * distribute, sub license, and/or sell copies of the Software, and to 1450N/A * permit persons to whom the Software is furnished to do so, subject to 1450N/A * the following conditions: 1450N/A * The above copyright notice and this permission notice (including the 1450N/A * next paragraph) shall be included in all copies or substantial portions 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1450N/A * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1450N/A * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 1450N/A * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 1450N/A * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 1450N/A * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 1450N/A * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 1450N/A /* VGA color palette registers */ 1450N/A for (i = 0; i <=
0x24; i++)
1450N/A /* Make sure we don't turn off CR group 0 writes */ 1450N/A /* Attribute controller registers */ 1450N/A for (i = 0; i <=
0x14; i++)
1450N/A /* Graphics controller registers */ 1450N/A /* Sequencer registers, don't write SR07 */ 1450N/A /* Enable CR group 0 writes */ 1450N/A for (i = 0; i <=
0x24; i++)
1450N/A /* Graphics controller regs */ 1450N/A /* Attribute controller registers */ 1450N/A for (i = 0; i <=
0x14; i++)
1450N/A /* VGA color palette registers */ 1450N/A /* Display arbitration control */ 1450N/A /* This is only meaningful in non-KMS mode */ 1450N/A /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2; 1450N/A * otherwise we get blank eDP screen after S3 on some machines 1450N/A /* only restore FBC info on the platform that supports FBC*/ 1450N/A /* Memory Arbitration state */ 1450N/A /* Memory arbitration state */