1450N/A * Copyright (c) 2012, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright (c) 2012, 2013, Intel Corporation. All rights reserved. 1450N/A * Copyright © 2010 Daniel Vetter 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 1450N/A/* gen6+ has bit 11-4 for physical addr bit 39-32 */ 1450N/A /* Mark the page as writeable. Other platforms don't have a 1450N/A 0xff000U,
/* dma_attr_addr_lo */ 1450N/A 0xffffffffU,
/* dma_attr_addr_hi */ 1450N/A 0xffffffffU,
/* dma_attr_count_max */ 1450N/A 0x1fffU,
/* dma_attr_burstsizes */ 1450N/A 0xffffffffU,
/* dma_attr_maxxfer */ 1450N/A 0xffffffffU,
/* dma_attr_seg */ 1450N/A 1,
/* dma_attr_sgllen, variable */ 1450N/A "ddi_dma_alloc_handle failed");
1450N/A "ddi_dma_mem_alloc failed");
1450N/A "ddi_dma_addr_bind_handle failed");
1450N/A for (n = 0, i =
1; ; i++) {
1450N/A /* GFX_MODE is per-ring on gen7+ */ 1450N/A /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 1450N/A * entries. For aliasing ppgtt support we just steal them at the end for 1450N/A /* First fill our portion of the GTT with scratch pages */ 1450N/A i915_ggtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE, 1450N/A (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE); 1450N/A * Binds an object into the global gtt with the specified cache level. The object 1450N/A * will be accessible to the GPU via commands whose operands reference offsets 1450N/A * within the global GTT as well as accessible by the GPU through the GMADR 1450N/A * mapped BAR (dev_priv->mm.gtt->gtt). 1450N/A /* XXX: This serves as a posting read to make sure that the PTE has 1450N/A * actually been updated. There is some concern that even though 1450N/A * registers and PTEs are within the same BAR that they are potentially 1450N/A * of NUMA access patterns. Therefore, even with the way we assume 1450N/A * hardware should work, we must keep this posting read for paranoia. 1450N/A /* This next bit makes the above posting read even more important. We 1450N/A * want to flush the TLBs only after we're certain all the PTE updates 1450N/A /* Let GEM Manage all of the aperture. 1450N/A * However, leave one page at the end still bound to the scratch page. 1450N/A * There are a number of places where the hardware apparently prefetches 1450N/A * past the end of the object, and we've seen multiple hangs with the 1450N/A * GPU head pointer stuck in a batchbuffer bound at the last page of the 1450N/A * aperture. One page should be enough to keep any prefetching inside 1450N/A /* Substract the guard page ... */ 1450N/A /* Mark any preallocated objects as occupied */ 1450N/A /* Disable ppgtt on SNB if VT-d is on. */ 1450N/A /* PPGTT pdes are stolen from global gtt ptes, so shrink the 1450N/A * aperture accordingly when using aliasing ppgtt. */ 1450N/A /* 64/512MB is the current min/max we actually know of, but this is just 1450N/A /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */ 1450N/A static const int ddt[
4] = { 0,
16,
32,
64 };
1450N/A return 0;
/* no stolen mem on i81x */ 1450N/A /* 9xx supports large sizes, just look at the length */ 1450N/A /* ensure that ppgtt is disabled */ 1450N/A /* write the new ggtt size */ 1450N/A /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 1450N/A /* On previous hardware, the GTT size was just what was 1450N/A * required to map the aperture. 1450N/A /* GMADR is the PCI mmio aperture into the global GTT. */