1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright (c) 2006-2007, 2013, Intel Corporation 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 1450N/A * DEALINGS IN THE SOFTWARE. 1450N/A * Eric Anholt <eric@anholt.net> 1450N/A /* n.min 1->2 fix high resolution issue */ 1450N/A /* Pineview's Ncounter is a ring counter */ 1450N/A /* Pineview only has one combined m divider, which we treat as m2. */ 1450N/A * We calculate clock using (register_value + 2) for N/M1/M2, so here 1450N/A * the range value for them is (actual_value - 2). 1450N/A /* n.min 1->2 fix high resolution issue */ 1450N/A/* LVDS 100mhz refclk limits. */ 1450N/A }
else /* The option is for other outputs */ 1450N/A/* m1 is reserved as 0 in Pineview, n is a ring counter */ 1450N/A * Returns whether any output on the specified pipe is of the specified type 1450N/A * Returns whether the given set of divisors are valid for a given refclk with 1450N/A /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 1450N/A * connector, etc., rather than just a single range. 1450N/A * For LVDS just rely on its current settings for dual-channel. 1450N/A * We haven't figured out how to reliably set up different 1450N/A * For LVDS just rely on its current settings for dual-channel. 1450N/A * We haven't figured out how to reliably set up different 1450N/A /* approximately equals target * 0.00585 */ 1450N/A /* based on hardware requirement prefer smaller n to precision */ 1450N/A /* based on hardware requirement prefer larger m1,m2 */ 1450N/A /* based on hardware requirement, prefer smaller n to precision */ 1450N/A /* based on hardware requirement, prefer bigger m1,m2 values */ 1450N/A * intel_wait_for_vblank - wait for vblank on a given pipe 1450N/A * Wait for vblank to occur on a given pipe. Needed for various bits of 1450N/A /* Clear existing vblank status. Note this will clear any other 1450N/A * sticky status fields as well. 1450N/A * This races with i915_driver_irq_handler() with the result 1450N/A * that either function could miss a vblank event. Here it is not 1450N/A * fatal, as we will either wait upon the next vblank interrupt or 1450N/A * timeout. Generally speaking intel_wait_for_vblank() is only 1450N/A * called during modeset at which time the GPU should be idle and 1450N/A * should *not* be performing page flips and thus not waiting on 1450N/A * Currently, the result of us stealing a vblank from the irq 1450N/A * handler is that a single frame will be skipped during swapbuffers. 1450N/A /* Wait for vblank interrupt bit to set */ 1450N/A * intel_wait_for_pipe_off - wait for pipe to turn off 1450N/A * After disabling a pipe, we can't wait for vblank in the usual way, 1450N/A * spinning on the vblank interrupt status bit, since we won't actually 1450N/A * see an interrupt when the pipe is disabled. 1450N/A * wait for the pipe register state bit to turn off 1450N/A * wait for the display line value to settle (it usually 1450N/A * ends up stopping at the start of the next frame). 1450N/A /* Wait for the Pipe State to go off */ 1450N/A /* Wait for the display line to settle */ 1450N/A * ibx_digital_port_connected - is the specified port connected? 1450N/A * @dev_priv: i915 private structure 1450N/A * Returns true if @port is connected, false otherwise. 1450N/A/* Only for pre-ILK configs */ 1450N/A /* On Haswell, DDI is used instead of FDI_TX_CTL */ 1450N/A /* ILK FDI PLL is always enabled */ 1450N/A /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 1450N/A DRM_ERROR(
"FDI TX PLL assertion failure, should be active but is disabled\n");
1450N/A DRM_ERROR(
"FDI RX PLL assertion failure, should be active but is disabled\n");
1450N/A /* if we need the pipe A quirk it must be always on */ 1450N/A DRM_ERROR(
"plane %c assertion failure, should be active but is disabled\n",
1450N/A /* Planes are fixed to pipes on ILK+ */ 1450N/A /* Need to check both planes against the pipe */ 1450N/A DRM_ERROR(
"plane %c assertion failure, should be off on pipe %c but is still active\n",
1450N/A DRM_ERROR(
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
1450N/A DRM_ERROR(
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
1450N/A DRM_ERROR(
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
1450N/A DRM_ERROR(
"PCH refclk assertion failure, should be active but is disabled\n");
1450N/A DRM_ERROR(
"transcoder assertion failed, should be off on pipe %c but is still active\n",
1450N/A DRM_ERROR(
"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1450N/A DRM_ERROR(
"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1450N/A * intel_enable_pll - enable a PLL 1450N/A * @dev_priv: i915 private structure 1450N/A * @pipe: pipe PLL to enable 1450N/A * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to 1450N/A * make sure the PLL reg is writable first though, since the panel write 1450N/A * protect mechanism may be enabled. 1450N/A * Note! This is for pre-ILK only. 1450N/A * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. 1450N/A /* No really, not for ILK+ */ 1450N/A /* PLL is protected by panel, make sure we can write it */ 1450N/A /* We do this three times for luck */ 1450N/A * intel_disable_pll - disable a PLL 1450N/A * @dev_priv: i915 private structure 1450N/A * @pipe: pipe PLL to disable 1450N/A * Disable the PLL for @pipe, making sure the pipe is off first. 1450N/A * Note! This is for pre-ILK only. 1450N/A /* Don't disable pipe A or pipe A PLLs if needed */ 1450N/A /* Make sure the pipe isn't still relying on us */ 1450N/A * ironlake_enable_pch_pll - enable PCH PLL 1450N/A * @dev_priv: i915 private structure 1450N/A * @pipe: pipe PLL to enable 1450N/A * The PCH PLL needs to be enabled before the PCH transcoder, since it 1450N/A * drives the transcoder clock. 1450N/A /* PCH PLLs only available on ILK, SNB and IVB */ 1450N/A /* PCH only available on ILK+ */ 1450N/A /* PCH only available on ILK+ */ 1450N/A /* Make sure PCH DPLL is enabled */ 1450N/A /* FDI must be feeding us bits for PCH ports */ 1450N/A /* Workaround: Set the timing override bit before enabling the 1450N/A * make the BPC in transcoder be consistent with 1450N/A /* PCH only available on ILK+ */ 1450N/A /* FDI must be feeding us bits for PCH ports */ 1450N/A /* Workaround: set timing override bit. */ 1450N/A /* FDI relies on the transcoder */ 1450N/A /* Ports must be off as well */ 1450N/A /* wait for PCH transcoder off, transcoder state */ 1450N/A /* Workaround: Clear the timing override chicken bit again. */ 1450N/A /* wait for PCH transcoder off, transcoder state */ 1450N/A /* Workaround: clear timing override bit. */ 1450N/A * intel_enable_pipe - enable a pipe, asserting requirements 1450N/A * @dev_priv: i915 private structure 1450N/A * @pch_port: on ILK+, is this pipe driving a PCH port or not 1450N/A * Enable @pipe, making sure that various hardware specific requirements 1450N/A * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1450N/A * @pipe should be %PIPE_A or %PIPE_B. 1450N/A * Will wait until the pipe is actually running (i.e. first vblank) before 1450N/A * A pipe without a PLL won't actually be able to drive bits from 1450N/A * a plane. On ILK+ the pipe PLLs are integrated, so we don't 1450N/A /* if driving the PCH, we need FDI enabled */ 1450N/A /* FIXME: assert CPU port conditions for SNB+ */ 1450N/A * intel_disable_pipe - disable a pipe, asserting requirements 1450N/A * @dev_priv: i915 private structure 1450N/A * Disable @pipe, making sure that various hardware specific requirements 1450N/A * are met, if applicable, e.g. plane disabled, panel fitter off, etc. 1450N/A * @pipe should be %PIPE_A or %PIPE_B. 1450N/A * Will wait until the pipe has shut down before returning. 1450N/A * Make sure planes won't keep trying to pump pixels to us, 1450N/A * or we might hang the display. 1450N/A /* Don't disable pipe A or pipe A PLLs if needed */ 1450N/A * Plane regs are double buffered, going from enabled->disabled needs a 1450N/A * trigger in order to latch. The display address reg provides this. 1450N/A * intel_enable_plane - enable a display plane on a given pipe 1450N/A * @dev_priv: i915 private structure 1450N/A * Enable @plane on @pipe, making sure that @pipe is running first. 1450N/A /* If the pipe isn't enabled, we can't pump pixels and may hang */ 1450N/A * intel_disable_plane - disable a display plane 1450N/A * @dev_priv: i915 private structure 1450N/A * @pipe: pipe consuming the data 1450N/A * Disable @plane; should be an independent operation. 1450N/A /* pin() will align the object as required by fence */ 1450N/A /* Despite that we check this in framebuffer_init userspace can 1450N/A * screw us over and change the tiling after the fact. Only 1450N/A * pinned buffers can't change their tiling. */ 1450N/A /* Note that the w/a also requires 64 PTE of padding following the 1450N/A * bo. We currently fill all unused PTE with the shadow page and so 1450N/A * we should always have valid PTE following the scanout preventing 1450N/A /* Install a fence for tiled scan-out. Pre-i965 always needs a 1450N/A * fence, whereas 965+ only requires a fence if using 1450N/A * framebuffer compression. For simplicity, we always install 1450N/A * a fence as the cost is not that onerous. 1450N/A/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel 1450N/A * is assumed to be a power-of-two. */ 1450N/A /* Mask out pixel format bits in case we change it */ 1450N/A /* Mask out pixel format bits in case we change it */ 1450N/A/* Assume fb object is pinned & idle & fenced and just update base pointers */ 1450N/A * Flips in the rings have been nuked by the reset, 1450N/A * so complete all pending flips so that user space 1450N/A * will get its events and not get stuck. 1450N/A * Also update the base address of all primary 1450N/A * planes to the the last fb to make sure we're 1450N/A * showing the correct fb after a reset. 1450N/A * Need to make two loops over the crtcs so that we 1450N/A * don't try to grab a crtc mutex before the 1450N/A * pending_flip_queue really got woken up. 1450N/A /* Big Hammer, we also need to ensure that any pending 1450N/A * MI_WAIT_FOR_EVENT inside a user batch buffer on the 1450N/A * current scanout is retired before unpinning the old 1450N/A * This should only fail upon a hung GPU, in which case we 1450N/A /* wait one idle pattern time */ 1450N/A /* IVB wants error correction enabled */ 1450N/A * When everything is off disable fdi C so that we could enable fdi B 1450N/A * with all lanes. Note that we don't care about enabled pipes without 1450N/A /* FDI needs bits from pipe & plane first */ 1450N/A /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 1450N/A /* enable CPU FDI TX and PCH FDI RX */ 1450N/A /* Ironlake workaround, enable clock pointer after FDI enable*/ 1450N/A /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 1450N/A /* enable CPU FDI TX and PCH FDI RX */ 1450N/A/* Manual link training for Ivy Bridge A0 parts */ 1450N/A /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 1450N/A /* enable CPU FDI TX and PCH FDI RX */ 1450N/A /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1450N/A /* Switch from Rawclk to PCDclk */ 1450N/A /* Enable CPU FDI TX PLL, always on for Ironlake */ 1450N/A /* Switch from PCDclk to Rawclk */ 1450N/A /* Disable CPU FDI TX PLL */ 1450N/A /* Wait for the clocks to turn off. */ 1450N/A /* disable CPU FDI tx and PCH FDI rx */ 1450N/A /* Ironlake workaround, disable clock pointer after downing FDI */ 1450N/A /* still set train pattern 1 */ 1450N/A /* BPC in FDI rx is consistent with that in PIPECONF */ 1450N/A/* Program iCLKIP clock to the desired frequency */ 1450N/A /* It is necessary to ungate the pixclk gate prior to programming 1450N/A * the divisors, and gate it back when it is done. 1450N/A /* 20MHz is a corner case which is out of range for the 7-bit divisor */ 1450N/A /* The iCLK virtual clock root frequency is in MHz, 1450N/A * but the crtc->mode.clock in in KHz. To get the divisors, 1450N/A * it is necessary to divide one by another, so we 1450N/A * convert the virtual clock precision to KHz here for higher 1450N/A /* This should not happen with any sane values */ 1450N/A DRM_DEBUG_KMS(
"iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
1450N/A /* Program SSCDIVINTPHASE6 */ 1450N/A /* Enable modulator and associated divider */ 1450N/A /* Wait for initialization time */ 1450N/A * Enable PCH resources required for PCH ports: 1450N/A * - update transcoder timings 1450N/A /* Write the TU size bits before fdi link training, so that error 1450N/A /* For PCH output, training FDI link */ 1450N/A /* XXX: pch pll's can be enabled any time before we enable the PCH 1450N/A * transcoder, and we actually should do this to not upset any PCH 1450N/A * transcoder that already use the clock when we share it. 1450N/A * Note that enable_pch_pll tries to do the right thing, but get_pch_pll 1450N/A * unconditionally resets the pll - we need that to have the right LVDS 1450N/A /* set transcoder timing */ 1450N/A /* For PCH DP, enable TRANS_DP_CTL */ 1450N/A /* Set transcoder timing. */ 1450N/A /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 1450N/A /* Only want to check enabled timings first */ 1450N/A /* Ok no matching timings, maybe there's a free one? */ 1450N/A /* Wait for the clocks to stabilize before rewriting the regs */ 1450N/A /* Force use of hard-coded filter coefficients 1450N/A * as some pre-programmed values are broken, 1450N/A /* Note: FDI PLL enabling _must_ be done before we enable the 1450N/A * cpu pipes, hence this is separate from all the other fdi/pch 1450N/A * On ILK+ LUT must be loaded before the pipe is running but with 1450N/A * There seems to be a race in PCH platform hw (at least on some 1450N/A * outputs) where an enabled pipe still completes any pageflip right 1450N/A * away (as if the pipe is off) instead of waiting for vblank. As soon 1450N/A * as the first vblank happend, everything works as expected. Hence just 1450N/A * wait for one vblank before returning to avoid strange things 1450N/A/* IPS only exists on ULT machines and is tied to pipe A. */ 1450N/A /* We can only enable IPS after we enable a plane and wait for a vblank. 1450N/A * We guarantee that the plane is enabled by calling intel_enable_ips 1450N/A * only after intel_enable_plane. And intel_enable_plane already waits 1450N/A * for a vblank, so all we need to do here is to enable the IPS bit. */ 1450N/A /* We need to wait for a vblank before we can disable the plane. */ 1450N/A * On ILK+ LUT must be loaded before the pipe is running but with 1450N/A * There seems to be a race in PCH platform hw (at least on some 1450N/A * outputs) where an enabled pipe still completes any pageflip right 1450N/A * away (as if the pipe is off) instead of waiting for vblank. As soon 1450N/A * as the first vblank happend, everything works as expected. Hence just 1450N/A * wait for one vblank before returning to avoid strange things 1450N/A /* To avoid upsetting the power well on haswell only disable the pfit if 1450N/A * it's in use. The hw state code will make sure we get this right. */ 1450N/A /* FBC must be disabled before disabling the plane on HSW. */ 1450N/A /* Let userspace switch the overlay on again. In most cases userspace 1450N/A * has to recompute where to put it anyway. 1450N/A * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware 1450N/A * cursor plane briefly if not already running after enabling the display 1450N/A * This workaround avoids occasional blank screens when self refresh is 1450N/A * The panel fitter should only be adjusted whilst the pipe is disabled, 1450N/A * according to register description and PRM. 1450N/A /* Border color in case we don't scale up to the full screen. Black by 1450N/A * default, change to something else for debugging. */ 1450N/A /* VLV wants encoder enabling _before_ the pipe is up. */ 1450N/A /* The fixup needs to happen before cursor is enabled */ 1450N/A /* Give the overlay scaler a chance to enable if it's on this pipe */ 1450N/A /* Give the overlay scaler a chance to disable if it's on this pipe */ 1450N/A * Sets the power management mode of the pipe and plane. 1450N/A /* crtc should still be enabled when we disable it. */ 1450N/A /* Update computed state. */ 1450N/A/* Simple dpms helper for encodres with just one connector, no cloning and only 1450N/A * one kind of off state. It clamps all !ON modes to fully OFF and changes the 1450N/A * state of the entire output pipe. */ 1450N/A/* Cross check the actual hw state with our own modeset state tracking (and it's 1450N/A * internal consistency). */ 1450N/A/* Even simpler default implementation, if there's really no special case to 1450N/A /* All the simple cases only support two dpms states. */ 1450N/A /* Only need to change hw state when actually enabled */ 1450N/A/* Simple connector->get_hw_state implementation for encoders that support only 1450N/A * one connector and no cloning and hence the encoder state determines the state 1450N/A /* Ivybridge 3 pipe is really complicated */ 1450N/A /* FDI is a binary signal running at ~2.7GHz, encoding 1450N/A * each output octet as 10 bits. The actual frequency 1450N/A * is stored as a divider into a 100MHz clock, and the 1450N/A * mode pixel clock is stored in units of 1KHz. 1450N/A * Hence the bw of each lane in terms of the mode signal 1450N/A /* FDI link clock is fixed at 2.7G */ 1450N/A /* All interlaced capable intel hw wants timings in frames. Note though 1450N/A * that intel_lvds_mode_fixup does some funny tricks with the crtc 1450N/A * timings, so we need to be careful not to clobber these.*/ 1450N/A /* Cantiga+ cannot handle modes with a hsync front porch of 0. 1450N/A * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 1450N/A /* only a 8bpc pipe, with 6bpc dither through the panel fitter 1450N/A /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old 1450N/A * clock survives for now. */ 1450N/A /* Assume that the hardware is in the high speed state. This 1450N/A return 100000;
/* only one validated so far */ 1450N/A if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 1450N/A } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 1450N/A if (intel_panel_use_ssc(dev_priv)) 1450N/A } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 1450N/A * PLLB opamp always calibrates to max value of 0x3f, force enable it 1450N/A * and set it to a reasonable value instead. 1450N/A /* See eDP HDMI DPIO driver vbios notes doc */ 1450N/A /* PLL B needs special handling */ 1450N/A /* Set up Tx target for periodic Rcomp update */ 1450N/A /* Disable target IRef on PLL */ 1450N/A /* Set idtafcrecal before PLL is enabled */ 1450N/A * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1450N/A * but we don't support that). 1450N/A * Note: don't use the DAC post divider as it seems unstable. 1450N/A /* Set HBR and RBR LPF coefficients */ 1450N/A /* Enable DPIO clock input */ 1450N/A /* compute bitmask from p1 value */ 1450N/A /* Wait for the clocks to stabilize. */ 1450N/A /* The pixel multiplier can only be updated once the 1450N/A * DPLL is enabled and the clocks are stable. 1450N/A /* Wait for the clocks to stabilize. */ 1450N/A /* The pixel multiplier can only be updated once the 1450N/A * DPLL is enabled and the clocks are stable. 1450N/A /* We need to be careful not to changed the adjusted mode, for otherwise 1450N/A * the hw state checker will get angry at the mismatch. */ 1450N/A /* the chip adds 2 halflines automatically */ 1450N/A /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 1450N/A * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 1450N/A * documented on the DDI_FUNC_CTL register description, EDP Input Select 1450N/A /* pipesrc controls the size that is scaled from, which should 1450N/A * always be the user's requested size. 1450N/A /* Enable pixel doubling when the dot clock is > 90% of the (display) 1450N/A * XXX: No double-wide on 915GM pipe B. Is that the only reason for the 1450N/A /* Bspec claims that we can't use dithering for 30bpp pipes. */ 1450N/A /* Case prevented by intel_choose_pipe_bpp_dither. */ 1450N/A * Returns a set of divisors for the desired target clock with the given 1450N/A * refclk, or FALSE. The returned values represent the clock equation: 1450N/A * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 1450N/A /* Ensure that the cursor is valid for the new mode before changing... */ 1450N/A * Ensure we match the reduced clock's P to the target clock. 1450N/A * If the clocks don't match, we can't switch the display clock 1450N/A * by using the FP0/FP1. In such case we will disable the LVDS 1450N/A /* Compat-code for transition, will disappear. */ 1450N/A /* Set up the display plane register */ 1450N/A /* pipesrc and dspsize control the size that is scaled from, 1450N/A * which should always be the user's requested size. 1450N/A /* Check whether the pfit is attached to our pipe. */ 1450N/A * port and will be fixed up in the encoder->get_config 1450N/A /* We need to take the global config into account */ 1450N/A /* Ironlake: try to setup display ref clock before DPLL 1450N/A * enabling. This is only under driver's control after 1450N/A * PCH B stepping, previous chipset stepping should be 1450N/A * compute the final state we want first and check if we need to 1450N/A /* Always enable nonspread source */ 1450N/A /* SSC must be turned on before enabling the CPU output */ 1450N/A /* Get SSC going before enabling the outputs */ 1450N/A /* Enable CPU source on CPU attached eDP */ 1450N/A /* Turn off the SSC source */ 1450N/A/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ 1450N/A /* XXX: Rip out SDV support once Haswell ships for real. */ 1450N/A tmp |= (
0x3F <<
24) | (
0xF <<
20) | (
0xF <<
16);
1450N/A tmp |= (
0x3F <<
24) | (
0xF <<
20) | (
0xF <<
16);
1450N/A /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ 1450N/A * Initialize reference clocks when the driver loads 1450N/A /* Case prevented by intel_choose_pipe_bpp_dither. */ 1450N/A * Set up the pipe CSC unit. 1450N/A * Currently only full range RGB to limited range RGB conversion 1450N/A * is supported, but eventually this should handle various 1450N/A * RGB<->YCbCr scenarios as well. 1450N/A * TODO: Check what kind of values actually come out of the pipe 1450N/A * accuracy. Perhaps we even need to take the bpc value into 1450N/A coeff = ((
235 -
16) * (
1 <<
12) /
255) &
0xff8;
/* 0.xxx... */ 1450N/A * to BSpec, but reality doesn't agree. Just set them up in 1450N/A * a way that results in the correct picture. 1450N/A * Returns a set of divisors for the desired target clock with the given 1450N/A * refclk, or FALSE. The returned values represent the clock equation: 1450N/A * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 1450N/A * Ensure we match the reduced clock's P to the target clock. 1450N/A * If the clocks don't match, we can't switch the display clock 1450N/A * by using the FP0/FP1. In such case we will disable the LVDS 1450N/A * Account for spread spectrum to avoid 1450N/A * oversubscribing the link. Max center spread 1450N/A * is 2.5%; use 5% for safety's sake. 1450N/A /* Enable autotuning of the PLL clock (if permissible) */ 1450N/A /* compute bitmask from p1 value */ 1450N/A /* Compat-code for transition, will disappear. */ 1450N/A /* Ensure that the cursor is valid for the new mode before changing... */ 1450N/A /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1450N/A * We previously verified the shared_dpll in the eDP case, 1450N/A * so pll should not be NULL from above call. 1450N/A /* Wait for the clocks to stabilize. */ 1450N/A /* The pixel multiplier can only be updated once the 1450N/A * DPLL is enabled and the clocks are stable. 1450N/A /* Set up the display plane register */ 1450N/A /* We currently do not free assignements of panel fitters on 1450N/A * ivb/hsw (since we don't use the higher upscaling modes which 1450N/A * differentiates them) so just WARN about this case for now. */ 1450N/A /* XXX: Can't properly read out the pch dpll pixel multiplier 1450N/A * since we don't have state tracking for pch clocks yet. */ 1450N/A /* Ensure that the cursor is valid for the new mode before changing... */ 1450N/A /* Set up the display plane register */ 1450N/A * Haswell has only FDI/PCH transcoder A. It is which is connected to 1450N/A * DDI E. So just check whether this pipe is wired to DDI E and whether 1450N/A * the PCH transcoder is on. 1450N/A len = (i >>
9) &
0x1f;
/* ELD buffer size */ 1450N/A /* Wait for 1 vertical blank */ 1450N/A /* clear N_programing_enable and N_value_index */ 1450N/A eld[
5] |= (
1 <<
2);
/* Conn_Type, 0x1 = DisplayPort */ 1450N/A /* operate blindly on all ports */ 1450N/A eld[
5] |= (
1 <<
2);
/* Conn_Type, 0x1 = DisplayPort */ 1450N/A /* The clocks have to be on to load the palette. */ 1450N/A /* use legacy palette for Ironlake */ 1450N/A * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. 1450N/A for (i = 0; i <
256; i++) {
1450N/A /* On these chipsets we can only modify the base whilst 1450N/A /* XXX width must be 64, stride 256 => 0x00 << 28 */ 1450N/A /* and commit changes on next vblank */ 1450N/A /* and commit changes on next vblank */ 1450N/A/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 1450N/A /* if we want to turn off the cursor ignore width and height */ 1450N/A /* Currently we only support 64x64 cursors */ 1450N/A /* we only need to pin inside GTT if cursor is non-phy */ 1450N/A /* Note that the w/a also requires 2 PTE of padding following 1450N/A * the bo. We currently fill all unused PTE with the shadow 1450N/A * page and so we should always have valid PTE following the 1450N/A * cursor preventing the VT-d warning. 1450N/A/** Sets the color ramps on behalf of RandR */ 1450N/A/* VESA 640x480x72Hz mode to set on the pipe */ 1450N/A * Algorithm gets a little messy: 1450N/A * - if the connector already has an assigned crtc, use it (but make 1450N/A * - try to find the first unused crtc that can drive this connector, 1450N/A * and use that if we find one 1450N/A /* See if we already have a CRTC for this connector */ 1450N/A /* Make sure the crtc and connector are running */ 1450N/A /* Make sure the crtc and connector are running */ 1450N/A /* Find an unused one (if possible) */ 1450N/A * If we didn't find an unused CRTC, don't use any. 1450N/A /* We need a framebuffer large enough to accommodate all accesses 1450N/A * that the plane may generate whilst we perform load detection. 1450N/A * We can not rely on the fbcon either being present (we get called 1450N/A * during its initialisation to detect all boot displays, or it may 1450N/A * not even exist) or that it is large enough to satisfy the 1450N/A /* let the connector get through one full cycle before testing */ 1450N/A /* Switch crtc and encoder back off if necessary */ 1450N/A/* Returns the clock of the currently programmed mode of the given pipe. */ 1450N/A /* XXX: might not be 66MHz */ 1450N/A /* XXX: It would be nice to validate the clocks, but we can't reuse 1450N/A * i830PllIsValid() because it relies on the xf86_config connector 1450N/A * configuration being accurate, which it isn't necessarily. 1450N/A/** Returns the currently programmed mode of the given pipe. */ 1450N/A * Since this is called by a timer, we should never get here in 1450N/A /* Ignore early vblank irqs */ 1450N/A /* NB: An MMIO update of the plane base pointer will also 1450N/A * generate a page-flip completion irq, i.e. every modeset 1450N/A * is also accompanied by a spurious intel_prepare_page_flip(). 1450N/A /* Ensure that the work item is consistent when activating it ... */ 1450N/A /* and that it is marked active as soon as the irq could fire. */ 1450N/A /* Can't queue multiple flips, so wait for the previous 1450N/A * one to finish before executing the next. 1450N/A /* i965+ uses the linear or tiled offsets from the 1450N/A * Display Registers (which do not change across a page-flip) 1450N/A * so we need only reprogram the base address. 1450N/A /* XXX Enabling the panel-fitter across page-flip is so far 1450N/A * untested on non-native modes, so ignore it for now. 1450N/A * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 1450N/A /* Contrary to the suggestions in the documentation, 1450N/A * "Enable Panel Fitter" does not seem to be required when page 1450N/A * flipping with a non-native mode, and worse causes a normal 1450N/A * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 1450N/A * On gen7 we currently use the blit ring because (in early silicon at least) 1450N/A * the render ring doesn't give us interrpts for page flip completion, which 1450N/A * means clients will hang after the first flip is queued. Fortunately the 1450N/A * blit ring generates interrupts properly, so use it instead. 1450N/A /* Can't change pixel format via MI display flips. */ 1450N/A * Note that pitch changes could also affect these register. 1450N/A /* We borrow the event spin lock for protecting unpin_work */ 1450N/A /* Reference the objects for the scheduled work. */ 1450N/A * intel_modeset_update_staged_output_state 1450N/A * Updates the staged output configuration state, e.g. after we've read out the 1450N/A * intel_modeset_commit_output_state 1450N/A * This function copies the stage display pipe configuration to the real one. 1450N/A /* Don't use an invalid EDID bpc value */ 1450N/A /* Clamp bpp to 8 on screens without EDID 1.4 */ 1450N/A bpp =
8*
3;
/* since we go through a colormap */ 1450N/A /* checked in intel_framebuffer_init already */ 1450N/A /* checked in intel_framebuffer_init already */ 1450N/A /* checked in intel_framebuffer_init already */ 1450N/A /* TODO: gen4+ supports 16 bpc floating point, too. */ 1450N/A /* Clamp display bpp to EDID value */ 1450N/A /* Compute a starting value for pipe_config->pipe_bpp taking the source 1450N/A * plane pixel format and any sink constraints into account. Returns the 1450N/A * source plane bpp so that dithering can be selected on mismatches 1450N/A * after encoders and crtc also have had their say. */ 1450N/A /* Ensure the port clock defaults are reset when retrying. */ 1450N/A /* Pass our mode to the connectors and the CRTC to give them a chance to 1450N/A * adjust it according to limitations or connector properties, and also 1450N/A * a chance to reject the mode entirely. 1450N/A /* Set default port clock if not overwritten by the encoder. Needs to be 1450N/A * done afterwards in case the encoder adjusts the mode. */ 1450N/A/* Computes which crtcs are affected and sets the relevant bits in the mask. For 1450N/A * simplicity we use the crtc's pipe number (because it's easier to obtain). */ 1450N/A /* Check which crtcs have changed outputs connected to them, these need 1450N/A * to be part of the prepare_pipes mask. We don't (yet) support global 1450N/A * modeset across multiple crtcs, so modeset_pipes will only have one 1450N/A /* Check for any pipes that will be fully disabled ... */ 1450N/A /* Don't try to disable disabled crtcs. */ 1450N/A /* set_mode is also used to update properties on life display pipes. */ 1450N/A * For simplicity do a full modeset on any pipe where the output routing 1450N/A * changed. We could be more clever, but that would require us to be 1450N/A * more careful with calling the relevant encoder->mode_set functions. 1450N/A /* ... and mask these out. */ 1450N/A * HACK: We don't (yet) fully support global modesets. intel_set_config 1450N/A * obies this rule, but the modeset restore mode of 1450N/A * intel_modeset_setup_hw_state does not. 1450N/A /* Update computed state. */ 1450N/A "(expected 0x%08x, found 0x%08x)\n", \
1450N/A "(expected %i, found %i)\n", \
1450N/A "(expected %i, found %i)\n", \
1450N/A /* pfit ratios are autocomputed by the hw on gen4+ */ 1450N/A * ->get_hw_state callbacks. */ 1450N/A DRM_ERROR(
"connector's staged encoder doesn't match current encoder\n");
1450N/A "(expected %i, found %i)\n",
1450N/A DRM_ERROR(
"encoder's computed active state doesn't match tracked active state " 1450N/A "(expected %i, found %i)\n",
1450N/A "(expected %i, found %i)\n",
1450N/A DRM_ERROR(
"crtc's computed active state doesn't match tracked active state " 1450N/A DRM_ERROR(
"crtc's computed enabled state doesn't match tracked enabled state " 1450N/A /* hw state is inconsistent with the pipe A quirk */ 1450N/A /* Hack: Because we don't (yet) support global modeset on multiple 1450N/A * crtcs, we don't keep track of the new mode for more than one crtc. 1450N/A * Hence simply check whether any bit is set in modeset_pipes in all the 1450N/A * pieces of code that are not yet converted to deal with mutliple crtcs 1450N/A * changing their mode at the same time. */ 1450N/A /* crtc->mode is already used by the ->mode_set callbacks, hence we need 1450N/A * to set it here already despite that we pass it down the callchain. 1450N/A /* Only after disabling all output pipelines that will be changed can we 1450N/A * update the the output configuration. */ 1450N/A /* Set up the DPLL and any encoders state that needs to adjust or depend 1450N/A /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 1450N/A /* Store real post-adjustment hardware mode. */ 1450N/A /* Calculate and store various constants which 1450N/A * are later needed by vblank and swap-completion 1450N/A * timestamping. They are derived from true hwmode. 1450N/A /* FIXME: add subpixel order */ 1450N/A /* Copy data. Note that driver private data is not affected. 1450N/A * Should anything bad happen only the expected state is 1450N/A * restored, not the drivers personal bookkeeping. 1450N/A /* We should be able to check here if the fb has the same properties 1450N/A * and then just flip_or_move it */ 1450N/A /* If we have no fb then treat it as a full mode set */ 1450N/A /* The upper layers ensure that we either disabl a crtc or have a list 1450N/A * of connectors. For paranoia, double-check this. */ 1450N/A /* Otherwise traverse passed in connector list and get encoders 1450N/A /* If we disable the crtc, disable all its connectors. Also, if 1450N/A * the connector is on the changing crtc but not on the new 1450N/A * connector list, disable it. */ 1450N/A /* connector->new_encoder is now updated for all connectors. */ 1450N/A /* Update crtc of enabled connectors. */ 1450N/A /* Make sure the new CRTC will work with the encoder */ 1450N/A /* Check for any encoders that needs to be disabled. */ 1450N/A /* Only now check for crtc changes so we don't miss encoders 1450N/A * that will be disabled. */ 1450N/A /* Now we've also updated encoder->new_crtc for all encoders. */ 1450N/A /* Enforce sane interface api - has been abused by the fb helper. */ 1450N/A /* Compute whether we need a full modeset, only an fb base update or no 1450N/A * change at all. In the future we might also check whether only the 1450N/A * mode changed, e.g. for LVDS where we only change the panel fitter in 1450N/A /* Try to restore the config */ 1450N/A /* PCH refclock must be enabled first */ 1450N/A /* Make sure no transcoder isn't still depending on us. */ 1450N/A for (i = 0; i <
256; i++) {
1450N/A /* Swap pipes & planes for FBC on pre-965 */ 1450N/A /* Intel hw has only one MUX where enocoders could be cloned. */ 1450N/A /* Haswell uses DDI functions to detect digital outputs */ 1450N/A /* DDI A only supports eDP */ 1450N/A /* DDI B, C and D detection is indicated by the SFUSE_STRAP 1450N/A /* PCH SDVOB multiplex with HDMIB */ 1450N/A /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ 1450N/A /* Before G4X SDVOC doesn't have its own detect register */ 1450N/A /* XXX DSPC is limited to 4k tiled */ 1450N/A /* Reject formats not supported by any plane early. */ 1450N/A/* Set up chip specific display functions */ 1450N/A /* Returns the core display clock speed */ 1450N/A /* FIXME: detect B0+ stepping and use auto training */ 1450N/A /* Default just returns -ENODEV to indicate unsupported */ 1450N/A * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 1450N/A * resume, or other times. This quirk makes sure that's the case for 1450N/A * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 1450N/A * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight 1450N/A * Some machines (Dell XPS13) suffer broken backlight controls if 1450N/A * BLM_PCH_PWM_ENABLE is set. 1450N/A .
ident =
"NCR Corporation",
1450N/A { }
/* terminating entry */ 1450N/A /* HP Mini needs pipe A force quirk (LP: #322104) */ 1450N/A /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 1450N/A /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 1450N/A /* 830/845 need to leave pipe A & dpll A up */ 1450N/A /* Lenovo U160 cannot use SSC on LVDS */ 1450N/A /* Sony Vaio Y cannot use SSC on LVDS */ 1450N/A /* Acer Aspire 5734Z must invert backlight brightness */ 1450N/A /* Dell XPS13 HD Sandy Bridge */ 1450N/A /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ 1450N/A/* Disable the VGA plane that we never use */ 1450N/A /* OSOL_I915 intel_init_quirks(dev); */ 1450N/A /* Just disable it once at startup */ 1450N/A /* Just in case the BIOS is doing something questionable. */ 1450N/A /* We can't just switch on the pipe A, we need to set things up with a 1450N/A * proper mode and output configuration. As a gross hack, enable pipe A 1450N/A * by enabling the load detect pipe once. */ 1450N/A /* Clear any frame start delays used for debugging left by the BIOS */ 1450N/A /* We need to sanitize the plane -> pipe mapping first because this will 1450N/A * disable the crtc (and hence change the state) if it is wrong. Note 1450N/A * that gen4+ has a fixed plane -> pipe mapping. */ 1450N/A /* Pipe has the wrong plane attached and the plane is active. 1450N/A * Temporarily change the plane mapping and disable everything 1450N/A /* ... and break all links. */ 1450N/A /* BIOS forgot to enable pipe A, this mostly happens after 1450N/A * resume. Force-enable the pipe to fix this, the update_dpms 1450N/A * call below we restore the pipe to the right state, but leave 1450N/A /* Adjust the state of the output pipe according to whether we 1450N/A /* This can happen either due to bugs in the get_hw_state 1450N/A * functions or because the pipe is force-enabled due to the 1450N/A /* Because we only establish the connector -> encoder -> 1450N/A * crtc links if something is active, this means the 1450N/A * crtc is now deactivated. Break the links. connector 1450N/A * -> encoder links are only establish when things are 1450N/A * actually up, hence no need to break them. */ 1450N/A /* We need to check both for a crtc link (meaning that the 1450N/A * encoder is active and trying to read from a pipe) and the 1450N/A * pipe itself being active. */ 1450N/A /* Connector is active, but has no active pipe. This is 1450N/A * fallout from our resume register restoring. Disable 1450N/A * the encoder manually again. */ 1450N/A * a bug in one of the get_hw_state functions. Or someplace else 1450N/A * in our code, like the register restore mess on resume. Clamp 1450N/A * things to off as a safer default. */ 1450N/A /* Enabled encoders without active connectors will be fixed in 1450N/A /* FIXME: Smash this into the new shared dpll infrastructure. */ 1450N/A/* Scan out the current hw modeset state, sanitizes it and maps it into the drm 1450N/A * and i915 state tracking structures. */ 1450N/A /* HW state is read out, now we need to sanitize this mess. */ 1450N/A * We need to use raw interfaces for restoring state to avoid 1450N/A * checking (bogus) intermediate states. 1450N/A * Interrupts and polling as the first thing to avoid creating havoc. 1450N/A * Too much stuff here (turning of rps, connectors, ...) would 1450N/A * experience fancy races otherwise. 1450N/A /* OSOL_I915 cancel_work_sync(&dev_priv->hotplug_work); */ 1450N/A * Due to the hpd irq storm handling the hotplug work can re-arm the 1450N/A * poll handlers. Hence disable polling after hpd handling is shut down. 1450N/A /* flush any delayed tasks or pending work */ 1450N/A /* OSOL_I915 flush_scheduled_work(); */ 1450N/A /* destroy backlight, if any, before the connectors */ 1450N/A/* current intel driver doesn't take advantage of encoders 1450N/A always give back the encoder for the connector 1450N/A * set vga decode state - true == enable VGA decode 1450N/A /* In the code above we read the registers without checking if the power 1450N/A * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to 1450N/A * prevent the next I915_WRITE from detecting it and printing an error