Lines Matching refs:I915_READ
64 fbc_ctl = I915_READ(FBC_CONTROL);
72 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
127 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
152 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
163 dpfc_ctl = I915_READ(DPFC_CONTROL);
176 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
186 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
211 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
243 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
251 I915_READ(ILK_DSPCLK_GATE_D) &
257 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
268 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
291 I915_READ(ILK_DSPCLK_GATE_D) |
299 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
624 tmp = I915_READ(CLKCFG);
654 tmp = I915_READ(CSHRDDR3CTL);
793 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
815 uint32_t dsparb = I915_READ(DSPARB);
831 uint32_t dsparb = I915_READ(DSPARB);
848 uint32_t dsparb = I915_READ(DSPARB);
864 uint32_t dsparb = I915_READ(DSPARB);
1118 reg = I915_READ(DSPFW1);
1128 reg = I915_READ(DSPFW3);
1137 reg = I915_READ(DSPFW3);
1146 reg = I915_READ(DSPFW3);
1154 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1408 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1423 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1426 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1459 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1474 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1478 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1532 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1607 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1657 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1678 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1712 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1717 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1890 val = I915_READ(WM0_PIPEA_ILK);
1904 val = I915_READ(WM0_PIPEB_ILK);
1993 val = I915_READ(WM0_PIPEA_ILK);
2007 val = I915_READ(WM0_PIPEB_ILK);
2021 val = I915_READ(WM0_PIPEC_IVB);
2525 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2526 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2527 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2528 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2529 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2530 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2531 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2532 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2533 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2534 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2535 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2536 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2538 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2541 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2577 val = I915_READ(WM_MISC);
2586 val = I915_READ(DISP_ARB_CTL);
2767 val = I915_READ(reg);
2936 u32 rgvmodectl = I915_READ(MEMMODECTL);
2942 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2943 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2961 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2986 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2992 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2993 I915_READ(0x112e0);
2995 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3011 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3013 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3015 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3153 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3182 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
3237 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3244 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3245 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3344 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
3349 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3387 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3484 pcbr = I915_READ(VLV_PCBR);
3527 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3650 if (I915_READ(PWRCTXA)) {
3652 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3653 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3659 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3742 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3798 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3840 lcfuse = I915_READ(LCFUSE02);
3930 I915_READ(DSPCNTR(pipe)) |
3960 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3964 (I915_READ(DISP_ARB_CTL) |
3979 I915_READ(ILK_DISPLAY_CHICKEN1) |
3982 I915_READ(ILK_DISPLAY_CHICKEN2) |
3989 I915_READ(ILK_DISPLAY_CHICKEN2) |
4016 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4022 val = I915_READ(TRANS_CHICKEN2(pipe));
4044 tmp = I915_READ(MCH_SSKPD);
4060 I915_READ(ILK_DISPLAY_CHICKEN2) |
4080 I915_READ(GEN6_UCGCTL1) |
4116 I915_READ(ILK_DISPLAY_CHICKEN1) |
4119 I915_READ(ILK_DISPLAY_CHICKEN2) |
4122 I915_READ(ILK_DSPCLK_GATE_D) |
4127 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4144 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4167 I915_READ(SOUTH_DSPCLK_GATE_D) |
4172 I915_READ(_TRANSA_CHICKEN1) |
4181 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4213 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4226 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4230 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4234 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4285 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4307 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4313 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4323 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4358 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4362 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4371 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4375 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4480 u32 dstate = I915_READ(D_STATE);
4545 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4559 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4569 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4688 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4728 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5080 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5088 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5094 *val = I915_READ(GEN6_PCODE_DATA);
5104 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5112 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,