1450N/A/*
1450N/A * Copyright © 2012-2013 Intel Corporation
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice (including the next
1450N/A * paragraph) shall be included in all copies or substantial portions of the
1450N/A * Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
1450N/A * IN THE SOFTWARE.
1450N/A *
1450N/A * Authors:
1450N/A * Eugeni Dodonov <eugeni.dodonov@intel.com>
1450N/A *
1450N/A */
1450N/A
1450N/A/*
1450N/A * Copyright (c) 2013, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A#include "drmP.h"
1450N/A#include "i915_drv.h"
1450N/A#include "intel_drv.h"
1450N/A#include <sys/archsystm.h>
1450N/A
1450N/A#define FORCEWAKE_ACK_TIMEOUT_MS 2
1450N/A
1450N/A/* FBC, or Frame Buffer Compression, is a technique employed to compress the
1450N/A * framebuffer contents in-memory, aiming at reducing the required bandwidth
1450N/A * during in-memory transfers and, therefore, reduce the power packet.
1450N/A *
1450N/A * The benefits of FBC are mostly visible with solid backgrounds and
1450N/A * variation-less patterns.
1450N/A *
1450N/A * FBC-related functionality can be enabled by the means of the
1450N/A * i915.i915_enable_fbc parameter
1450N/A */
1450N/A
1450N/Astatic bool intel_crtc_active(struct drm_crtc *crtc)
1450N/A{
1450N/A /* Be paranoid as we can arrive here with only partial
1450N/A * state retrieved from the hardware during setup.
1450N/A */
1450N/A return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
1450N/A}
1450N/A
1450N/Astatic void i8xx_disable_fbc(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 fbc_ctl;
1450N/A
1450N/A /* Disable compression */
1450N/A fbc_ctl = I915_READ(FBC_CONTROL);
1450N/A if ((fbc_ctl & FBC_CTL_EN) == 0)
1450N/A return;
1450N/A
1450N/A fbc_ctl &= ~FBC_CTL_EN;
1450N/A I915_WRITE(FBC_CONTROL, fbc_ctl);
1450N/A
1450N/A /* Wait for compressing bit to clear */
1450N/A if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1450N/A DRM_DEBUG_KMS("FBC idle timed out\n");
1450N/A return;
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("disabled FBC\n");
1450N/A}
1450N/A
1450N/Astatic void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1450N/A{
1450N/A struct drm_device *dev = crtc->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_framebuffer *fb = crtc->fb;
1450N/A struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1450N/A struct drm_i915_gem_object *obj = intel_fb->obj;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A int cfb_pitch;
1450N/A int plane, i;
1450N/A u32 fbc_ctl, fbc_ctl2;
1450N/A
1450N/A cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1450N/A if (fb->pitches[0] < cfb_pitch)
1450N/A cfb_pitch = fb->pitches[0];
1450N/A
1450N/A /* FBC_CTL wants 64B units */
1450N/A cfb_pitch = (cfb_pitch / 64) - 1;
1450N/A plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1450N/A
1450N/A /* Clear old tags */
1450N/A for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1450N/A I915_WRITE(FBC_TAG + (i * 4), 0);
1450N/A
1450N/A /* Set it up... */
1450N/A fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1450N/A fbc_ctl2 |= plane;
1450N/A I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1450N/A I915_WRITE(FBC_FENCE_OFF, crtc->y);
1450N/A
1450N/A /* enable it... */
1450N/A fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1450N/A if (IS_I945GM(dev))
1450N/A fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1450N/A fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1450N/A fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1450N/A fbc_ctl |= obj->fence_reg;
1450N/A I915_WRITE(FBC_CONTROL, fbc_ctl);
1450N/A
1450N/A DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
1450N/A cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
1450N/A}
1450N/A
1450N/Astatic bool i8xx_fbc_enabled(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1450N/A}
1450N/A
1450N/Astatic void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1450N/A{
1450N/A struct drm_device *dev = crtc->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_framebuffer *fb = crtc->fb;
1450N/A struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1450N/A struct drm_i915_gem_object *obj = intel_fb->obj;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1450N/A unsigned long stall_watermark = 200;
1450N/A u32 dpfc_ctl;
1450N/A
1450N/A dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1450N/A dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1450N/A I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1450N/A
1450N/A I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1450N/A (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1450N/A (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1450N/A I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1450N/A
1450N/A /* enable it... */
1450N/A I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1450N/A
1450N/A DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
1450N/A}
1450N/A
1450N/Astatic void g4x_disable_fbc(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 dpfc_ctl;
1450N/A
1450N/A /* Disable compression */
1450N/A dpfc_ctl = I915_READ(DPFC_CONTROL);
1450N/A if (dpfc_ctl & DPFC_CTL_EN) {
1450N/A dpfc_ctl &= ~DPFC_CTL_EN;
1450N/A I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1450N/A
1450N/A DRM_DEBUG_KMS("disabled FBC\n");
1450N/A }
1450N/A}
1450N/A
1450N/Astatic bool g4x_fbc_enabled(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1450N/A}
1450N/A
1450N/Astatic void sandybridge_blit_fbc_update(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 blt_ecoskpd;
1450N/A
1450N/A /* Make sure blitter notifies FBC of writes */
1450N/A gen6_gt_force_wake_get(dev_priv);
1450N/A blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1450N/A blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1450N/A GEN6_BLITTER_LOCK_SHIFT;
1450N/A I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1450N/A blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1450N/A I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1450N/A blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1450N/A GEN6_BLITTER_LOCK_SHIFT);
1450N/A I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1450N/A POSTING_READ(GEN6_BLITTER_ECOSKPD);
1450N/A gen6_gt_force_wake_put(dev_priv);
1450N/A}
1450N/A
1450N/Astatic void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1450N/A{
1450N/A struct drm_device *dev = crtc->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_framebuffer *fb = crtc->fb;
1450N/A struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1450N/A struct drm_i915_gem_object *obj = intel_fb->obj;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1450N/A unsigned long stall_watermark = 200;
1450N/A u32 dpfc_ctl;
1450N/A
1450N/A dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1450N/A dpfc_ctl &= DPFC_RESERVED;
1450N/A dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1450N/A /* Set persistent mode for front-buffer rendering, ala X. */
1450N/A dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1450N/A dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1450N/A I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1450N/A
1450N/A I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1450N/A (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1450N/A (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1450N/A I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1450N/A I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1450N/A /* enable it... */
1450N/A I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1450N/A
1450N/A if (IS_GEN6(dev)) {
1450N/A I915_WRITE(SNB_DPFC_CTL_SA,
1450N/A SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1450N/A I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1450N/A sandybridge_blit_fbc_update(dev);
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
1450N/A}
1450N/A
1450N/Astatic void ironlake_disable_fbc(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 dpfc_ctl;
1450N/A
1450N/A /* Disable compression */
1450N/A dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1450N/A if (dpfc_ctl & DPFC_CTL_EN) {
1450N/A dpfc_ctl &= ~DPFC_CTL_EN;
1450N/A I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1450N/A
1450N/A if (IS_IVYBRIDGE(dev))
1450N/A /* WaFbcDisableDpfcClockGating:ivb */
1450N/A I915_WRITE(ILK_DSPCLK_GATE_D,
1450N/A I915_READ(ILK_DSPCLK_GATE_D) &
1450N/A ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A if (IS_HASWELL(dev))
1450N/A /* WaFbcDisableDpfcClockGating:hsw */
1450N/A I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
1450N/A I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
1450N/A ~HSW_DPFC_GATING_DISABLE);
1450N/A
1450N/A DRM_DEBUG_KMS("disabled FBC\n");
1450N/A }
1450N/A}
1450N/A
1450N/Astatic bool ironlake_fbc_enabled(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1450N/A}
1450N/A
1450N/Astatic void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1450N/A{
1450N/A struct drm_device *dev = crtc->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_framebuffer *fb = crtc->fb;
1450N/A struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1450N/A struct drm_i915_gem_object *obj = intel_fb->obj;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A
1450N/A I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset);
1450N/A
1450N/A I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
1450N/A IVB_DPFC_CTL_FENCE_EN |
1450N/A intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
1450N/A
1450N/A if (IS_IVYBRIDGE(dev)) {
1450N/A /* WaFbcAsynchFlipDisableFbcQueue:ivb */
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
1450N/A /* WaFbcDisableDpfcClockGating:ivb */
1450N/A I915_WRITE(ILK_DSPCLK_GATE_D,
1450N/A I915_READ(ILK_DSPCLK_GATE_D) |
1450N/A ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
1450N/A } else {
1450N/A /* WaFbcAsynchFlipDisableFbcQueue:hsw */
1450N/A I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
1450N/A HSW_BYPASS_FBC_QUEUE);
1450N/A /* WaFbcDisableDpfcClockGating:hsw */
1450N/A I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
1450N/A I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
1450N/A HSW_DPFC_GATING_DISABLE);
1450N/A }
1450N/A
1450N/A I915_WRITE(SNB_DPFC_CTL_SA,
1450N/A SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1450N/A I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1450N/A
1450N/A sandybridge_blit_fbc_update(dev);
1450N/A
1450N/A DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1450N/A}
1450N/A
1450N/Abool intel_fbc_enabled(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (!dev_priv->display.fbc_enabled)
1450N/A return false;
1450N/A
1450N/A return dev_priv->display.fbc_enabled(dev);
1450N/A}
1450N/A
1450N/Astatic void intel_fbc_work_fn(struct work_struct *arg)
1450N/A{
1450N/A struct intel_fbc_work *work = container_of(arg, struct intel_fbc_work,
1450N/A work);
1450N/A struct drm_device *dev = work->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A mutex_lock(&dev->struct_mutex);
1450N/A if (work == dev_priv->fbc_work) {
1450N/A /* Double check that we haven't switched fb without cancelling
1450N/A * the prior work.
1450N/A */
1450N/A if (work->crtc->fb == work->fb) {
1450N/A dev_priv->display.enable_fbc(work->crtc,
1450N/A work->interval);
1450N/A
1450N/A dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1450N/A dev_priv->cfb_fb = work->crtc->fb->base.id;
1450N/A dev_priv->cfb_y = work->crtc->y;
1450N/A }
1450N/A
1450N/A dev_priv->fbc_work = NULL;
1450N/A }
1450N/A mutex_unlock(&dev->struct_mutex);
1450N/A
1450N/A kfree(work, sizeof(struct intel_fbc_work));
1450N/A}
1450N/A
1450N/Avoid
1450N/Aintel_fbc_work_timer(void *device)
1450N/A{
1450N/A struct intel_fbc_work *work = (struct intel_fbc_work *)device;
1450N/A struct drm_device *dev = work->dev;
1450N/A drm_i915_private_t *dev_priv = dev->dev_private;
1450N/A queue_work(dev_priv->other_wq, &work->work);
1450N/A}
1450N/A
1450N/Astatic void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A if (dev_priv->fbc_work == NULL)
1450N/A return;
1450N/A
1450N/A DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1450N/A
1450N/A /* Synchronisation is provided by struct_mutex and checking of
1450N/A * dev_priv->fbc_work, so we can perform the cancellation
1450N/A * entirely asynchronously.
1450N/A */
1450N/A del_timer_sync(&dev_priv->fbc_timer);
1450N/A cancel_delayed_work(dev_priv->other_wq);
1450N/A /* tasklet was killed before being run, clean up */
1450N/A kfree(dev_priv->fbc_work, sizeof(struct intel_fbc_work));
1450N/A
1450N/A /* Mark the work as no longer wanted so that if it does
1450N/A * wake-up (because the work was already running and waiting
1450N/A * for our mutex), it will discover that is no longer
1450N/A * necessary to run.
1450N/A */
1450N/A dev_priv->fbc_work = NULL;
1450N/A}
1450N/A
1450N/Avoid intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1450N/A{
1450N/A struct intel_fbc_work *work;
1450N/A struct drm_device *dev = crtc->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (!dev_priv->display.enable_fbc)
1450N/A return;
1450N/A
1450N/A intel_cancel_fbc_work(dev_priv);
1450N/A
1450N/A work = kzalloc(sizeof *work, GFP_KERNEL);
1450N/A if (work == NULL) {
1450N/A dev_priv->display.enable_fbc(crtc, interval);
1450N/A return;
1450N/A }
1450N/A
1450N/A work->dev = crtc->dev;
1450N/A work->crtc = crtc;
1450N/A work->fb = crtc->fb;
1450N/A work->interval = interval;
1450N/A
1450N/A INIT_WORK(&work->work, intel_fbc_work_fn);
1450N/A setup_timer(&dev_priv->fbc_timer, intel_fbc_work_timer,
1450N/A (void *)work);
1450N/A
1450N/A dev_priv->fbc_work = work;
1450N/A
1450N/A DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1450N/A
1450N/A /* Delay the actual enabling to let pageflipping cease and the
1450N/A * display to settle before starting the compression. Note that
1450N/A * this delay also serves a second purpose: it allows for a
1450N/A * vblank to pass after disabling the FBC before we attempt
1450N/A * to modify the control registers.
1450N/A *
1450N/A * A more complicated solution would involve tracking vblanks
1450N/A * following the termination of the page-flipping sequence
1450N/A * and indeed performing the enable as a co-routine and not
1450N/A * waiting synchronously upon the vblank.
1450N/A */
1450N/A test_set_timer(&dev_priv->fbc_timer, msecs_to_jiffies(50));
1450N/A}
1450N/A
1450N/Avoid intel_disable_fbc(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A intel_cancel_fbc_work(dev_priv);
1450N/A
1450N/A if (!dev_priv->display.disable_fbc)
1450N/A return;
1450N/A
1450N/A dev_priv->display.disable_fbc(dev);
1450N/A dev_priv->cfb_plane = -1;
1450N/A}
1450N/A
1450N/A/**
1450N/A * intel_update_fbc - enable/disable FBC as needed
1450N/A * @mode: mode in use
1450N/A *
1450N/A * Set up the framebuffer compression hardware at mode set time. We
1450N/A * enable it if possible:
1450N/A * - plane A only (on pre-965)
1450N/A * - no pixel multiply/line duplication
1450N/A * - no alpha buffer discard
1450N/A * - no dual wide
1450N/A * - framebuffer <= 2048 in width, 1536 in height
1450N/A *
1450N/A * We can't assume that any compression will take place (worst case),
1450N/A * so the compressed buffer has to be the same size as the uncompressed
1450N/A * one. It also must reside (along with the line length buffer) in
1450N/A * stolen memory.
1450N/A *
1450N/A * We need to enable/disable FBC on a global basis.
1450N/A */
1450N/Avoid intel_update_fbc(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_crtc *crtc = NULL, *tmp_crtc;
1450N/A struct intel_crtc *intel_crtc;
1450N/A struct drm_framebuffer *fb;
1450N/A struct intel_framebuffer *intel_fb;
1450N/A struct drm_i915_gem_object *obj;
1450N/A int enable_fbc;
1450N/A unsigned int max_hdisplay, max_vdisplay;
1450N/A
1450N/A if (!i915_powersave)
1450N/A return;
1450N/A
1450N/A if (!I915_HAS_FBC(dev))
1450N/A return;
1450N/A
1450N/A /*
1450N/A * If FBC is already on, we just have to verify that we can
1450N/A * keep it that way...
1450N/A * Need to disable if:
1450N/A * - more than one pipe is active
1450N/A * - changing FBC params (stride, fence, mode)
1450N/A * - new fb is too large to fit in compressed buffer
1450N/A * - going to an unsupported config (interlace, pixel multiply, etc.)
1450N/A */
1450N/A list_for_each_entry(tmp_crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
1450N/A if (intel_crtc_active(tmp_crtc) &&
1450N/A !to_intel_crtc(tmp_crtc)->primary_disabled) {
1450N/A if (crtc) {
1450N/A DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1450N/A dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1450N/A goto out_disable;
1450N/A }
1450N/A crtc = tmp_crtc;
1450N/A }
1450N/A }
1450N/A
1450N/A if (!crtc || crtc->fb == NULL) {
1450N/A DRM_DEBUG_KMS("no output, disabling\n");
1450N/A dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1450N/A goto out_disable;
1450N/A }
1450N/A
1450N/A intel_crtc = to_intel_crtc(crtc);
1450N/A fb = crtc->fb;
1450N/A intel_fb = to_intel_framebuffer(fb);
1450N/A obj = intel_fb->obj;
1450N/A
1450N/A enable_fbc = i915_enable_fbc;
1450N/A if (enable_fbc < 0) {
1450N/A DRM_DEBUG_KMS("fbc set to per-chip default\n");
1450N/A enable_fbc = 1;
1450N/A if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1450N/A enable_fbc = 0;
1450N/A }
1450N/A if (!enable_fbc) {
1450N/A DRM_DEBUG_KMS("fbc disabled per module param\n");
1450N/A dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1450N/A goto out_disable;
1450N/A }
1450N/A if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1450N/A (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1450N/A DRM_DEBUG_KMS("mode incompatible with compression, "
1450N/A "disabling\n");
1450N/A dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1450N/A goto out_disable;
1450N/A }
1450N/A
1450N/A if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1450N/A max_hdisplay = 4096;
1450N/A max_vdisplay = 2048;
1450N/A } else {
1450N/A max_hdisplay = 2048;
1450N/A max_vdisplay = 1536;
1450N/A }
1450N/A if ((crtc->mode.hdisplay > max_hdisplay) ||
1450N/A (crtc->mode.vdisplay > max_vdisplay)) {
1450N/A DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1450N/A dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1450N/A goto out_disable;
1450N/A }
1450N/A if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
1450N/A intel_crtc->plane != 0) {
1450N/A DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1450N/A dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1450N/A goto out_disable;
1450N/A }
1450N/A
1450N/A /* The use of a CPU fence is mandatory in order to detect writes
1450N/A * by the CPU to the scanout and trigger updates to the FBC.
1450N/A */
1450N/A if (obj->tiling_mode != I915_TILING_X ||
1450N/A obj->fence_reg == I915_FENCE_REG_NONE) {
1450N/A DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1450N/A dev_priv->no_fbc_reason = FBC_NOT_TILED;
1450N/A goto out_disable;
1450N/A }
1450N/A
1450N/A /* If the kernel debugger is active, always disable compression */
1450N/A /*LINTED*/
1450N/A if (in_dbg_master())
1450N/A goto out_disable;
1450N/A
1450N/A if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
1450N/A DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
1450N/A dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1450N/A goto out_disable;
1450N/A }
1450N/A
1450N/A /* If the scanout has not changed, don't modify the FBC settings.
1450N/A * Note that we make the fundamental assumption that the fb->obj
1450N/A * cannot be unpinned (and have its GTT offset and fence revoked)
1450N/A * without first being decoupled from the scanout and FBC disabled.
1450N/A */
1450N/A if (dev_priv->cfb_plane == intel_crtc->plane &&
1450N/A dev_priv->cfb_fb == fb->base.id &&
1450N/A dev_priv->cfb_y == crtc->y)
1450N/A return;
1450N/A
1450N/A if (intel_fbc_enabled(dev)) {
1450N/A /* We update FBC along two paths, after changing fb/crtc
1450N/A * configuration (modeswitching) and after page-flipping
1450N/A * finishes. For the latter, we know that not only did
1450N/A * we disable the FBC at the start of the page-flip
1450N/A * sequence, but also more than one vblank has passed.
1450N/A *
1450N/A * For the former case of modeswitching, it is possible
1450N/A * to switch between two FBC valid configurations
1450N/A * instantaneously so we do need to disable the FBC
1450N/A * before we can modify its control registers. We also
1450N/A * have to wait for the next vblank for that to take
1450N/A * effect. However, since we delay enabling FBC we can
1450N/A * assume that a vblank has passed since disabling and
1450N/A * that we can safely alter the registers in the deferred
1450N/A * callback.
1450N/A *
1450N/A * In the scenario that we go from a valid to invalid
1450N/A * and then back to valid FBC configuration we have
1450N/A * no strict enforcement that a vblank occurred since
1450N/A * disabling the FBC. However, along all current pipe
1450N/A * disabling paths we do need to wait for a vblank at
1450N/A * some point. And we wait before enabling FBC anyway.
1450N/A */
1450N/A DRM_DEBUG_KMS("disabling active FBC for update\n");
1450N/A intel_disable_fbc(dev);
1450N/A }
1450N/A
1450N/A intel_enable_fbc(crtc, 500);
1450N/A return;
1450N/A
1450N/Aout_disable:
1450N/A /* Multiple disables should be harmless */
1450N/A if (intel_fbc_enabled(dev)) {
1450N/A DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1450N/A intel_disable_fbc(dev);
1450N/A }
1450N/A i915_gem_stolen_cleanup_compression(dev);
1450N/A}
1450N/A
1450N/Astatic void i915_pineview_get_mem_freq(struct drm_device *dev)
1450N/A{
1450N/A drm_i915_private_t *dev_priv = dev->dev_private;
1450N/A u32 tmp;
1450N/A
1450N/A tmp = I915_READ(CLKCFG);
1450N/A
1450N/A switch (tmp & CLKCFG_FSB_MASK) {
1450N/A case CLKCFG_FSB_533:
1450N/A dev_priv->fsb_freq = 533; /* 133*4 */
1450N/A break;
1450N/A case CLKCFG_FSB_800:
1450N/A dev_priv->fsb_freq = 800; /* 200*4 */
1450N/A break;
1450N/A case CLKCFG_FSB_667:
1450N/A dev_priv->fsb_freq = 667; /* 167*4 */
1450N/A break;
1450N/A case CLKCFG_FSB_400:
1450N/A dev_priv->fsb_freq = 400; /* 100*4 */
1450N/A break;
1450N/A }
1450N/A
1450N/A switch (tmp & CLKCFG_MEM_MASK) {
1450N/A case CLKCFG_MEM_533:
1450N/A dev_priv->mem_freq = 533;
1450N/A break;
1450N/A case CLKCFG_MEM_667:
1450N/A dev_priv->mem_freq = 667;
1450N/A break;
1450N/A case CLKCFG_MEM_800:
1450N/A dev_priv->mem_freq = 800;
1450N/A break;
1450N/A }
1450N/A
1450N/A /* detect pineview DDR3 setting */
1450N/A tmp = I915_READ(CSHRDDR3CTL);
1450N/A dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1450N/A}
1450N/A
1450N/Astatic void i915_ironlake_get_mem_freq(struct drm_device *dev)
1450N/A{
1450N/A drm_i915_private_t *dev_priv = dev->dev_private;
1450N/A u16 ddrpll, csipll;
1450N/A
1450N/A ddrpll = I915_READ16(DDRMPLL1);
1450N/A csipll = I915_READ16(CSIPLL0);
1450N/A
1450N/A switch (ddrpll & 0xff) {
1450N/A case 0xc:
1450N/A dev_priv->mem_freq = 800;
1450N/A break;
1450N/A case 0x10:
1450N/A dev_priv->mem_freq = 1066;
1450N/A break;
1450N/A case 0x14:
1450N/A dev_priv->mem_freq = 1333;
1450N/A break;
1450N/A case 0x18:
1450N/A dev_priv->mem_freq = 1600;
1450N/A break;
1450N/A default:
1450N/A DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1450N/A ddrpll & 0xff);
1450N/A dev_priv->mem_freq = 0;
1450N/A break;
1450N/A }
1450N/A
1450N/A dev_priv->ips.r_t = dev_priv->mem_freq;
1450N/A
1450N/A switch (csipll & 0x3ff) {
1450N/A case 0x00c:
1450N/A dev_priv->fsb_freq = 3200;
1450N/A break;
1450N/A case 0x00e:
1450N/A dev_priv->fsb_freq = 3733;
1450N/A break;
1450N/A case 0x010:
1450N/A dev_priv->fsb_freq = 4266;
1450N/A break;
1450N/A case 0x012:
1450N/A dev_priv->fsb_freq = 4800;
1450N/A break;
1450N/A case 0x014:
1450N/A dev_priv->fsb_freq = 5333;
1450N/A break;
1450N/A case 0x016:
1450N/A dev_priv->fsb_freq = 5866;
1450N/A break;
1450N/A case 0x018:
1450N/A dev_priv->fsb_freq = 6400;
1450N/A break;
1450N/A default:
1450N/A DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1450N/A csipll & 0x3ff);
1450N/A dev_priv->fsb_freq = 0;
1450N/A break;
1450N/A }
1450N/A
1450N/A if (dev_priv->fsb_freq == 3200) {
1450N/A dev_priv->ips.c_m = 0;
1450N/A } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1450N/A dev_priv->ips.c_m = 1;
1450N/A } else {
1450N/A dev_priv->ips.c_m = 2;
1450N/A }
1450N/A}
1450N/A
1450N/Astatic const struct cxsr_latency cxsr_latency_table[] = {
1450N/A {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
1450N/A {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
1450N/A {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
1450N/A {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
1450N/A {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
1450N/A
1450N/A {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
1450N/A {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
1450N/A {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
1450N/A {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
1450N/A {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
1450N/A
1450N/A {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
1450N/A {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
1450N/A {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
1450N/A {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
1450N/A {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
1450N/A
1450N/A {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
1450N/A {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
1450N/A {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
1450N/A {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
1450N/A {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
1450N/A
1450N/A {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
1450N/A {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
1450N/A {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
1450N/A {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
1450N/A {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
1450N/A
1450N/A {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
1450N/A {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
1450N/A {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
1450N/A {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
1450N/A {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
1450N/A};
1450N/A
1450N/Astatic const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
1450N/A int is_ddr3,
1450N/A int fsb,
1450N/A int mem)
1450N/A{
1450N/A const struct cxsr_latency *latency;
1450N/A int i;
1450N/A
1450N/A if (fsb == 0 || mem == 0)
1450N/A return NULL;
1450N/A
1450N/A for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1450N/A latency = &cxsr_latency_table[i];
1450N/A if (is_desktop == latency->is_desktop &&
1450N/A is_ddr3 == latency->is_ddr3 &&
1450N/A fsb == latency->fsb_freq && mem == latency->mem_freq)
1450N/A return latency;
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1450N/A
1450N/A return NULL;
1450N/A}
1450N/A
1450N/Astatic void pineview_disable_cxsr(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A /* deactivate cxsr */
1450N/A I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
1450N/A}
1450N/A
1450N/A/*
1450N/A * Latency for FIFO fetches is dependent on several factors:
1450N/A * - memory configuration (speed, channels)
1450N/A * - chipset
1450N/A * - current MCH state
1450N/A * It can be fairly high in some situations, so here we assume a fairly
1450N/A * pessimal value. It's a tradeoff between extra memory fetches (if we
1450N/A * set this value too high, the FIFO will fetch frequently to stay full)
1450N/A * and power consumption (set it too low to save power and we might see
1450N/A * FIFO underruns and display "flicker").
1450N/A *
1450N/A * A value of 5us seems to be a good balance; safe for very low end
1450N/A * platforms but not overly aggressive on lower latency configs.
1450N/A */
1450N/Astatic const int latency_ns = 5000;
1450N/A
1450N/Astatic int i9xx_get_fifo_size(struct drm_device *dev, int plane)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t dsparb = I915_READ(DSPARB);
1450N/A int size;
1450N/A
1450N/A size = dsparb & 0x7f;
1450N/A if (plane)
1450N/A size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
1450N/A
1450N/A DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
1450N/A plane ? "B" : "A", size);
1450N/A
1450N/A return size;
1450N/A}
1450N/A
1450N/Astatic int i85x_get_fifo_size(struct drm_device *dev, int plane)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t dsparb = I915_READ(DSPARB);
1450N/A int size;
1450N/A
1450N/A size = dsparb & 0x1ff;
1450N/A if (plane)
1450N/A size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
1450N/A size >>= 1; /* Convert to cachelines */
1450N/A
1450N/A DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
1450N/A plane ? "B" : "A", size);
1450N/A
1450N/A return size;
1450N/A}
1450N/A
1450N/Astatic int i845_get_fifo_size(struct drm_device *dev, int plane)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t dsparb = I915_READ(DSPARB);
1450N/A int size;
1450N/A
1450N/A size = dsparb & 0x7f;
1450N/A size >>= 2; /* Convert to cachelines */
1450N/A
1450N/A DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
1450N/A plane ? "B" : "A",
1450N/A size);
1450N/A
1450N/A return size;
1450N/A}
1450N/A
1450N/Astatic int i830_get_fifo_size(struct drm_device *dev, int plane)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t dsparb = I915_READ(DSPARB);
1450N/A int size;
1450N/A
1450N/A size = dsparb & 0x7f;
1450N/A size >>= 1; /* Convert to cachelines */
1450N/A
1450N/A DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
1450N/A plane ? "B" : "A", size);
1450N/A
1450N/A return size;
1450N/A}
1450N/A
1450N/A/* Pineview has different values for various configs */
1450N/Astatic const struct intel_watermark_params pineview_display_wm = {
1450N/A PINEVIEW_DISPLAY_FIFO,
1450N/A PINEVIEW_MAX_WM,
1450N/A PINEVIEW_DFT_WM,
1450N/A PINEVIEW_GUARD_WM,
1450N/A PINEVIEW_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params pineview_display_hplloff_wm = {
1450N/A PINEVIEW_DISPLAY_FIFO,
1450N/A PINEVIEW_MAX_WM,
1450N/A PINEVIEW_DFT_HPLLOFF_WM,
1450N/A PINEVIEW_GUARD_WM,
1450N/A PINEVIEW_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params pineview_cursor_wm = {
1450N/A PINEVIEW_CURSOR_FIFO,
1450N/A PINEVIEW_CURSOR_MAX_WM,
1450N/A PINEVIEW_CURSOR_DFT_WM,
1450N/A PINEVIEW_CURSOR_GUARD_WM,
1450N/A PINEVIEW_FIFO_LINE_SIZE,
1450N/A};
1450N/Astatic const struct intel_watermark_params pineview_cursor_hplloff_wm = {
1450N/A PINEVIEW_CURSOR_FIFO,
1450N/A PINEVIEW_CURSOR_MAX_WM,
1450N/A PINEVIEW_CURSOR_DFT_WM,
1450N/A PINEVIEW_CURSOR_GUARD_WM,
1450N/A PINEVIEW_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params g4x_wm_info = {
1450N/A G4X_FIFO_SIZE,
1450N/A G4X_MAX_WM,
1450N/A G4X_MAX_WM,
1450N/A 2,
1450N/A G4X_FIFO_LINE_SIZE,
1450N/A};
1450N/Astatic const struct intel_watermark_params g4x_cursor_wm_info = {
1450N/A I965_CURSOR_FIFO,
1450N/A I965_CURSOR_MAX_WM,
1450N/A I965_CURSOR_DFT_WM,
1450N/A 2,
1450N/A G4X_FIFO_LINE_SIZE,
1450N/A};
1450N/Astatic const struct intel_watermark_params valleyview_wm_info = {
1450N/A VALLEYVIEW_FIFO_SIZE,
1450N/A VALLEYVIEW_MAX_WM,
1450N/A VALLEYVIEW_MAX_WM,
1450N/A 2,
1450N/A G4X_FIFO_LINE_SIZE,
1450N/A};
1450N/Astatic const struct intel_watermark_params valleyview_cursor_wm_info = {
1450N/A I965_CURSOR_FIFO,
1450N/A VALLEYVIEW_CURSOR_MAX_WM,
1450N/A I965_CURSOR_DFT_WM,
1450N/A 2,
1450N/A G4X_FIFO_LINE_SIZE,
1450N/A};
1450N/Astatic const struct intel_watermark_params i965_cursor_wm_info = {
1450N/A I965_CURSOR_FIFO,
1450N/A I965_CURSOR_MAX_WM,
1450N/A I965_CURSOR_DFT_WM,
1450N/A 2,
1450N/A I915_FIFO_LINE_SIZE,
1450N/A};
1450N/Astatic const struct intel_watermark_params i945_wm_info = {
1450N/A I945_FIFO_SIZE,
1450N/A I915_MAX_WM,
1450N/A 1,
1450N/A 2,
1450N/A I915_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params i915_wm_info = {
1450N/A I915_FIFO_SIZE,
1450N/A I915_MAX_WM,
1450N/A 1,
1450N/A 2,
1450N/A I915_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params i855_wm_info = {
1450N/A I855GM_FIFO_SIZE,
1450N/A I915_MAX_WM,
1450N/A 1,
1450N/A 2,
1450N/A I830_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params i830_wm_info = {
1450N/A I830_FIFO_SIZE,
1450N/A I915_MAX_WM,
1450N/A 1,
1450N/A 2,
1450N/A I830_FIFO_LINE_SIZE
1450N/A};
1450N/A
1450N/Astatic const struct intel_watermark_params ironlake_display_wm_info = {
1450N/A ILK_DISPLAY_FIFO,
1450N/A ILK_DISPLAY_MAXWM,
1450N/A ILK_DISPLAY_DFTWM,
1450N/A 2,
1450N/A ILK_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params ironlake_cursor_wm_info = {
1450N/A ILK_CURSOR_FIFO,
1450N/A ILK_CURSOR_MAXWM,
1450N/A ILK_CURSOR_DFTWM,
1450N/A 2,
1450N/A ILK_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params ironlake_display_srwm_info = {
1450N/A ILK_DISPLAY_SR_FIFO,
1450N/A ILK_DISPLAY_MAX_SRWM,
1450N/A ILK_DISPLAY_DFT_SRWM,
1450N/A 2,
1450N/A ILK_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params ironlake_cursor_srwm_info = {
1450N/A ILK_CURSOR_SR_FIFO,
1450N/A ILK_CURSOR_MAX_SRWM,
1450N/A ILK_CURSOR_DFT_SRWM,
1450N/A 2,
1450N/A ILK_FIFO_LINE_SIZE
1450N/A};
1450N/A
1450N/Astatic const struct intel_watermark_params sandybridge_display_wm_info = {
1450N/A SNB_DISPLAY_FIFO,
1450N/A SNB_DISPLAY_MAXWM,
1450N/A SNB_DISPLAY_DFTWM,
1450N/A 2,
1450N/A SNB_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params sandybridge_cursor_wm_info = {
1450N/A SNB_CURSOR_FIFO,
1450N/A SNB_CURSOR_MAXWM,
1450N/A SNB_CURSOR_DFTWM,
1450N/A 2,
1450N/A SNB_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params sandybridge_display_srwm_info = {
1450N/A SNB_DISPLAY_SR_FIFO,
1450N/A SNB_DISPLAY_MAX_SRWM,
1450N/A SNB_DISPLAY_DFT_SRWM,
1450N/A 2,
1450N/A SNB_FIFO_LINE_SIZE
1450N/A};
1450N/Astatic const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1450N/A SNB_CURSOR_SR_FIFO,
1450N/A SNB_CURSOR_MAX_SRWM,
1450N/A SNB_CURSOR_DFT_SRWM,
1450N/A 2,
1450N/A SNB_FIFO_LINE_SIZE
1450N/A};
1450N/A
1450N/A
1450N/A/**
1450N/A * intel_calculate_wm - calculate watermark level
1450N/A * @clock_in_khz: pixel clock
1450N/A * @wm: chip FIFO params
1450N/A * @pixel_size: display pixel size
1450N/A * @latency_ns: memory latency for the platform
1450N/A *
1450N/A * Calculate the watermark level (the level at which the display plane will
1450N/A * start fetching from memory again). Each chip has a different display
1450N/A * FIFO size and allocation, so the caller needs to figure that out and pass
1450N/A * in the correct intel_watermark_params structure.
1450N/A *
1450N/A * As the pixel clock runs, the FIFO will be drained at a rate that depends
1450N/A * on the pixel size. When it reaches the watermark level, it'll start
1450N/A * fetching FIFO line sized based chunks from memory until the FIFO fills
1450N/A * past the watermark point. If the FIFO drains completely, a FIFO underrun
1450N/A * will occur, and a display engine hang could result.
1450N/A */
1450N/Astatic unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1450N/A const struct intel_watermark_params *wm,
1450N/A int fifo_size,
1450N/A int pixel_size,
1450N/A unsigned long latency_ns)
1450N/A{
1450N/A long entries_required, wm_size;
1450N/A
1450N/A /*
1450N/A * Note: we need to make sure we don't overflow for various clock &
1450N/A * latency values.
1450N/A * clocks go from a few thousand to several hundred thousand.
1450N/A * latency is usually a few thousand
1450N/A */
1450N/A entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1450N/A 1000;
1450N/A entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1450N/A
1450N/A DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1450N/A
1450N/A wm_size = fifo_size - (entries_required + wm->guard_size);
1450N/A
1450N/A DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1450N/A
1450N/A /* Don't promote wm_size to unsigned... */
1450N/A if (wm_size > (long)wm->max_wm)
1450N/A wm_size = wm->max_wm;
1450N/A if (wm_size <= 0)
1450N/A wm_size = wm->default_wm;
1450N/A return wm_size;
1450N/A}
1450N/A
1450N/Astatic struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1450N/A{
1450N/A struct drm_crtc *crtc, *enabled = NULL;
1450N/A
1450N/A list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
1450N/A if (intel_crtc_active(crtc)) {
1450N/A if (enabled)
1450N/A return NULL;
1450N/A enabled = crtc;
1450N/A }
1450N/A }
1450N/A
1450N/A return enabled;
1450N/A}
1450N/A
1450N/Astatic void pineview_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_crtc *crtc;
1450N/A const struct cxsr_latency *latency;
1450N/A u32 reg;
1450N/A unsigned long wm;
1450N/A
1450N/A latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1450N/A dev_priv->fsb_freq, dev_priv->mem_freq);
1450N/A if (!latency) {
1450N/A DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1450N/A pineview_disable_cxsr(dev);
1450N/A return;
1450N/A }
1450N/A
1450N/A crtc = single_enabled_crtc(dev);
1450N/A if (crtc) {
1450N/A int clock = crtc->mode.clock;
1450N/A int pixel_size = crtc->fb->bits_per_pixel / 8;
1450N/A
1450N/A /* Display SR */
1450N/A wm = intel_calculate_wm(clock, &pineview_display_wm,
1450N/A pineview_display_wm.fifo_size,
1450N/A pixel_size, latency->display_sr);
1450N/A reg = I915_READ(DSPFW1);
1450N/A reg &= ~DSPFW_SR_MASK;
1450N/A reg |= wm << DSPFW_SR_SHIFT;
1450N/A I915_WRITE(DSPFW1, reg);
1450N/A DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1450N/A
1450N/A /* cursor SR */
1450N/A wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1450N/A pineview_display_wm.fifo_size,
1450N/A pixel_size, latency->cursor_sr);
1450N/A reg = I915_READ(DSPFW3);
1450N/A reg &= ~DSPFW_CURSOR_SR_MASK;
1450N/A reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1450N/A I915_WRITE(DSPFW3, reg);
1450N/A
1450N/A /* Display HPLL off SR */
1450N/A wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1450N/A pineview_display_hplloff_wm.fifo_size,
1450N/A pixel_size, latency->display_hpll_disable);
1450N/A reg = I915_READ(DSPFW3);
1450N/A reg &= ~DSPFW_HPLL_SR_MASK;
1450N/A reg |= wm & DSPFW_HPLL_SR_MASK;
1450N/A I915_WRITE(DSPFW3, reg);
1450N/A
1450N/A /* cursor HPLL off SR */
1450N/A wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1450N/A pineview_display_hplloff_wm.fifo_size,
1450N/A pixel_size, latency->cursor_hpll_disable);
1450N/A reg = I915_READ(DSPFW3);
1450N/A reg &= ~DSPFW_HPLL_CURSOR_MASK;
1450N/A reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1450N/A I915_WRITE(DSPFW3, reg);
1450N/A DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1450N/A
1450N/A /* activate cxsr */
1450N/A I915_WRITE(DSPFW3,
1450N/A I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1450N/A DRM_DEBUG_KMS("Self-refresh is enabled\n");
1450N/A } else {
1450N/A pineview_disable_cxsr(dev);
1450N/A DRM_DEBUG_KMS("Self-refresh is disabled\n");
1450N/A }
1450N/A}
1450N/A
1450N/Astatic bool g4x_compute_wm0(struct drm_device *dev,
1450N/A int plane,
1450N/A const struct intel_watermark_params *display,
1450N/A int display_latency_ns,
1450N/A const struct intel_watermark_params *cursor,
1450N/A int cursor_latency_ns,
1450N/A int *plane_wm,
1450N/A int *cursor_wm)
1450N/A{
1450N/A struct drm_crtc *crtc;
1450N/A int htotal, hdisplay, clock, pixel_size;
1450N/A int line_time_us, line_count;
1450N/A int entries, tlb_miss;
1450N/A
1450N/A crtc = intel_get_crtc_for_plane(dev, plane);
1450N/A if (!intel_crtc_active(crtc)) {
1450N/A *cursor_wm = cursor->guard_size;
1450N/A *plane_wm = display->guard_size;
1450N/A return false;
1450N/A }
1450N/A
1450N/A htotal = crtc->mode.htotal;
1450N/A hdisplay = crtc->mode.hdisplay;
1450N/A clock = crtc->mode.clock;
1450N/A pixel_size = crtc->fb->bits_per_pixel / 8;
1450N/A
1450N/A /* Use the small buffer method to calculate plane watermark */
1450N/A entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1450N/A tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1450N/A if (tlb_miss > 0)
1450N/A entries += tlb_miss;
1450N/A entries = DIV_ROUND_UP(entries, display->cacheline_size);
1450N/A *plane_wm = entries + display->guard_size;
1450N/A if (*plane_wm > (int)display->max_wm)
1450N/A *plane_wm = display->max_wm;
1450N/A
1450N/A /* Use the large buffer method to calculate cursor watermark */
1450N/A line_time_us = ((htotal * 1000) / clock);
1450N/A line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1450N/A entries = line_count * 64 * pixel_size;
1450N/A tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1450N/A if (tlb_miss > 0)
1450N/A entries += tlb_miss;
1450N/A entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1450N/A *cursor_wm = entries + cursor->guard_size;
1450N/A if (*cursor_wm > (int)cursor->max_wm)
1450N/A *cursor_wm = (int)cursor->max_wm;
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/A/*
1450N/A * Check the wm result.
1450N/A *
1450N/A * If any calculated watermark values is larger than the maximum value that
1450N/A * can be programmed into the associated watermark register, that watermark
1450N/A * must be disabled.
1450N/A */
1450N/Astatic bool g4x_check_srwm(struct drm_device *dev,
1450N/A int display_wm, int cursor_wm,
1450N/A const struct intel_watermark_params *display,
1450N/A const struct intel_watermark_params *cursor)
1450N/A{
1450N/A DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1450N/A display_wm, cursor_wm);
1450N/A
1450N/A if (display_wm > display->max_wm) {
1450N/A DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1450N/A display_wm, display->max_wm);
1450N/A return false;
1450N/A }
1450N/A
1450N/A if (cursor_wm > cursor->max_wm) {
1450N/A DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1450N/A cursor_wm, cursor->max_wm);
1450N/A return false;
1450N/A }
1450N/A
1450N/A if (!(display_wm || cursor_wm)) {
1450N/A DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1450N/A return false;
1450N/A }
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/Astatic bool g4x_compute_srwm(struct drm_device *dev,
1450N/A int plane,
1450N/A int latency_ns,
1450N/A const struct intel_watermark_params *display,
1450N/A const struct intel_watermark_params *cursor,
1450N/A int *display_wm, int *cursor_wm)
1450N/A{
1450N/A struct drm_crtc *crtc;
1450N/A int hdisplay, htotal, pixel_size, clock;
1450N/A unsigned long line_time_us;
1450N/A int line_count, line_size;
1450N/A int small, large;
1450N/A int entries;
1450N/A
1450N/A if (!latency_ns) {
1450N/A *display_wm = *cursor_wm = 0;
1450N/A return false;
1450N/A }
1450N/A
1450N/A crtc = intel_get_crtc_for_plane(dev, plane);
1450N/A hdisplay = crtc->mode.hdisplay;
1450N/A htotal = crtc->mode.htotal;
1450N/A clock = crtc->mode.clock;
1450N/A pixel_size = crtc->fb->bits_per_pixel / 8;
1450N/A
1450N/A line_time_us = (htotal * 1000) / clock;
1450N/A line_count = (latency_ns / line_time_us + 1000) / 1000;
1450N/A line_size = hdisplay * pixel_size;
1450N/A
1450N/A /* Use the minimum of the small and large buffer method for primary */
1450N/A small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1450N/A large = line_count * line_size;
1450N/A
1450N/A entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1450N/A *display_wm = entries + display->guard_size;
1450N/A
1450N/A /* calculate the self-refresh watermark for display cursor */
1450N/A entries = line_count * pixel_size * 64;
1450N/A entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1450N/A *cursor_wm = entries + cursor->guard_size;
1450N/A
1450N/A return g4x_check_srwm(dev,
1450N/A *display_wm, *cursor_wm,
1450N/A display, cursor);
1450N/A}
1450N/A
1450N/Astatic bool vlv_compute_drain_latency(struct drm_device *dev,
1450N/A int plane,
1450N/A int *plane_prec_mult,
1450N/A int *plane_dl,
1450N/A int *cursor_prec_mult,
1450N/A int *cursor_dl)
1450N/A{
1450N/A struct drm_crtc *crtc;
1450N/A int clock, pixel_size;
1450N/A int entries;
1450N/A
1450N/A crtc = intel_get_crtc_for_plane(dev, plane);
1450N/A if (!intel_crtc_active(crtc))
1450N/A return false;
1450N/A
1450N/A clock = crtc->mode.clock; /* VESA DOT Clock */
1450N/A pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1450N/A
1450N/A entries = (clock / 1000) * pixel_size;
1450N/A *plane_prec_mult = (entries > 256) ?
1450N/A DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1450N/A *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1450N/A pixel_size);
1450N/A
1450N/A entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1450N/A *cursor_prec_mult = (entries > 256) ?
1450N/A DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1450N/A *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/A/*
1450N/A * Update drain latency registers of memory arbiter
1450N/A *
1450N/A * Valleyview SoC has a new memory arbiter and needs drain latency registers
1450N/A * to be programmed. Each plane has a drain latency multiplier and a drain
1450N/A * latency value.
1450N/A */
1450N/A
1450N/Astatic void vlv_update_drain_latency(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int planea_prec, planea_dl, planeb_prec, planeb_dl;
1450N/A int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1450N/A int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1450N/A either 16 or 32 */
1450N/A
1450N/A /* For plane A, Cursor A */
1450N/A if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1450N/A &cursor_prec_mult, &cursora_dl)) {
1450N/A cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1450N/A DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1450N/A planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1450N/A DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1450N/A
1450N/A I915_WRITE(VLV_DDL1, cursora_prec |
1450N/A (cursora_dl << DDL_CURSORA_SHIFT) |
1450N/A planea_prec | planea_dl);
1450N/A }
1450N/A
1450N/A /* For plane B, Cursor B */
1450N/A if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1450N/A &cursor_prec_mult, &cursorb_dl)) {
1450N/A cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1450N/A DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1450N/A planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1450N/A DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1450N/A
1450N/A I915_WRITE(VLV_DDL2, cursorb_prec |
1450N/A (cursorb_dl << DDL_CURSORB_SHIFT) |
1450N/A planeb_prec | planeb_dl);
1450N/A }
1450N/A}
1450N/A
1450N/A#define single_plane_enabled(x) ((x) != 0 && (((x) & ((x) - 1)) == 0))
1450N/A
1450N/Astatic void valleyview_update_wm(struct drm_device *dev)
1450N/A{
1450N/A static const int sr_latency_ns = 12000;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1450N/A int plane_sr, cursor_sr;
1450N/A int ignore_plane_sr, ignore_cursor_sr;
1450N/A unsigned int enabled = 0;
1450N/A
1450N/A vlv_update_drain_latency(dev);
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_A,
1450N/A &valleyview_wm_info, latency_ns,
1450N/A &valleyview_cursor_wm_info, latency_ns,
1450N/A &planea_wm, &cursora_wm))
1450N/A enabled |= 1 << PIPE_A;
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_B,
1450N/A &valleyview_wm_info, latency_ns,
1450N/A &valleyview_cursor_wm_info, latency_ns,
1450N/A &planeb_wm, &cursorb_wm))
1450N/A enabled |= 1 << PIPE_B;
1450N/A
1450N/A if (single_plane_enabled(enabled) &&
1450N/A g4x_compute_srwm(dev, ffs(enabled) - 1,
1450N/A sr_latency_ns,
1450N/A &valleyview_wm_info,
1450N/A &valleyview_cursor_wm_info,
1450N/A &plane_sr, &ignore_cursor_sr) &&
1450N/A g4x_compute_srwm(dev, ffs(enabled) - 1,
1450N/A 2*sr_latency_ns,
1450N/A &valleyview_wm_info,
1450N/A &valleyview_cursor_wm_info,
1450N/A &ignore_plane_sr, &cursor_sr)) {
1450N/A I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1450N/A } else {
1450N/A I915_WRITE(FW_BLC_SELF_VLV,
1450N/A I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1450N/A plane_sr = cursor_sr = 0;
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1450N/A planea_wm, cursora_wm,
1450N/A planeb_wm, cursorb_wm,
1450N/A plane_sr, cursor_sr);
1450N/A
1450N/A I915_WRITE(DSPFW1,
1450N/A (plane_sr << DSPFW_SR_SHIFT) |
1450N/A (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1450N/A (planeb_wm << DSPFW_PLANEB_SHIFT) |
1450N/A planea_wm);
1450N/A I915_WRITE(DSPFW2,
1450N/A (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1450N/A (cursora_wm << DSPFW_CURSORA_SHIFT));
1450N/A I915_WRITE(DSPFW3,
1450N/A (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1450N/A (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1450N/A}
1450N/A
1450N/Astatic void g4x_update_wm(struct drm_device *dev)
1450N/A{
1450N/A static const int sr_latency_ns = 12000;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1450N/A int plane_sr, cursor_sr;
1450N/A unsigned int enabled = 0;
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_A,
1450N/A &g4x_wm_info, latency_ns,
1450N/A &g4x_cursor_wm_info, latency_ns,
1450N/A &planea_wm, &cursora_wm))
1450N/A enabled |= 1 << PIPE_A;
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_B,
1450N/A &g4x_wm_info, latency_ns,
1450N/A &g4x_cursor_wm_info, latency_ns,
1450N/A &planeb_wm, &cursorb_wm))
1450N/A enabled |= 1 << PIPE_B;
1450N/A
1450N/A if (single_plane_enabled(enabled) &&
1450N/A g4x_compute_srwm(dev, ffs(enabled) - 1,
1450N/A sr_latency_ns,
1450N/A &g4x_wm_info,
1450N/A &g4x_cursor_wm_info,
1450N/A &plane_sr, &cursor_sr)) {
1450N/A I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1450N/A } else {
1450N/A I915_WRITE(FW_BLC_SELF,
1450N/A I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1450N/A plane_sr = cursor_sr = 0;
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1450N/A planea_wm, cursora_wm,
1450N/A planeb_wm, cursorb_wm,
1450N/A plane_sr, cursor_sr);
1450N/A
1450N/A I915_WRITE(DSPFW1,
1450N/A (plane_sr << DSPFW_SR_SHIFT) |
1450N/A (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1450N/A (planeb_wm << DSPFW_PLANEB_SHIFT) |
1450N/A planea_wm);
1450N/A I915_WRITE(DSPFW2,
1450N/A (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1450N/A (cursora_wm << DSPFW_CURSORA_SHIFT));
1450N/A /* HPLL off in SR has some issues on G4x... disable it */
1450N/A I915_WRITE(DSPFW3,
1450N/A (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1450N/A (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1450N/A}
1450N/A
1450N/Astatic void i965_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_crtc *crtc;
1450N/A int srwm = 1;
1450N/A int cursor_sr = 16;
1450N/A
1450N/A /* Calc sr entries for one plane configs */
1450N/A crtc = single_enabled_crtc(dev);
1450N/A if (crtc) {
1450N/A /* self-refresh has much higher latency */
1450N/A static const int sr_latency_ns = 12000;
1450N/A int clock = crtc->mode.clock;
1450N/A int htotal = crtc->mode.htotal;
1450N/A int hdisplay = crtc->mode.hdisplay;
1450N/A int pixel_size = crtc->fb->bits_per_pixel / 8;
1450N/A unsigned long line_time_us;
1450N/A int entries;
1450N/A
1450N/A line_time_us = ((htotal * 1000) / clock);
1450N/A
1450N/A /* Use ns/us then divide to preserve precision */
1450N/A entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450N/A pixel_size * hdisplay;
1450N/A entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1450N/A srwm = I965_FIFO_SIZE - entries;
1450N/A if (srwm < 0)
1450N/A srwm = 1;
1450N/A srwm &= 0x1ff;
1450N/A DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1450N/A entries, srwm);
1450N/A
1450N/A entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450N/A pixel_size * 64;
1450N/A entries = DIV_ROUND_UP(entries,
1450N/A i965_cursor_wm_info.cacheline_size);
1450N/A cursor_sr = i965_cursor_wm_info.fifo_size -
1450N/A (entries + i965_cursor_wm_info.guard_size);
1450N/A
1450N/A if (cursor_sr > i965_cursor_wm_info.max_wm)
1450N/A cursor_sr = (int) i965_cursor_wm_info.max_wm;
1450N/A
1450N/A DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1450N/A "cursor %d\n", srwm, cursor_sr);
1450N/A
1450N/A if (IS_CRESTLINE(dev))
1450N/A I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1450N/A } else {
1450N/A /* Turn off self refresh if both pipes are enabled */
1450N/A if (IS_CRESTLINE(dev))
1450N/A I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1450N/A & ~FW_BLC_SELF_EN);
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1450N/A srwm);
1450N/A
1450N/A /* 965 has limitations... */
1450N/A I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1450N/A (8 << 16) | (8 << 8) | (8 << 0));
1450N/A I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1450N/A /* update cursor SR watermark */
1450N/A I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1450N/A}
1450N/A
1450N/Astatic void i9xx_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A const struct intel_watermark_params *wm_info;
1450N/A uint32_t fwater_lo;
1450N/A uint32_t fwater_hi;
1450N/A int cwm, srwm = 1;
1450N/A int fifo_size;
1450N/A int planea_wm, planeb_wm;
1450N/A struct drm_crtc *crtc, *enabled = NULL;
1450N/A
1450N/A if (IS_I945GM(dev))
1450N/A wm_info = &i945_wm_info;
1450N/A else if (!IS_GEN2(dev))
1450N/A wm_info = &i915_wm_info;
1450N/A else
1450N/A wm_info = &i855_wm_info;
1450N/A
1450N/A fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1450N/A crtc = intel_get_crtc_for_plane(dev, 0);
1450N/A if (intel_crtc_active(crtc)) {
1450N/A int cpp = crtc->fb->bits_per_pixel / 8;
1450N/A if (IS_GEN2(dev))
1450N/A cpp = 4;
1450N/A
1450N/A planea_wm = intel_calculate_wm(crtc->mode.clock,
1450N/A wm_info, fifo_size, cpp,
1450N/A latency_ns);
1450N/A enabled = crtc;
1450N/A } else
1450N/A planea_wm = fifo_size - wm_info->guard_size;
1450N/A
1450N/A fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1450N/A crtc = intel_get_crtc_for_plane(dev, 1);
1450N/A if (intel_crtc_active(crtc)) {
1450N/A int cpp = crtc->fb->bits_per_pixel / 8;
1450N/A if (IS_GEN2(dev))
1450N/A cpp = 4;
1450N/A
1450N/A planeb_wm = intel_calculate_wm(crtc->mode.clock,
1450N/A wm_info, fifo_size, cpp,
1450N/A latency_ns);
1450N/A if (enabled == NULL)
1450N/A enabled = crtc;
1450N/A else
1450N/A enabled = NULL;
1450N/A } else
1450N/A planeb_wm = fifo_size - wm_info->guard_size;
1450N/A
1450N/A DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1450N/A
1450N/A /*
1450N/A * Overlay gets an aggressive default since video jitter is bad.
1450N/A */
1450N/A cwm = 2;
1450N/A
1450N/A /* Play safe and disable self-refresh before adjusting watermarks. */
1450N/A if (IS_I945G(dev) || IS_I945GM(dev))
1450N/A I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1450N/A else if (IS_I915GM(dev))
1450N/A I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1450N/A
1450N/A /* Calc sr entries for one plane configs */
1450N/A if (HAS_FW_BLC(dev) && enabled) {
1450N/A /* self-refresh has much higher latency */
1450N/A static const int sr_latency_ns = 6000;
1450N/A int clock = enabled->mode.clock;
1450N/A int htotal = enabled->mode.htotal;
1450N/A int hdisplay = enabled->mode.hdisplay;
1450N/A int pixel_size = enabled->fb->bits_per_pixel / 8;
1450N/A unsigned long line_time_us;
1450N/A int entries;
1450N/A
1450N/A line_time_us = (htotal * 1000) / clock;
1450N/A
1450N/A /* Use ns/us then divide to preserve precision */
1450N/A entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450N/A pixel_size * hdisplay;
1450N/A entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1450N/A DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1450N/A srwm = wm_info->fifo_size - entries;
1450N/A if (srwm < 0)
1450N/A srwm = 1;
1450N/A
1450N/A if (IS_I945G(dev) || IS_I945GM(dev))
1450N/A I915_WRITE(FW_BLC_SELF,
1450N/A FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1450N/A else if (IS_I915GM(dev))
1450N/A I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1450N/A planea_wm, planeb_wm, cwm, srwm);
1450N/A
1450N/A fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1450N/A fwater_hi = (cwm & 0x1f);
1450N/A
1450N/A /* Set request length to 8 cachelines per fetch */
1450N/A fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1450N/A fwater_hi = fwater_hi | (1 << 8);
1450N/A
1450N/A I915_WRITE(FW_BLC, fwater_lo);
1450N/A I915_WRITE(FW_BLC2, fwater_hi);
1450N/A
1450N/A if (HAS_FW_BLC(dev)) {
1450N/A if (enabled) {
1450N/A if (IS_I945G(dev) || IS_I945GM(dev))
1450N/A I915_WRITE(FW_BLC_SELF,
1450N/A FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1450N/A else if (IS_I915GM(dev))
1450N/A I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1450N/A DRM_DEBUG_KMS("memory self refresh enabled\n");
1450N/A } else
1450N/A DRM_DEBUG_KMS("memory self refresh disabled\n");
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void i830_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_crtc *crtc;
1450N/A uint32_t fwater_lo;
1450N/A int planea_wm;
1450N/A
1450N/A crtc = single_enabled_crtc(dev);
1450N/A if (crtc == NULL)
1450N/A return;
1450N/A
1450N/A planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1450N/A dev_priv->display.get_fifo_size(dev, 0),
1450N/A 4, latency_ns);
1450N/A fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1450N/A fwater_lo |= (3<<8) | planea_wm;
1450N/A
1450N/A DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1450N/A
1450N/A I915_WRITE(FW_BLC, fwater_lo);
1450N/A}
1450N/A
1450N/A#define ILK_LP0_PLANE_LATENCY 700
1450N/A#define ILK_LP0_CURSOR_LATENCY 1300
1450N/A
1450N/A/*
1450N/A * Check the wm result.
1450N/A *
1450N/A * If any calculated watermark values is larger than the maximum value that
1450N/A * can be programmed into the associated watermark register, that watermark
1450N/A * must be disabled.
1450N/A */
1450N/Astatic bool ironlake_check_srwm(struct drm_device *dev, int level,
1450N/A int fbc_wm, int display_wm, int cursor_wm,
1450N/A const struct intel_watermark_params *display,
1450N/A const struct intel_watermark_params *cursor)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1450N/A " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1450N/A
1450N/A if (fbc_wm > SNB_FBC_MAX_SRWM) {
1450N/A DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1450N/A fbc_wm, SNB_FBC_MAX_SRWM, level);
1450N/A
1450N/A /* fbc has it's own way to disable FBC WM */
1450N/A I915_WRITE(DISP_ARB_CTL,
1450N/A I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1450N/A return false;
1450N/A } else if (INTEL_INFO(dev)->gen >= 6) {
1450N/A /* enable FBC WM (except on ILK, where it must remain off) */
1450N/A I915_WRITE(DISP_ARB_CTL,
1450N/A I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1450N/A }
1450N/A
1450N/A if (display_wm > display->max_wm) {
1450N/A DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1450N/A display_wm, SNB_DISPLAY_MAX_SRWM, level);
1450N/A return false;
1450N/A }
1450N/A
1450N/A if (cursor_wm > cursor->max_wm) {
1450N/A DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1450N/A cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1450N/A return false;
1450N/A }
1450N/A
1450N/A if (!(fbc_wm || display_wm || cursor_wm)) {
1450N/A DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1450N/A return false;
1450N/A }
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/A/*
1450N/A * Compute watermark values of WM[1-3],
1450N/A */
1450N/Astatic bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1450N/A int latency_ns,
1450N/A const struct intel_watermark_params *display,
1450N/A const struct intel_watermark_params *cursor,
1450N/A int *fbc_wm, int *display_wm, int *cursor_wm)
1450N/A{
1450N/A struct drm_crtc *crtc;
1450N/A unsigned long line_time_us;
1450N/A int hdisplay, htotal, pixel_size, clock;
1450N/A int line_count, line_size;
1450N/A int small, large;
1450N/A int entries;
1450N/A
1450N/A if (!latency_ns) {
1450N/A *fbc_wm = *display_wm = *cursor_wm = 0;
1450N/A return false;
1450N/A }
1450N/A
1450N/A crtc = intel_get_crtc_for_plane(dev, plane);
1450N/A hdisplay = crtc->mode.hdisplay;
1450N/A htotal = crtc->mode.htotal;
1450N/A clock = crtc->mode.clock;
1450N/A pixel_size = crtc->fb->bits_per_pixel / 8;
1450N/A
1450N/A line_time_us = (htotal * 1000) / clock;
1450N/A line_count = (latency_ns / line_time_us + 1000) / 1000;
1450N/A line_size = hdisplay * pixel_size;
1450N/A
1450N/A /* Use the minimum of the small and large buffer method for primary */
1450N/A small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1450N/A large = line_count * line_size;
1450N/A
1450N/A entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1450N/A *display_wm = entries + display->guard_size;
1450N/A
1450N/A /*
1450N/A * Spec says:
1450N/A * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1450N/A */
1450N/A *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1450N/A
1450N/A /* calculate the self-refresh watermark for display cursor */
1450N/A entries = line_count * pixel_size * 64;
1450N/A entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1450N/A *cursor_wm = entries + cursor->guard_size;
1450N/A
1450N/A return ironlake_check_srwm(dev, level,
1450N/A *fbc_wm, *display_wm, *cursor_wm,
1450N/A display, cursor);
1450N/A}
1450N/A
1450N/Astatic void ironlake_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int fbc_wm, plane_wm, cursor_wm;
1450N/A unsigned int enabled;
1450N/A
1450N/A enabled = 0;
1450N/A if (g4x_compute_wm0(dev, PIPE_A,
1450N/A &ironlake_display_wm_info,
1450N/A ILK_LP0_PLANE_LATENCY,
1450N/A &ironlake_cursor_wm_info,
1450N/A ILK_LP0_CURSOR_LATENCY,
1450N/A &plane_wm, &cursor_wm)) {
1450N/A I915_WRITE(WM0_PIPEA_ILK,
1450N/A (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1450N/A DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1450N/A " plane %d, " "cursor: %d\n",
1450N/A plane_wm, cursor_wm);
1450N/A enabled |= 1 << PIPE_A;
1450N/A }
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_B,
1450N/A &ironlake_display_wm_info,
1450N/A ILK_LP0_PLANE_LATENCY,
1450N/A &ironlake_cursor_wm_info,
1450N/A ILK_LP0_CURSOR_LATENCY,
1450N/A &plane_wm, &cursor_wm)) {
1450N/A I915_WRITE(WM0_PIPEB_ILK,
1450N/A (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1450N/A DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1450N/A " plane %d, cursor: %d\n",
1450N/A plane_wm, cursor_wm);
1450N/A enabled |= 1 << PIPE_B;
1450N/A }
1450N/A
1450N/A /*
1450N/A * Calculate and update the self-refresh watermark only when one
1450N/A * display plane is used.
1450N/A */
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A if (!single_plane_enabled(enabled))
1450N/A return;
1450N/A enabled = ffs(enabled) - 1;
1450N/A
1450N/A /* WM1 */
1450N/A if (!ironlake_compute_srwm(dev, 1, enabled,
1450N/A ILK_READ_WM1_LATENCY() * 500,
1450N/A &ironlake_display_srwm_info,
1450N/A &ironlake_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM1_LP_ILK,
1450N/A WM1_LP_SR_EN |
1450N/A (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A
1450N/A /* WM2 */
1450N/A if (!ironlake_compute_srwm(dev, 2, enabled,
1450N/A ILK_READ_WM2_LATENCY() * 500,
1450N/A &ironlake_display_srwm_info,
1450N/A &ironlake_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM2_LP_ILK,
1450N/A WM2_LP_EN |
1450N/A (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A
1450N/A /*
1450N/A * WM3 is unsupported on ILK, probably because we don't have latency
1450N/A * data for that power state
1450N/A */
1450N/A}
1450N/A
1450N/Astatic void sandybridge_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1450N/A u32 val;
1450N/A int fbc_wm, plane_wm, cursor_wm;
1450N/A unsigned int enabled;
1450N/A
1450N/A enabled = 0;
1450N/A if (g4x_compute_wm0(dev, PIPE_A,
1450N/A &sandybridge_display_wm_info, latency,
1450N/A &sandybridge_cursor_wm_info, latency,
1450N/A &plane_wm, &cursor_wm)) {
1450N/A val = I915_READ(WM0_PIPEA_ILK);
1450N/A val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1450N/A I915_WRITE(WM0_PIPEA_ILK, val |
1450N/A ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1450N/A DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1450N/A " plane %d, " "cursor: %d\n",
1450N/A plane_wm, cursor_wm);
1450N/A enabled |= 1 << PIPE_A;
1450N/A }
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_B,
1450N/A &sandybridge_display_wm_info, latency,
1450N/A &sandybridge_cursor_wm_info, latency,
1450N/A &plane_wm, &cursor_wm)) {
1450N/A val = I915_READ(WM0_PIPEB_ILK);
1450N/A val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1450N/A I915_WRITE(WM0_PIPEB_ILK, val |
1450N/A ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1450N/A DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1450N/A " plane %d, cursor: %d\n",
1450N/A plane_wm, cursor_wm);
1450N/A enabled |= 1 << PIPE_B;
1450N/A }
1450N/A
1450N/A /*
1450N/A * Calculate and update the self-refresh watermark only when one
1450N/A * display plane is used.
1450N/A *
1450N/A * SNB support 3 levels of watermark.
1450N/A *
1450N/A * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1450N/A * and disabled in the descending order
1450N/A *
1450N/A */
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A if (!single_plane_enabled(enabled) ||
1450N/A dev_priv->sprite_scaling_enabled)
1450N/A return;
1450N/A enabled = ffs(enabled) - 1;
1450N/A
1450N/A /* WM1 */
1450N/A if (!ironlake_compute_srwm(dev, 1, enabled,
1450N/A SNB_READ_WM1_LATENCY() * 500,
1450N/A &sandybridge_display_srwm_info,
1450N/A &sandybridge_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM1_LP_ILK,
1450N/A WM1_LP_SR_EN |
1450N/A (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A
1450N/A /* WM2 */
1450N/A if (!ironlake_compute_srwm(dev, 2, enabled,
1450N/A SNB_READ_WM2_LATENCY() * 500,
1450N/A &sandybridge_display_srwm_info,
1450N/A &sandybridge_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM2_LP_ILK,
1450N/A WM2_LP_EN |
1450N/A (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A
1450N/A /* WM3 */
1450N/A if (!ironlake_compute_srwm(dev, 3, enabled,
1450N/A SNB_READ_WM3_LATENCY() * 500,
1450N/A &sandybridge_display_srwm_info,
1450N/A &sandybridge_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM3_LP_ILK,
1450N/A WM3_LP_EN |
1450N/A (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A}
1450N/A
1450N/Astatic void ivybridge_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1450N/A u32 val;
1450N/A int fbc_wm, plane_wm, cursor_wm;
1450N/A int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1450N/A unsigned int enabled;
1450N/A
1450N/A enabled = 0;
1450N/A if (g4x_compute_wm0(dev, PIPE_A,
1450N/A &sandybridge_display_wm_info, latency,
1450N/A &sandybridge_cursor_wm_info, latency,
1450N/A &plane_wm, &cursor_wm)) {
1450N/A val = I915_READ(WM0_PIPEA_ILK);
1450N/A val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1450N/A I915_WRITE(WM0_PIPEA_ILK, val |
1450N/A ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1450N/A DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1450N/A " plane %d, " "cursor: %d\n",
1450N/A plane_wm, cursor_wm);
1450N/A enabled |= 1 << PIPE_A;
1450N/A }
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_B,
1450N/A &sandybridge_display_wm_info, latency,
1450N/A &sandybridge_cursor_wm_info, latency,
1450N/A &plane_wm, &cursor_wm)) {
1450N/A val = I915_READ(WM0_PIPEB_ILK);
1450N/A val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1450N/A I915_WRITE(WM0_PIPEB_ILK, val |
1450N/A ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1450N/A DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1450N/A " plane %d, cursor: %d\n",
1450N/A plane_wm, cursor_wm);
1450N/A enabled |= 1 << PIPE_B;
1450N/A }
1450N/A
1450N/A if (g4x_compute_wm0(dev, PIPE_C,
1450N/A &sandybridge_display_wm_info, latency,
1450N/A &sandybridge_cursor_wm_info, latency,
1450N/A &plane_wm, &cursor_wm)) {
1450N/A val = I915_READ(WM0_PIPEC_IVB);
1450N/A val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1450N/A I915_WRITE(WM0_PIPEC_IVB, val |
1450N/A ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1450N/A DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1450N/A " plane %d, cursor: %d\n",
1450N/A plane_wm, cursor_wm);
1450N/A enabled |= 1 << PIPE_C;
1450N/A }
1450N/A
1450N/A /*
1450N/A * Calculate and update the self-refresh watermark only when one
1450N/A * display plane is used.
1450N/A *
1450N/A * SNB support 3 levels of watermark.
1450N/A *
1450N/A * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1450N/A * and disabled in the descending order
1450N/A *
1450N/A */
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A if (!single_plane_enabled(enabled) ||
1450N/A dev_priv->sprite_scaling_enabled)
1450N/A return;
1450N/A enabled = ffs(enabled) - 1;
1450N/A
1450N/A /* WM1 */
1450N/A if (!ironlake_compute_srwm(dev, 1, enabled,
1450N/A SNB_READ_WM1_LATENCY() * 500,
1450N/A &sandybridge_display_srwm_info,
1450N/A &sandybridge_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM1_LP_ILK,
1450N/A WM1_LP_SR_EN |
1450N/A (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A
1450N/A /* WM2 */
1450N/A if (!ironlake_compute_srwm(dev, 2, enabled,
1450N/A SNB_READ_WM2_LATENCY() * 500,
1450N/A &sandybridge_display_srwm_info,
1450N/A &sandybridge_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM2_LP_ILK,
1450N/A WM2_LP_EN |
1450N/A (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A
1450N/A /* WM3, note we have to correct the cursor latency */
1450N/A if (!ironlake_compute_srwm(dev, 3, enabled,
1450N/A SNB_READ_WM3_LATENCY() * 500,
1450N/A &sandybridge_display_srwm_info,
1450N/A &sandybridge_cursor_srwm_info,
1450N/A &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
1450N/A !ironlake_compute_srwm(dev, 3, enabled,
1450N/A 2 * SNB_READ_WM3_LATENCY() * 500,
1450N/A &sandybridge_display_srwm_info,
1450N/A &sandybridge_cursor_srwm_info,
1450N/A &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
1450N/A return;
1450N/A
1450N/A I915_WRITE(WM3_LP_ILK,
1450N/A WM3_LP_EN |
1450N/A (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1450N/A (fbc_wm << WM1_LP_FBC_SHIFT) |
1450N/A (plane_wm << WM1_LP_SR_SHIFT) |
1450N/A cursor_wm);
1450N/A}
1450N/A
1450N/Astatic uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
1450N/A struct drm_crtc *crtc)
1450N/A{
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A uint32_t pixel_rate, pfit_size;
1450N/A
1450N/A pixel_rate = intel_crtc->config.adjusted_mode.clock;
1450N/A
1450N/A /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1450N/A * adjust the pixel_rate here. */
1450N/A
1450N/A pfit_size = intel_crtc->config.pch_pfit.size;
1450N/A if (pfit_size) {
1450N/A uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1450N/A
1450N/A pipe_w = intel_crtc->config.requested_mode.hdisplay;
1450N/A pipe_h = intel_crtc->config.requested_mode.vdisplay;
1450N/A pfit_w = (pfit_size >> 16) & 0xFFFF;
1450N/A pfit_h = pfit_size & 0xFFFF;
1450N/A if (pipe_w < pfit_w)
1450N/A pipe_w = pfit_w;
1450N/A if (pipe_h < pfit_h)
1450N/A pipe_h = pfit_h;
1450N/A
1450N/A pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1450N/A pfit_w * pfit_h);
1450N/A }
1450N/A
1450N/A return pixel_rate;
1450N/A}
1450N/A
1450N/Astatic uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1450N/A uint32_t latency)
1450N/A{
1450N/A uint64_t ret;
1450N/A
1450N/A ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1450N/A ret = POS_DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1450N/A
1450N/A return (uint32_t)ret;
1450N/A}
1450N/A
1450N/Astatic uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1450N/A uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1450N/A uint32_t latency)
1450N/A{
1450N/A uint32_t ret;
1450N/A
1450N/A ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1450N/A ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1450N/A ret = DIV_ROUND_UP(ret, 64) + 2;
1450N/A return ret;
1450N/A}
1450N/A
1450N/Astatic uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1450N/A uint8_t bytes_per_pixel)
1450N/A{
1450N/A return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1450N/A}
1450N/A
1450N/Astruct hsw_pipe_wm_parameters {
1450N/A bool active;
1450N/A bool sprite_enabled;
1450N/A uint8_t pri_bytes_per_pixel;
1450N/A uint8_t spr_bytes_per_pixel;
1450N/A uint8_t cur_bytes_per_pixel;
1450N/A uint32_t pri_horiz_pixels;
1450N/A uint32_t spr_horiz_pixels;
1450N/A uint32_t cur_horiz_pixels;
1450N/A uint32_t pipe_htotal;
1450N/A uint32_t pixel_rate;
1450N/A};
1450N/A
1450N/Astruct hsw_wm_maximums {
1450N/A uint16_t pri;
1450N/A uint16_t spr;
1450N/A uint16_t cur;
1450N/A uint16_t fbc;
1450N/A};
1450N/A
1450N/Astruct hsw_lp_wm_result {
1450N/A bool enable;
1450N/A bool fbc_enable;
1450N/A uint32_t pri_val;
1450N/A uint32_t spr_val;
1450N/A uint32_t cur_val;
1450N/A uint32_t fbc_val;
1450N/A};
1450N/A
1450N/Astruct hsw_wm_values {
1450N/A uint32_t wm_pipe[3];
1450N/A uint32_t wm_lp[3];
1450N/A uint32_t wm_lp_spr[3];
1450N/A uint32_t wm_linetime[3];
1450N/A bool enable_fbc_wm;
1450N/A};
1450N/A
1450N/Aenum hsw_data_buf_partitioning {
1450N/A HSW_DATA_BUF_PART_1_2,
1450N/A HSW_DATA_BUF_PART_5_6,
1450N/A};
1450N/A
1450N/A/* For both WM_PIPE and WM_LP. */
1450N/Astatic uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
1450N/A uint32_t mem_value,
1450N/A bool is_lp)
1450N/A{
1450N/A uint32_t method1, method2;
1450N/A
1450N/A /* TODO: for now, assume the primary plane is always enabled. */
1450N/A if (!params->active)
1450N/A return 0;
1450N/A
1450N/A method1 = hsw_wm_method1(params->pixel_rate,
1450N/A params->pri_bytes_per_pixel,
1450N/A mem_value);
1450N/A
1450N/A if (!is_lp)
1450N/A return method1;
1450N/A
1450N/A method2 = hsw_wm_method2(params->pixel_rate,
1450N/A params->pipe_htotal,
1450N/A params->pri_horiz_pixels,
1450N/A params->pri_bytes_per_pixel,
1450N/A mem_value);
1450N/A
1450N/A return min(method1, method2);
1450N/A}
1450N/A
1450N/A/* For both WM_PIPE and WM_LP. */
1450N/Astatic uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
1450N/A uint32_t mem_value)
1450N/A{
1450N/A uint32_t method1, method2;
1450N/A
1450N/A if (!params->active || !params->sprite_enabled)
1450N/A return 0;
1450N/A
1450N/A method1 = hsw_wm_method1(params->pixel_rate,
1450N/A params->spr_bytes_per_pixel,
1450N/A mem_value);
1450N/A method2 = hsw_wm_method2(params->pixel_rate,
1450N/A params->pipe_htotal,
1450N/A params->spr_horiz_pixels,
1450N/A params->spr_bytes_per_pixel,
1450N/A mem_value);
1450N/A return min(method1, method2);
1450N/A}
1450N/A
1450N/A/* For both WM_PIPE and WM_LP. */
1450N/Astatic uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
1450N/A uint32_t mem_value)
1450N/A{
1450N/A if (!params->active)
1450N/A return 0;
1450N/A
1450N/A return hsw_wm_method2(params->pixel_rate,
1450N/A params->pipe_htotal,
1450N/A params->cur_horiz_pixels,
1450N/A params->cur_bytes_per_pixel,
1450N/A mem_value);
1450N/A}
1450N/A
1450N/A/* Only for WM_LP. */
1450N/Astatic uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
1450N/A uint32_t pri_val,
1450N/A uint32_t mem_value)
1450N/A{
1450N/A if (!params->active)
1450N/A return 0;
1450N/A
1450N/A return hsw_wm_fbc(pri_val,
1450N/A params->pri_horiz_pixels,
1450N/A params->pri_bytes_per_pixel);
1450N/A}
1450N/A
1450N/Astatic bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
1450N/A struct hsw_pipe_wm_parameters *params,
1450N/A struct hsw_lp_wm_result *result)
1450N/A{
1450N/A enum pipe pipe;
1450N/A uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
1450N/A
1450N/A for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
1450N/A struct hsw_pipe_wm_parameters *p = &params[pipe];
1450N/A
1450N/A pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
1450N/A spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
1450N/A cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
1450N/A fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
1450N/A }
1450N/A
1450N/A result->pri_val = max(max(pri_val[0], pri_val[1]), pri_val[2]);
1450N/A result->spr_val = max(max(spr_val[0], spr_val[1]), spr_val[2]);
1450N/A result->cur_val = max(max(cur_val[0], cur_val[1]), cur_val[2]);
1450N/A result->fbc_val = max(max(fbc_val[0], fbc_val[1]), fbc_val[2]);
1450N/A
1450N/A if (result->fbc_val > max->fbc) {
1450N/A result->fbc_enable = false;
1450N/A result->fbc_val = 0;
1450N/A } else {
1450N/A result->fbc_enable = true;
1450N/A }
1450N/A
1450N/A result->enable = result->pri_val <= max->pri &&
1450N/A result->spr_val <= max->spr &&
1450N/A result->cur_val <= max->cur;
1450N/A return result->enable;
1450N/A}
1450N/A
1450N/Astatic uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
1450N/A uint32_t mem_value, enum pipe pipe,
1450N/A struct hsw_pipe_wm_parameters *params)
1450N/A{
1450N/A uint32_t pri_val, cur_val, spr_val;
1450N/A
1450N/A pri_val = hsw_compute_pri_wm(params, mem_value, false);
1450N/A spr_val = hsw_compute_spr_wm(params, mem_value);
1450N/A cur_val = hsw_compute_cur_wm(params, mem_value);
1450N/A
1450N/A if(pri_val > 127)
1450N/A DRM_ERROR("Primary WM error, mode not supported for pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A if(spr_val > 127)
1450N/A DRM_ERROR("Sprite WM error, mode not supported for pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A if(cur_val > 63)
1450N/A DRM_ERROR("Cursor WM error, mode not supported for pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A
1450N/A return (pri_val << WM0_PIPE_PLANE_SHIFT) |
1450N/A (spr_val << WM0_PIPE_SPRITE_SHIFT) |
1450N/A cur_val;
1450N/A}
1450N/A
1450N/Astatic uint32_t
1450N/Ahsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1450N/A u32 linetime, ips_linetime;
1450N/A
1450N/A if (!intel_crtc_active(crtc))
1450N/A return 0;
1450N/A
1450N/A /* The WM are computed with base on how long it takes to fill a single
1450N/A * row at the given clock rate, multiplied by 8.
1450N/A * */
1450N/A linetime = POS_DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
1450N/A ips_linetime = POS_DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
1450N/A intel_ddi_get_cdclk_freq(dev_priv));
1450N/A
1450N/A return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1450N/A PIPE_WM_LINETIME_TIME(linetime);
1450N/A}
1450N/A
1450N/Astatic void hsw_compute_wm_parameters(struct drm_device *dev,
1450N/A struct hsw_pipe_wm_parameters *params,
1450N/A uint32_t *wm,
1450N/A struct hsw_wm_maximums *lp_max_1_2,
1450N/A struct hsw_wm_maximums *lp_max_5_6)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_crtc *crtc;
1450N/A struct drm_plane *plane;
1450N/A uint64_t sskpd = I915_READ64(MCH_SSKPD);
1450N/A enum pipe pipe;
1450N/A int pipes_active = 0, sprites_enabled = 0;
1450N/A
1450N/A if ((sskpd >> 56) & 0xFF)
1450N/A wm[0] = (sskpd >> 56) & 0xFF;
1450N/A else
1450N/A wm[0] = sskpd & 0xF;
1450N/A wm[1] = ((sskpd >> 4) & 0xFF) * 5;
1450N/A wm[2] = ((sskpd >> 12) & 0xFF) * 5;
1450N/A wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
1450N/A wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
1450N/A
1450N/A list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct hsw_pipe_wm_parameters *p;
1450N/A
1450N/A pipe = intel_crtc->pipe;
1450N/A p = &params[pipe];
1450N/A
1450N/A p->active = intel_crtc_active(crtc);
1450N/A if (!p->active)
1450N/A continue;
1450N/A
1450N/A pipes_active++;
1450N/A
1450N/A p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
1450N/A p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
1450N/A p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
1450N/A p->cur_bytes_per_pixel = 4;
1450N/A p->pri_horiz_pixels =
1450N/A intel_crtc->config.requested_mode.hdisplay;
1450N/A p->cur_horiz_pixels = 64;
1450N/A }
1450N/A
1450N/A list_for_each_entry(plane, struct drm_plane, &dev->mode_config.plane_list, head) {
1450N/A struct intel_plane *intel_plane = to_intel_plane(plane);
1450N/A struct hsw_pipe_wm_parameters *p;
1450N/A
1450N/A pipe = intel_plane->pipe;
1450N/A p = &params[pipe];
1450N/A
1450N/A p->sprite_enabled = intel_plane->wm.enable;
1450N/A p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
1450N/A p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
1450N/A
1450N/A if (p->sprite_enabled)
1450N/A sprites_enabled++;
1450N/A }
1450N/A
1450N/A if (pipes_active > 1) {
1450N/A lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
1450N/A lp_max_1_2->spr = lp_max_5_6->spr = 128;
1450N/A lp_max_1_2->cur = lp_max_5_6->cur = 64;
1450N/A } else {
1450N/A lp_max_1_2->pri = sprites_enabled ? 384 : 768;
1450N/A lp_max_5_6->pri = sprites_enabled ? 128 : 768;
1450N/A lp_max_1_2->spr = 384;
1450N/A lp_max_5_6->spr = 640;
1450N/A lp_max_1_2->cur = lp_max_5_6->cur = 255;
1450N/A }
1450N/A lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
1450N/A}
1450N/A
1450N/Astatic void hsw_compute_wm_results(struct drm_device *dev,
1450N/A struct hsw_pipe_wm_parameters *params,
1450N/A uint32_t *wm,
1450N/A struct hsw_wm_maximums *lp_maximums,
1450N/A struct hsw_wm_values *results)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_crtc *crtc;
1450N/A struct hsw_lp_wm_result lp_results[4];
1450N/A enum pipe pipe;
1450N/A int level, max_level, wm_lp;
1450N/A
1450N/A for (level = 1; level <= 4; level++)
1450N/A if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
1450N/A &lp_results[level - 1]))
1450N/A break;
1450N/A max_level = level - 1;
1450N/A
1450N/A /* The spec says it is preferred to disable FBC WMs instead of disabling
1450N/A * a WM level. */
1450N/A results->enable_fbc_wm = true;
1450N/A for (level = 1; level <= max_level; level++) {
1450N/A if (!lp_results[level - 1].fbc_enable) {
1450N/A results->enable_fbc_wm = false;
1450N/A break;
1450N/A }
1450N/A }
1450N/A
1450N/A memset(results, 0, sizeof(*results));
1450N/A for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1450N/A const struct hsw_lp_wm_result *r;
1450N/A
1450N/A level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
1450N/A if (level > max_level)
1450N/A break;
1450N/A
1450N/A r = &lp_results[level - 1];
1450N/A results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
1450N/A r->fbc_val,
1450N/A r->pri_val,
1450N/A r->cur_val);
1450N/A results->wm_lp_spr[wm_lp - 1] = r->spr_val;
1450N/A }
1450N/A
1450N/A for_each_pipe(pipe)
1450N/A results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
1450N/A pipe,
1450N/A &params[pipe]);
1450N/A
1450N/A for_each_pipe(pipe) {
1450N/A crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1450N/A results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
1450N/A }
1450N/A}
1450N/A
1450N/A/* Find the result with the highest level enabled. Check for enable_fbc_wm in
1450N/A * case both are at the same level. Prefer r1 in case they're the same. */
1450N/Astruct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
1450N/A struct hsw_wm_values *r2)
1450N/A{
1450N/A int i, val_r1 = 0, val_r2 = 0;
1450N/A
1450N/A for (i = 0; i < 3; i++) {
1450N/A if (r1->wm_lp[i] & WM3_LP_EN)
1450N/A val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
1450N/A if (r2->wm_lp[i] & WM3_LP_EN)
1450N/A val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
1450N/A }
1450N/A
1450N/A if (val_r1 == val_r2) {
1450N/A if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
1450N/A return r2;
1450N/A else
1450N/A return r1;
1450N/A } else if (val_r1 > val_r2) {
1450N/A return r1;
1450N/A } else {
1450N/A return r2;
1450N/A }
1450N/A}
1450N/A
1450N/A/*
1450N/A * The spec says we shouldn't write when we don't need, because every write
1450N/A * causes WMs to be re-evaluated, expending some power.
1450N/A */
1450N/Astatic void hsw_write_wm_values(struct drm_i915_private *dev_priv,
1450N/A struct hsw_wm_values *results,
1450N/A enum hsw_data_buf_partitioning partitioning)
1450N/A{
1450N/A struct hsw_wm_values previous;
1450N/A uint32_t val;
1450N/A enum hsw_data_buf_partitioning prev_partitioning;
1450N/A bool prev_enable_fbc_wm;
1450N/A
1450N/A previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
1450N/A previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
1450N/A previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
1450N/A previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
1450N/A previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
1450N/A previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
1450N/A previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
1450N/A previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
1450N/A previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
1450N/A previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
1450N/A previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
1450N/A previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
1450N/A
1450N/A prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
1450N/A HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
1450N/A
1450N/A prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
1450N/A
1450N/A if (memcmp(results->wm_pipe, previous.wm_pipe,
1450N/A sizeof(results->wm_pipe)) == 0 &&
1450N/A memcmp(results->wm_lp, previous.wm_lp,
1450N/A sizeof(results->wm_lp)) == 0 &&
1450N/A memcmp(results->wm_lp_spr, previous.wm_lp_spr,
1450N/A sizeof(results->wm_lp_spr)) == 0 &&
1450N/A memcmp(results->wm_linetime, previous.wm_linetime,
1450N/A sizeof(results->wm_linetime)) == 0 &&
1450N/A partitioning == prev_partitioning &&
1450N/A results->enable_fbc_wm == prev_enable_fbc_wm)
1450N/A return;
1450N/A
1450N/A if (previous.wm_lp[2] != 0)
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A if (previous.wm_lp[1] != 0)
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A if (previous.wm_lp[0] != 0)
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A if (previous.wm_pipe[0] != results->wm_pipe[0])
1450N/A I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
1450N/A if (previous.wm_pipe[1] != results->wm_pipe[1])
1450N/A I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
1450N/A if (previous.wm_pipe[2] != results->wm_pipe[2])
1450N/A I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
1450N/A
1450N/A if (previous.wm_linetime[0] != results->wm_linetime[0])
1450N/A I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
1450N/A if (previous.wm_linetime[1] != results->wm_linetime[1])
1450N/A I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
1450N/A if (previous.wm_linetime[2] != results->wm_linetime[2])
1450N/A I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
1450N/A
1450N/A if (prev_partitioning != partitioning) {
1450N/A val = I915_READ(WM_MISC);
1450N/A if (partitioning == HSW_DATA_BUF_PART_1_2)
1450N/A val &= ~WM_MISC_DATA_PARTITION_5_6;
1450N/A else
1450N/A val |= WM_MISC_DATA_PARTITION_5_6;
1450N/A I915_WRITE(WM_MISC, val);
1450N/A }
1450N/A
1450N/A if (prev_enable_fbc_wm != results->enable_fbc_wm) {
1450N/A val = I915_READ(DISP_ARB_CTL);
1450N/A if (results->enable_fbc_wm)
1450N/A val &= ~DISP_FBC_WM_DIS;
1450N/A else
1450N/A val |= DISP_FBC_WM_DIS;
1450N/A I915_WRITE(DISP_ARB_CTL, val);
1450N/A }
1450N/A
1450N/A if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
1450N/A I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
1450N/A if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
1450N/A I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
1450N/A if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
1450N/A I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
1450N/A
1450N/A if (results->wm_lp[0] != 0)
1450N/A I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
1450N/A if (results->wm_lp[1] != 0)
1450N/A I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
1450N/A if (results->wm_lp[2] != 0)
1450N/A I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
1450N/A}
1450N/A
1450N/Astatic void haswell_update_wm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
1450N/A struct hsw_pipe_wm_parameters params[3];
1450N/A struct hsw_wm_values results_1_2, results_5_6, *best_results;
1450N/A uint32_t wm[5];
1450N/A enum hsw_data_buf_partitioning partitioning;
1450N/A
1450N/A hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6);
1450N/A
1450N/A hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
1450N/A if (lp_max_1_2.pri != lp_max_5_6.pri) {
1450N/A hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
1450N/A &results_5_6);
1450N/A best_results = hsw_find_best_result(&results_1_2, &results_5_6);
1450N/A } else {
1450N/A best_results = &results_1_2;
1450N/A }
1450N/A
1450N/A partitioning = (best_results == &results_1_2) ?
1450N/A HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
1450N/A
1450N/A hsw_write_wm_values(dev_priv, best_results, partitioning);
1450N/A}
1450N/A
1450N/Astatic void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
1450N/A uint32_t sprite_width, int pixel_size,
1450N/A bool enable)
1450N/A{
1450N/A struct drm_plane *plane;
1450N/A
1450N/A list_for_each_entry(plane, struct drm_plane, &dev->mode_config.plane_list, head) {
1450N/A struct intel_plane *intel_plane = to_intel_plane(plane);
1450N/A
1450N/A if (intel_plane->pipe == pipe) {
1450N/A intel_plane->wm.enable = enable;
1450N/A intel_plane->wm.horiz_pixels = sprite_width + 1;
1450N/A intel_plane->wm.bytes_per_pixel = (uint8_t)pixel_size;
1450N/A break;
1450N/A }
1450N/A }
1450N/A
1450N/A haswell_update_wm(dev);
1450N/A}
1450N/A
1450N/Astatic bool
1450N/Asandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1450N/A uint32_t sprite_width, int pixel_size,
1450N/A const struct intel_watermark_params *display,
1450N/A int display_latency_ns, int *sprite_wm)
1450N/A{
1450N/A struct drm_crtc *crtc;
1450N/A int clock;
1450N/A int entries, tlb_miss;
1450N/A
1450N/A crtc = intel_get_crtc_for_plane(dev, plane);
1450N/A if (!intel_crtc_active(crtc)) {
1450N/A *sprite_wm = display->guard_size;
1450N/A return false;
1450N/A }
1450N/A
1450N/A clock = crtc->mode.clock;
1450N/A
1450N/A /* Use the small buffer method to calculate the sprite watermark */
1450N/A entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1450N/A tlb_miss = display->fifo_size*display->cacheline_size -
1450N/A sprite_width * 8;
1450N/A if (tlb_miss > 0)
1450N/A entries += tlb_miss;
1450N/A entries = DIV_ROUND_UP(entries, display->cacheline_size);
1450N/A *sprite_wm = entries + display->guard_size;
1450N/A if (*sprite_wm > (int)display->max_wm)
1450N/A *sprite_wm = display->max_wm;
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/Astatic bool
1450N/Asandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1450N/A uint32_t sprite_width, int pixel_size,
1450N/A const struct intel_watermark_params *display,
1450N/A int latency_ns, int *sprite_wm)
1450N/A{
1450N/A struct drm_crtc *crtc;
1450N/A unsigned long line_time_us;
1450N/A int clock;
1450N/A int line_count, line_size;
1450N/A int small, large;
1450N/A int entries;
1450N/A
1450N/A if (!latency_ns) {
1450N/A *sprite_wm = 0;
1450N/A return false;
1450N/A }
1450N/A
1450N/A crtc = intel_get_crtc_for_plane(dev, plane);
1450N/A clock = crtc->mode.clock;
1450N/A if (!clock) {
1450N/A *sprite_wm = 0;
1450N/A return false;
1450N/A }
1450N/A
1450N/A line_time_us = (sprite_width * 1000) / clock;
1450N/A if (!line_time_us) {
1450N/A *sprite_wm = 0;
1450N/A return false;
1450N/A }
1450N/A
1450N/A line_count = (latency_ns / line_time_us + 1000) / 1000;
1450N/A line_size = sprite_width * pixel_size;
1450N/A
1450N/A /* Use the minimum of the small and large buffer method for primary */
1450N/A small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1450N/A large = line_count * line_size;
1450N/A
1450N/A entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1450N/A *sprite_wm = entries + display->guard_size;
1450N/A
1450N/A return *sprite_wm > 0x3ff ? false : true;
1450N/A}
1450N/A
1450N/Astatic void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
1450N/A uint32_t sprite_width, int pixel_size,
1450N/A bool enable)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1450N/A u32 val;
1450N/A int sprite_wm, reg;
1450N/A int ret;
1450N/A
1450N/A if (!enable)
1450N/A return;
1450N/A
1450N/A switch (pipe) {
1450N/A case 0:
1450N/A reg = WM0_PIPEA_ILK;
1450N/A break;
1450N/A case 1:
1450N/A reg = WM0_PIPEB_ILK;
1450N/A break;
1450N/A case 2:
1450N/A reg = WM0_PIPEC_IVB;
1450N/A break;
1450N/A default:
1450N/A return; /* bad pipe */
1450N/A }
1450N/A
1450N/A ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
1450N/A &sandybridge_display_wm_info,
1450N/A latency, &sprite_wm);
1450N/A if (!ret) {
1450N/A DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A return;
1450N/A }
1450N/A
1450N/A val = I915_READ(reg);
1450N/A val &= ~WM0_PIPE_SPRITE_MASK;
1450N/A I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
1450N/A DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
1450N/A
1450N/A
1450N/A ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
1450N/A pixel_size,
1450N/A &sandybridge_display_srwm_info,
1450N/A SNB_READ_WM1_LATENCY() * 500,
1450N/A &sprite_wm);
1450N/A if (!ret) {
1450N/A DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A return;
1450N/A }
1450N/A I915_WRITE(WM1S_LP_ILK, sprite_wm);
1450N/A
1450N/A /* Only IVB has two more LP watermarks for sprite */
1450N/A if (!IS_IVYBRIDGE(dev))
1450N/A return;
1450N/A
1450N/A ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
1450N/A pixel_size,
1450N/A &sandybridge_display_srwm_info,
1450N/A SNB_READ_WM2_LATENCY() * 500,
1450N/A &sprite_wm);
1450N/A if (!ret) {
1450N/A DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A return;
1450N/A }
1450N/A I915_WRITE(WM2S_LP_IVB, sprite_wm);
1450N/A
1450N/A ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
1450N/A pixel_size,
1450N/A &sandybridge_display_srwm_info,
1450N/A SNB_READ_WM3_LATENCY() * 500,
1450N/A &sprite_wm);
1450N/A if (!ret) {
1450N/A DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A return;
1450N/A }
1450N/A I915_WRITE(WM3S_LP_IVB, sprite_wm);
1450N/A}
1450N/A
1450N/A/**
1450N/A * intel_update_watermarks - update FIFO watermark values based on current modes
1450N/A *
1450N/A * Calculate watermark values for the various WM regs based on current mode
1450N/A * and plane configuration.
1450N/A *
1450N/A * There are several cases to deal with here:
1450N/A * - normal (i.e. non-self-refresh)
1450N/A * - self-refresh (SR) mode
1450N/A * - lines are large relative to FIFO size (buffer can hold up to 2)
1450N/A * - lines are small relative to FIFO size (buffer can hold more than 2
1450N/A * lines), so need to account for TLB latency
1450N/A *
1450N/A * The normal calculation is:
1450N/A * watermark = dotclock * bytes per pixel * latency
1450N/A * where latency is platform & configuration dependent (we assume pessimal
1450N/A * values here).
1450N/A *
1450N/A * The SR calculation is:
1450N/A * watermark = (trunc(latency/line time)+1) * surface width *
1450N/A * bytes per pixel
1450N/A * where
1450N/A * line time = htotal / dotclock
1450N/A * surface width = hdisplay for normal plane and 64 for cursor
1450N/A * and latency is assumed to be high, as above.
1450N/A *
1450N/A * The final value programmed to the register should always be rounded up,
1450N/A * and include an extra 2 entries to account for clock crossings.
1450N/A *
1450N/A * We don't use the sprite, so we can ignore that. And on Crestline we have
1450N/A * to set the non-SR watermarks to 8.
1450N/A */
1450N/Avoid intel_update_watermarks(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (dev_priv->display.update_wm)
1450N/A dev_priv->display.update_wm(dev);
1450N/A}
1450N/A
1450N/Avoid intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
1450N/A uint32_t sprite_width, int pixel_size,
1450N/A bool enable)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (dev_priv->display.update_sprite_wm)
1450N/A dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
1450N/A pixel_size, enable);
1450N/A}
1450N/A
1450N/Astatic struct drm_i915_gem_object *
1450N/Aintel_alloc_context_page(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_gem_object *ctx;
1450N/A int ret;
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev->struct_mutex));
1450N/A
1450N/A ctx = i915_gem_alloc_object(dev, 4096);
1450N/A if (!ctx) {
1450N/A DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
1450N/A return NULL;
1450N/A }
1450N/A
1450N/A ret = i915_gem_object_pin(ctx, 4096, true, false);
1450N/A if (ret) {
1450N/A DRM_ERROR("failed to pin power context: %d\n", ret);
1450N/A goto err_unref;
1450N/A }
1450N/A
1450N/A ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
1450N/A if (ret) {
1450N/A DRM_ERROR("failed to set-domain on power context: %d\n", ret);
1450N/A goto err_unpin;
1450N/A }
1450N/A
1450N/A return ctx;
1450N/A
1450N/Aerr_unpin:
1450N/A i915_gem_object_unpin(ctx);
1450N/Aerr_unref:
1450N/A drm_gem_object_unreference(&ctx->base);
1450N/A return NULL;
1450N/A}
1450N/A
1450N/A/**
1450N/A * Lock protecting IPS related data structures
1450N/A */
1450N/Aspinlock_t mchdev_lock;
1450N/A
1450N/A/* Global for IPS driver to get at the current i915 device. Protected by
1450N/A * mchdev_lock. */
1450N/Astatic struct drm_i915_private *i915_mch_dev;
1450N/A
1450N/Abool ironlake_set_drps(struct drm_device *dev, u8 val)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u16 rgvswctl;
1450N/A
1450N/A ASSERT(MUTEX_HELD(&mchdev_lock));
1450N/A
1450N/A rgvswctl = I915_READ16(MEMSWCTL);
1450N/A if (rgvswctl & MEMCTL_CMD_STS) {
1450N/A DRM_DEBUG("gpu busy, RCS change rejected\n");
1450N/A return false; /* still busy with another command */
1450N/A }
1450N/A
1450N/A rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
1450N/A (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
1450N/A I915_WRITE16(MEMSWCTL, rgvswctl);
1450N/A POSTING_READ16(MEMSWCTL);
1450N/A
1450N/A rgvswctl |= MEMCTL_CMD_STS;
1450N/A I915_WRITE16(MEMSWCTL, rgvswctl);
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/Astatic void ironlake_enable_drps(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 rgvmodectl = I915_READ(MEMMODECTL);
1450N/A u8 fmax, fmin, fstart, vstart;
1450N/A
1450N/A spin_lock_irq(&mchdev_lock);
1450N/A
1450N/A /* Enable temp reporting */
1450N/A I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
1450N/A I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
1450N/A
1450N/A /* 100ms RC evaluation intervals */
1450N/A I915_WRITE(RCUPEI, 100000);
1450N/A I915_WRITE(RCDNEI, 100000);
1450N/A
1450N/A /* Set max/min thresholds to 90ms and 80ms respectively */
1450N/A I915_WRITE(RCBMAXAVG, 90000);
1450N/A I915_WRITE(RCBMINAVG, 80000);
1450N/A
1450N/A I915_WRITE(MEMIHYST, 1);
1450N/A
1450N/A /* Set up min, max, and cur for interrupt handling */
1450N/A fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
1450N/A fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
1450N/A fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
1450N/A MEMMODE_FSTART_SHIFT;
1450N/A
1450N/A vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
1450N/A PXVFREQ_PX_SHIFT;
1450N/A
1450N/A dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
1450N/A dev_priv->ips.fstart = fstart;
1450N/A
1450N/A dev_priv->ips.max_delay = fstart;
1450N/A dev_priv->ips.min_delay = fmin;
1450N/A dev_priv->ips.cur_delay = fstart;
1450N/A
1450N/A DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
1450N/A fmax, fmin, fstart);
1450N/A
1450N/A I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
1450N/A
1450N/A /*
1450N/A * Interrupts will be enabled in ironlake_irq_postinstall
1450N/A */
1450N/A
1450N/A I915_WRITE(VIDSTART, vstart);
1450N/A POSTING_READ(VIDSTART);
1450N/A
1450N/A rgvmodectl |= MEMMODE_SWMODE_EN;
1450N/A I915_WRITE(MEMMODECTL, rgvmodectl);
1450N/A
1450N/A if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
1450N/A DRM_ERROR("stuck trying to change perf mode\n");
1450N/A msleep(1);
1450N/A
1450N/A (void) ironlake_set_drps(dev, fstart);
1450N/A
1450N/A dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
1450N/A I915_READ(0x112e0);
1450N/A dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
1450N/A dev_priv->ips.last_count2 = I915_READ(0x112f4);
1450N/A dev_priv->ips.last_time2 = jiffies;
1450N/A
1450N/A spin_unlock_irq(&mchdev_lock);
1450N/A}
1450N/A
1450N/Astatic void ironlake_disable_drps(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u16 rgvswctl;
1450N/A
1450N/A spin_lock_irq(&mchdev_lock);
1450N/A
1450N/A rgvswctl = I915_READ16(MEMSWCTL);
1450N/A
1450N/A /* Ack interrupts, disable EFC interrupt */
1450N/A I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
1450N/A I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
1450N/A I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
1450N/A I915_WRITE(DEIIR, DE_PCU_EVENT);
1450N/A I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
1450N/A
1450N/A /* Go back to the starting frequency */
1450N/A (void) ironlake_set_drps(dev, dev_priv->ips.fstart);
1450N/A msleep(1);
1450N/A rgvswctl |= MEMCTL_CMD_STS;
1450N/A I915_WRITE(MEMSWCTL, rgvswctl);
1450N/A msleep(1);
1450N/A
1450N/A spin_unlock_irq(&mchdev_lock);
1450N/A}
1450N/A
1450N/A/* There's a funny hw issue where the hw returns all 0 when reading from
1450N/A * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
1450N/A * ourselves, instead of doing a rmw cycle (which might result in us clearing
1450N/A * all limits and the gpu stuck at whatever frequency it is at atm).
1450N/A */
1450N/Astatic u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
1450N/A{
1450N/A u32 limits;
1450N/A
1450N/A limits = 0;
1450N/A
1450N/A if (*val >= dev_priv->rps.max_delay)
1450N/A *val = dev_priv->rps.max_delay;
1450N/A limits |= dev_priv->rps.max_delay << 24;
1450N/A
1450N/A /* Only set the down limit when we've reached the lowest level to avoid
1450N/A * getting more interrupts, otherwise leave this clear. This prevents a
1450N/A * race in the hw when coming out of rc6: There's a tiny window where
1450N/A * the hw runs at the minimal clock before selecting the desired
1450N/A * frequency, if the down threshold expires in that window we will not
1450N/A * receive a down interrupt. */
1450N/A if (*val <= dev_priv->rps.min_delay) {
1450N/A *val = dev_priv->rps.min_delay;
1450N/A limits |= dev_priv->rps.min_delay << 16;
1450N/A }
1450N/A
1450N/A return limits;
1450N/A}
1450N/A
1450N/Avoid gen6_set_rps(struct drm_device *dev, u8 val)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 limits = gen6_rps_limits(dev_priv, &val);
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A WARN_ON(val > dev_priv->rps.max_delay);
1450N/A WARN_ON(val < dev_priv->rps.min_delay);
1450N/A
1450N/A if (val == dev_priv->rps.cur_delay)
1450N/A return;
1450N/A
1450N/A if (IS_HASWELL(dev))
1450N/A I915_WRITE(GEN6_RPNSWREQ,
1450N/A HSW_FREQUENCY(val));
1450N/A else
1450N/A I915_WRITE(GEN6_RPNSWREQ,
1450N/A GEN6_FREQUENCY(val) |
1450N/A GEN6_OFFSET(0) |
1450N/A GEN6_AGGRESSIVE_TURBO);
1450N/A
1450N/A /* Make sure we continue to get interrupts
1450N/A * until we hit the minimum or maximum frequencies.
1450N/A */
1450N/A I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
1450N/A
1450N/A POSTING_READ(GEN6_RPNSWREQ);
1450N/A
1450N/A dev_priv->rps.cur_delay = (u8)val;
1450N/A}
1450N/A
1450N/A/*
1450N/A * Wait until the previous freq change has completed,
1450N/A * or the timeout elapsed, and then update our notion
1450N/A * of the current GPU frequency.
1450N/A */
1450N/Astatic void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A unsigned long timeout = jiffies + msecs_to_jiffies(10);
1450N/A u32 pval;
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A
1450N/A do {
1450N/A pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1450N/A if (time_after(jiffies, timeout)) {
1450N/A DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
1450N/A break;
1450N/A }
1450N/A udelay(10);
1450N/A } while (pval & 1);
1450N/A
1450N/A pval >>= 8;
1450N/A
1450N/A if (pval != dev_priv->rps.cur_delay)
1450N/A DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
1450N/A vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
1450N/A dev_priv->rps.cur_delay,
1450N/A vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
1450N/A
1450N/A dev_priv->rps.cur_delay = (u8)pval;
1450N/A}
1450N/A
1450N/Avoid valleyview_set_rps(struct drm_device *dev, u8 val)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A gen6_rps_limits(dev_priv, &val);
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A WARN_ON(val > dev_priv->rps.max_delay);
1450N/A WARN_ON(val < dev_priv->rps.min_delay);
1450N/A
1450N/A vlv_update_rps_cur_delay(dev_priv);
1450N/A
1450N/A DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
1450N/A vlv_gpu_freq(dev_priv->mem_freq,
1450N/A dev_priv->rps.cur_delay),
1450N/A dev_priv->rps.cur_delay,
1450N/A vlv_gpu_freq(dev_priv->mem_freq, val), val);
1450N/A
1450N/A if (val == dev_priv->rps.cur_delay)
1450N/A return;
1450N/A
1450N/A vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
1450N/A
1450N/A dev_priv->rps.cur_delay = val;
1450N/A}
1450N/A
1450N/A
1450N/Astatic void gen6_disable_rps(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(GEN6_RC_CONTROL, 0);
1450N/A I915_WRITE(GEN6_RPNSWREQ, 1UL << 31);
1450N/A I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
1450N/A I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
1450N/A /* Complete PM interrupt masking here doesn't race with the rps work
1450N/A * item again unmasking PM interrupts because that is using a different
1450N/A * register (PMIMR) to mask PM interrupts. The only risk is in leaving
1450N/A * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
1450N/A
1450N/A spin_lock_irq(&dev_priv->rps.lock);
1450N/A dev_priv->rps.pm_iir = 0;
1450N/A spin_unlock_irq(&dev_priv->rps.lock);
1450N/A
1450N/A I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
1450N/A}
1450N/A
1450N/Astatic void valleyview_disable_rps(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(GEN6_RC_CONTROL, 0);
1450N/A I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
1450N/A I915_WRITE(GEN6_PMIER, 0);
1450N/A /* Complete PM interrupt masking here doesn't race with the rps work
1450N/A * item again unmasking PM interrupts because that is using a different
1450N/A * register (PMIMR) to mask PM interrupts. The only risk is in leaving
1450N/A * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
1450N/A
1450N/A spin_lock_irq(&dev_priv->rps.lock);
1450N/A dev_priv->rps.pm_iir = 0;
1450N/A spin_unlock_irq(&dev_priv->rps.lock);
1450N/A
1450N/A I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
1450N/A
1450N/A if (dev_priv->vlv_pctx) {
1450N/A drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
1450N/A dev_priv->vlv_pctx = NULL;
1450N/A }
1450N/A}
1450N/A
1450N/Aint intel_enable_rc6(const struct drm_device *dev)
1450N/A{
1450N/A /* Respect the kernel parameter if it is set */
1450N/A if (i915_enable_rc6 >= 0)
1450N/A return i915_enable_rc6;
1450N/A
1450N/A /* Disable RC6 on Ironlake */
1450N/A if (INTEL_INFO(dev)->gen == 5)
1450N/A return 0;
1450N/A
1450N/A if (IS_HASWELL(dev)) {
1450N/A DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
1450N/A return INTEL_RC6_ENABLE;
1450N/A }
1450N/A
1450N/A /* snb/ivb have more than one rc6 state. */
1450N/A if (INTEL_INFO(dev)->gen == 6) {
1450N/A DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
1450N/A return INTEL_RC6_ENABLE;
1450N/A }
1450N/A
1450N/A DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
1450N/A return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
1450N/A}
1450N/A
1450N/Astatic void gen6_enable_rps(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct intel_ring_buffer *ring;
1450N/A u32 rp_state_cap;
1450N/A u32 gt_perf_status;
1450N/A u32 rc6vids, pcu_mbox, rc6_mask = 0;
1450N/A u32 gtfifodbg;
1450N/A int rc6_mode;
1450N/A int i, ret;
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A
1450N/A /* Here begins a magic sequence of register writes to enable
1450N/A * auto-downclocking.
1450N/A *
1450N/A * Perhaps there might be some value in exposing these to
1450N/A * userspace...
1450N/A */
1450N/A I915_WRITE(GEN6_RC_STATE, 0);
1450N/A
1450N/A /* Clear the DBG now so we don't confuse earlier errors */
1450N/A if ((gtfifodbg = I915_READ(GTFIFODBG))) {
1450N/A DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
1450N/A I915_WRITE(GTFIFODBG, gtfifodbg);
1450N/A }
1450N/A
1450N/A gen6_gt_force_wake_get(dev_priv);
1450N/A
1450N/A rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1450N/A gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1450N/A
1450N/A /* In units of 100MHz */
1450N/A dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
1450N/A dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
1450N/A dev_priv->rps.cur_delay = 0;
1450N/A
1450N/A /* disable the counters and set deterministic thresholds */
1450N/A I915_WRITE(GEN6_RC_CONTROL, 0);
1450N/A
1450N/A I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
1450N/A I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
1450N/A I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
1450N/A I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
1450N/A I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
1450N/A
1450N/A for_each_ring(ring, dev_priv, i)
1450N/A I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
1450N/A
1450N/A I915_WRITE(GEN6_RC_SLEEP, 0);
1450N/A I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
1450N/A I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
1450N/A I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
1450N/A I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
1450N/A
1450N/A /* Check if we are enabling RC6 */
1450N/A rc6_mode = intel_enable_rc6(dev_priv->dev);
1450N/A if (rc6_mode & INTEL_RC6_ENABLE)
1450N/A rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
1450N/A
1450N/A /* We don't use those on Haswell */
1450N/A if (!IS_HASWELL(dev)) {
1450N/A if (rc6_mode & INTEL_RC6p_ENABLE)
1450N/A rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
1450N/A
1450N/A if (rc6_mode & INTEL_RC6pp_ENABLE)
1450N/A rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
1450N/A }
1450N/A
1450N/A DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1450N/A (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
1450N/A (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
1450N/A (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
1450N/A
1450N/A I915_WRITE(GEN6_RC_CONTROL,
1450N/A rc6_mask |
1450N/A GEN6_RC_CTL_EI_MODE(1) |
1450N/A GEN6_RC_CTL_HW_ENABLE);
1450N/A
1450N/A if (IS_HASWELL(dev)) {
1450N/A I915_WRITE(GEN6_RPNSWREQ,
1450N/A HSW_FREQUENCY(10));
1450N/A I915_WRITE(GEN6_RC_VIDEO_FREQ,
1450N/A HSW_FREQUENCY(12));
1450N/A } else {
1450N/A I915_WRITE(GEN6_RPNSWREQ,
1450N/A GEN6_FREQUENCY(10) |
1450N/A GEN6_OFFSET(0) |
1450N/A GEN6_AGGRESSIVE_TURBO);
1450N/A I915_WRITE(GEN6_RC_VIDEO_FREQ,
1450N/A GEN6_FREQUENCY(12));
1450N/A }
1450N/A
1450N/A I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
1450N/A I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
1450N/A dev_priv->rps.max_delay << 24 |
1450N/A dev_priv->rps.min_delay << 16);
1450N/A
1450N/A I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
1450N/A I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
1450N/A I915_WRITE(GEN6_RP_UP_EI, 66000);
1450N/A I915_WRITE(GEN6_RP_DOWN_EI, 350000);
1450N/A
1450N/A I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
1450N/A I915_WRITE(GEN6_RP_CONTROL,
1450N/A GEN6_RP_MEDIA_TURBO |
1450N/A GEN6_RP_MEDIA_HW_NORMAL_MODE |
1450N/A GEN6_RP_MEDIA_IS_GFX |
1450N/A GEN6_RP_ENABLE |
1450N/A GEN6_RP_UP_BUSY_AVG |
1450N/A (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
1450N/A
1450N/A ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
1450N/A if (!ret) {
1450N/A pcu_mbox = 0;
1450N/A ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
1450N/A if (ret && pcu_mbox & (1UL<<31)) { /* OC supported */
1450N/A DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
1450N/A (dev_priv->rps.max_delay & 0xff) * 50,
1450N/A (pcu_mbox & 0xff) * 50);
1450N/A dev_priv->rps.hw_max = pcu_mbox & 0xff;
1450N/A }
1450N/A } else {
1450N/A DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
1450N/A }
1450N/A
1450N/A gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
1450N/A
1450N/A /* requires MSI enabled */
1450N/A I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
1450N/A spin_lock_irq(&dev_priv->rps.lock);
1450N/A /* FIXME: Our interrupt enabling sequence is bonghits.
1450N/A * dev_priv->rps.pm_iir really should be 0 here. */
1450N/A dev_priv->rps.pm_iir = 0;
1450N/A I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
1450N/A I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
1450N/A spin_unlock_irq(&dev_priv->rps.lock);
1450N/A /* enable all PM interrupts */
1450N/A I915_WRITE(GEN6_PMINTRMSK, 0);
1450N/A
1450N/A rc6vids = 0;
1450N/A ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1450N/A if (IS_GEN6(dev) && ret) {
1450N/A DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
1450N/A } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
1450N/A DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
1450N/A GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
1450N/A rc6vids &= 0xffff00;
1450N/A rc6vids |= GEN6_ENCODE_RC6_VID(450);
1450N/A ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
1450N/A if (ret)
1450N/A DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
1450N/A }
1450N/A
1450N/A gen6_gt_force_wake_put(dev_priv);
1450N/A}
1450N/A
1450N/Astatic void gen6_update_ring_freq(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int min_freq = 15;
1450N/A unsigned int gpu_freq;
1450N/A unsigned int max_ia_freq, min_ring_freq;
1450N/A int scaling_factor = 180;
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A
1450N/A if (cpu_freq == 0)
1450N/A return;
1450N/A
1450N/A max_ia_freq = cpu_freq;
1450N/A DRM_INFO("CPU frequence %d MHz", max_ia_freq);
1450N/A min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
1450N/A /* convert DDR frequency from units of 133.3MHz to bandwidth */
1450N/A min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
1450N/A
1450N/A /*
1450N/A * For each potential GPU frequency, load a ring frequency we'd like
1450N/A * to use for memory access. We do this by specifying the IA frequency
1450N/A * the PCU should use as a reference to determine the ring frequency.
1450N/A */
1450N/A for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
1450N/A gpu_freq--) {
1450N/A int diff = dev_priv->rps.max_delay - gpu_freq;
1450N/A unsigned int ia_freq = 0, ring_freq = 0;
1450N/A
1450N/A if (IS_HASWELL(dev)) {
1450N/A ring_freq = (gpu_freq * 5 + 3) / 4;
1450N/A ring_freq = max(min_ring_freq, ring_freq);
1450N/A /* leave ia_freq as the default, chosen by cpufreq */
1450N/A } else {
1450N/A /* On older processors, there is no separate ring
1450N/A * clock domain, so in order to boost the bandwidth
1450N/A * of the ring, we need to upclock the CPU (ia_freq).
1450N/A *
1450N/A * For GPU frequencies less than 750MHz, just use the lowest
1450N/A * ring freq.
1450N/A */
1450N/A if (gpu_freq < min_freq)
1450N/A ia_freq = 800;
1450N/A else
1450N/A ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
1450N/A ia_freq = ia_freq / 100 + (((ia_freq % 100) >= 50)? 1 : 0);
1450N/A }
1450N/A
1450N/A sandybridge_pcode_write(dev_priv,
1450N/A GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
1450N/A ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
1450N/A ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
1450N/A gpu_freq);
1450N/A }
1450N/A}
1450N/A
1450N/Aint valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A u32 val, rp0;
1450N/A
1450N/A val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
1450N/A
1450N/A rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
1450N/A /* Clamp to max */
1450N/A rp0 = min(rp0, 0xea);
1450N/A
1450N/A return rp0;
1450N/A}
1450N/A
1450N/Astatic int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A u32 val, rpe;
1450N/A
1450N/A val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
1450N/A rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
1450N/A val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
1450N/A rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
1450N/A
1450N/A return rpe;
1450N/A}
1450N/A
1450N/Aint valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
1450N/A}
1450N/A#if 0
1450N/Astatic void vlv_rps_timer_work(struct work_struct *work)
1450N/A{
1450N/A drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1450N/A rps.vlv_work.work);
1450N/A
1450N/A /*
1450N/A * Timer fired, we must be idle. Drop to min voltage state.
1450N/A * Note: we use RPe here since it should match the
1450N/A * Vmin we were shooting for. That should give us better
1450N/A * perf when we come back out of RC6 than if we used the
1450N/A * min freq available.
1450N/A */
1450N/A mutex_lock(&dev_priv->rps.hw_lock);
1450N/A if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1450N/A valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
1450N/A mutex_unlock(&dev_priv->rps.hw_lock);
1450N/A}
1450N/A#endif
1450N/Astatic void valleyview_setup_pctx(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_i915_gem_object *pctx;
1450N/A unsigned long pctx_paddr;
1450N/A u32 pcbr;
1450N/A int pctx_size = 24*1024;
1450N/A
1450N/A pcbr = I915_READ(VLV_PCBR);
1450N/A if (pcbr) {
1450N/A /* BIOS set it up already, grab the pre-alloc'd space */
1450N/A int pcbr_offset;
1450N/A
1450N/A pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
1450N/A pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
1450N/A pcbr_offset,
1450N/A -1,
1450N/A pctx_size);
1450N/A goto out;
1450N/A }
1450N/A
1450N/A /*
1450N/A * From the Gunit register HAS:
1450N/A * The Gfx driver is expected to program this register and ensure
1450N/A * proper allocation within Gfx stolen memory. For example, this
1450N/A * register should be programmed such than the PCBR range does not
1450N/A * overlap with other ranges, such as the frame buffer, protected
1450N/A * memory, or any other relevant ranges.
1450N/A */
1450N/A pctx = i915_gem_object_create_stolen(dev, pctx_size);
1450N/A if (!pctx) {
1450N/A DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
1450N/A return;
1450N/A }
1450N/A
1450N/A pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
1450N/A I915_WRITE(VLV_PCBR, pctx_paddr);
1450N/A
1450N/Aout:
1450N/A dev_priv->vlv_pctx = pctx;
1450N/A}
1450N/A
1450N/Astatic void valleyview_enable_rps(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct intel_ring_buffer *ring;
1450N/A u32 gtfifodbg, val;
1450N/A int i;
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A
1450N/A if ((gtfifodbg = I915_READ(GTFIFODBG))) {
1450N/A DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
1450N/A I915_WRITE(GTFIFODBG, gtfifodbg);
1450N/A }
1450N/A
1450N/A valleyview_setup_pctx(dev);
1450N/A
1450N/A gen6_gt_force_wake_get(dev_priv);
1450N/A
1450N/A I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
1450N/A I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
1450N/A I915_WRITE(GEN6_RP_UP_EI, 66000);
1450N/A I915_WRITE(GEN6_RP_DOWN_EI, 350000);
1450N/A
1450N/A I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
1450N/A
1450N/A I915_WRITE(GEN6_RP_CONTROL,
1450N/A GEN6_RP_MEDIA_TURBO |
1450N/A GEN6_RP_MEDIA_HW_NORMAL_MODE |
1450N/A GEN6_RP_MEDIA_IS_GFX |
1450N/A GEN6_RP_ENABLE |
1450N/A GEN6_RP_UP_BUSY_AVG |
1450N/A GEN6_RP_DOWN_IDLE_CONT);
1450N/A
1450N/A I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
1450N/A I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
1450N/A I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
1450N/A
1450N/A for_each_ring(ring, dev_priv, i)
1450N/A I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
1450N/A
1450N/A I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
1450N/A
1450N/A /* allows RC6 residency counter to work */
1450N/A I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
1450N/A I915_WRITE(GEN6_RC_CONTROL,
1450N/A GEN7_RC_CTL_TO_MODE);
1450N/A
1450N/A val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1450N/A switch ((val >> 6) & 3) {
1450N/A case 0:
1450N/A case 1:
1450N/A dev_priv->mem_freq = 800;
1450N/A break;
1450N/A case 2:
1450N/A dev_priv->mem_freq = 1066;
1450N/A break;
1450N/A case 3:
1450N/A dev_priv->mem_freq = 1333;
1450N/A break;
1450N/A }
1450N/A DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
1450N/A
1450N/A DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
1450N/A DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
1450N/A
1450N/A dev_priv->rps.cur_delay = (val >> 8) & 0xff;
1450N/A DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
1450N/A vlv_gpu_freq(dev_priv->mem_freq,
1450N/A dev_priv->rps.cur_delay),
1450N/A dev_priv->rps.cur_delay);
1450N/A
1450N/A dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
1450N/A dev_priv->rps.hw_max = dev_priv->rps.max_delay;
1450N/A DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
1450N/A vlv_gpu_freq(dev_priv->mem_freq,
1450N/A dev_priv->rps.max_delay),
1450N/A dev_priv->rps.max_delay);
1450N/A
1450N/A dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
1450N/A DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
1450N/A vlv_gpu_freq(dev_priv->mem_freq,
1450N/A dev_priv->rps.rpe_delay),
1450N/A dev_priv->rps.rpe_delay);
1450N/A
1450N/A dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
1450N/A DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
1450N/A vlv_gpu_freq(dev_priv->mem_freq,
1450N/A dev_priv->rps.min_delay),
1450N/A dev_priv->rps.min_delay);
1450N/A
1450N/A DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
1450N/A vlv_gpu_freq(dev_priv->mem_freq,
1450N/A dev_priv->rps.rpe_delay),
1450N/A dev_priv->rps.rpe_delay);
1450N/A
1450N/A //INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
1450N/A
1450N/A valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
1450N/A
1450N/A /* requires MSI enabled */
1450N/A I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
1450N/A spin_lock_irq(&dev_priv->rps.lock);
1450N/A WARN_ON(dev_priv->rps.pm_iir != 0);
1450N/A I915_WRITE(GEN6_PMIMR, 0);
1450N/A spin_unlock_irq(&dev_priv->rps.lock);
1450N/A /* enable all PM interrupts */
1450N/A I915_WRITE(GEN6_PMINTRMSK, 0);
1450N/A
1450N/A gen6_gt_force_wake_put(dev_priv);
1450N/A}
1450N/A
1450N/Avoid ironlake_teardown_rc6(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (dev_priv->ips.renderctx) {
1450N/A i915_gem_object_unpin(dev_priv->ips.renderctx);
1450N/A drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
1450N/A dev_priv->ips.renderctx = NULL;
1450N/A }
1450N/A
1450N/A if (dev_priv->ips.pwrctx) {
1450N/A i915_gem_object_unpin(dev_priv->ips.pwrctx);
1450N/A drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
1450N/A dev_priv->ips.pwrctx = NULL;
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void ironlake_disable_rc6(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (I915_READ(PWRCTXA)) {
1450N/A /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
1450N/A I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
1450N/A wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
1450N/A 50);
1450N/A
1450N/A I915_WRITE(PWRCTXA, 0);
1450N/A POSTING_READ(PWRCTXA);
1450N/A
1450N/A I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
1450N/A POSTING_READ(RSTDBYCTL);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic int ironlake_setup_rc6(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (dev_priv->ips.renderctx == NULL)
1450N/A dev_priv->ips.renderctx = intel_alloc_context_page(dev);
1450N/A if (!dev_priv->ips.renderctx)
1450N/A return -ENOMEM;
1450N/A
1450N/A if (dev_priv->ips.pwrctx == NULL)
1450N/A dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
1450N/A if (!dev_priv->ips.pwrctx) {
1450N/A ironlake_teardown_rc6(dev);
1450N/A return -ENOMEM;
1450N/A }
1450N/A
1450N/A return 0;
1450N/A}
1450N/A
1450N/Astatic void ironlake_enable_rc6(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1450N/A bool was_interruptible;
1450N/A int ret;
1450N/A
1450N/A /* rc6 disabled by default due to repeated reports of hanging during
1450N/A * boot and resume.
1450N/A */
1450N/A if (!intel_enable_rc6(dev))
1450N/A return;
1450N/A
1450N/A WARN_ON(!mutex_is_locked(&dev->struct_mutex));
1450N/A
1450N/A ret = ironlake_setup_rc6(dev);
1450N/A if (ret)
1450N/A return;
1450N/A
1450N/A was_interruptible = dev_priv->mm.interruptible;
1450N/A dev_priv->mm.interruptible = false;
1450N/A
1450N/A /*
1450N/A * GPU can automatically power down the render unit if given a page
1450N/A * to save state.
1450N/A */
1450N/A ret = intel_ring_begin(ring, 6);
1450N/A if (ret) {
1450N/A ironlake_teardown_rc6(dev);
1450N/A dev_priv->mm.interruptible = was_interruptible;
1450N/A return;
1450N/A }
1450N/A
1450N/A intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
1450N/A intel_ring_emit(ring, MI_SET_CONTEXT);
1450N/A intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
1450N/A MI_MM_SPACE_GTT |
1450N/A MI_SAVE_EXT_STATE_EN |
1450N/A MI_RESTORE_EXT_STATE_EN |
1450N/A MI_RESTORE_INHIBIT);
1450N/A intel_ring_emit(ring, MI_SUSPEND_FLUSH);
1450N/A intel_ring_emit(ring, MI_NOOP);
1450N/A intel_ring_emit(ring, MI_FLUSH);
1450N/A intel_ring_advance(ring);
1450N/A
1450N/A /*
1450N/A * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
1450N/A * does an implicit flush, combined with MI_FLUSH above, it should be
1450N/A * safe to assume that renderctx is valid
1450N/A */
1450N/A ret = intel_ring_idle(ring);
1450N/A dev_priv->mm.interruptible = was_interruptible;
1450N/A if (ret) {
1450N/A DRM_ERROR("failed to enable ironlake power savings\n");
1450N/A ironlake_teardown_rc6(dev);
1450N/A return;
1450N/A }
1450N/A
1450N/A I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
1450N/A I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
1450N/A}
1450N/A
1450N/Astatic unsigned long intel_pxfreq(u32 vidfreq)
1450N/A{
1450N/A unsigned long freq;
1450N/A int div = (vidfreq & 0x3f0000) >> 16;
1450N/A int post = (vidfreq & 0x3000) >> 12;
1450N/A int pre = (vidfreq & 0x7);
1450N/A
1450N/A if (!pre)
1450N/A return 0;
1450N/A
1450N/A freq = ((div * 133333) / ((1<<post) * pre));
1450N/A
1450N/A return freq;
1450N/A}
1450N/A
1450N/Astatic const struct cparams {
1450N/A u16 i;
1450N/A u16 t;
1450N/A u16 m;
1450N/A u16 c;
1450N/A} cparams[] = {
1450N/A { 1, 1333, 301, 28664 },
1450N/A { 1, 1066, 294, 24460 },
1450N/A { 1, 800, 294, 25192 },
1450N/A { 0, 1333, 276, 27605 },
1450N/A { 0, 1066, 276, 27605 },
1450N/A { 0, 800, 231, 23784 },
1450N/A};
1450N/A
1450N/Astatic void intel_init_emon(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 lcfuse;
1450N/A u8 pxw[16];
1450N/A int i;
1450N/A
1450N/A /* Disable to program */
1450N/A I915_WRITE(ECR, 0);
1450N/A POSTING_READ(ECR);
1450N/A
1450N/A /* Program energy weights for various events */
1450N/A I915_WRITE(SDEW, 0x15040d00);
1450N/A I915_WRITE(CSIEW0, 0x007f0000);
1450N/A I915_WRITE(CSIEW1, 0x1e220004);
1450N/A I915_WRITE(CSIEW2, 0x04000004);
1450N/A
1450N/A for (i = 0; i < 5; i++)
1450N/A I915_WRITE(PEW + (i * 4), 0);
1450N/A for (i = 0; i < 3; i++)
1450N/A I915_WRITE(DEW + (i * 4), 0);
1450N/A
1450N/A /* Program P-state weights to account for frequency power adjustment */
1450N/A for (i = 0; i < 16; i++) {
1450N/A u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
1450N/A unsigned long freq = intel_pxfreq(pxvidfreq);
1450N/A unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
1450N/A PXVFREQ_PX_SHIFT;
1450N/A unsigned long val;
1450N/A
1450N/A val = vid * vid;
1450N/A val *= (freq / 1000);
1450N/A val *= 255;
1450N/A val /= (127*127*900);
1450N/A if (val > 0xff)
1450N/A DRM_ERROR("bad pxval: %ld\n", val);
1450N/A pxw[i] = (u8)val;
1450N/A }
1450N/A /* Render standby states get 0 weight */
1450N/A pxw[14] = 0;
1450N/A pxw[15] = 0;
1450N/A
1450N/A for (i = 0; i < 4; i++) {
1450N/A u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
1450N/A (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
1450N/A I915_WRITE(PXW + (i * 4), val);
1450N/A }
1450N/A
1450N/A /* Adjust magic regs to magic values (more experimental results) */
1450N/A I915_WRITE(OGW0, 0);
1450N/A I915_WRITE(OGW1, 0);
1450N/A I915_WRITE(EG0, 0x00007f00);
1450N/A I915_WRITE(EG1, 0x0000000e);
1450N/A I915_WRITE(EG2, 0x000e0000);
1450N/A I915_WRITE(EG3, 0x68000300);
1450N/A I915_WRITE(EG4, 0x42000000);
1450N/A I915_WRITE(EG5, 0x00140031);
1450N/A I915_WRITE(EG6, 0);
1450N/A I915_WRITE(EG7, 0);
1450N/A
1450N/A for (i = 0; i < 8; i++)
1450N/A I915_WRITE(PXWL + (i * 4), 0);
1450N/A
1450N/A /* Enable PMON + select events */
1450N/A I915_WRITE(ECR, 0x80000019);
1450N/A
1450N/A lcfuse = I915_READ(LCFUSE02);
1450N/A
1450N/A dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
1450N/A}
1450N/A
1450N/Avoid intel_disable_gt_powersave(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A /* Interrupts should be disabled already to avoid re-arming. */
1450N/A /* fix me i915_quiesce */
1450N/A// WARN_ON(dev->irq_enabled);
1450N/A
1450N/A if (IS_IRONLAKE_M(dev)) {
1450N/A ironlake_disable_drps(dev);
1450N/A ironlake_disable_rc6(dev);
1450N/A } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
1450N/A del_timer_sync(&dev_priv->rps.delayed_resume_timer);
1450N/A// if (IS_VALLEYVIEW(dev))
1450N/A// cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
1450N/A mutex_lock(&dev_priv->rps.hw_lock);
1450N/A if (IS_VALLEYVIEW(dev))
1450N/A valleyview_disable_rps(dev);
1450N/A else
1450N/A gen6_disable_rps(dev);
1450N/A mutex_unlock(&dev_priv->rps.hw_lock);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void intel_gen6_powersave_work(struct work_struct *work)
1450N/A{
1450N/A drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1450N/A rps.delayed_resume_work);
1450N/A struct drm_device *dev = dev_priv->dev;
1450N/A
1450N/A mutex_lock(&dev_priv->rps.hw_lock);
1450N/A
1450N/A if (IS_VALLEYVIEW(dev)) {
1450N/A valleyview_enable_rps(dev);
1450N/A } else {
1450N/A gen6_enable_rps(dev);
1450N/A gen6_update_ring_freq(dev);
1450N/A }
1450N/A mutex_unlock(&dev_priv->rps.hw_lock);
1450N/A}
1450N/A
1450N/Avoid
1450N/Aintel_gen6_powersave_work_timer(void *device)
1450N/A{
1450N/A struct drm_device *dev = (struct drm_device *)device;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A (void) queue_work(dev_priv->wq, &dev_priv->rps.delayed_resume_work);
1450N/A}
1450N/Avoid intel_enable_gt_powersave(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (IS_IRONLAKE_M(dev)) {
1450N/A ironlake_enable_drps(dev);
1450N/A ironlake_enable_rc6(dev);
1450N/A intel_init_emon(dev);
1450N/A } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1450N/A /*
1450N/A * PCU communication is slow and this doesn't need to be
1450N/A * done at any specific time, so do this out of our fast path
1450N/A * to make resume and init faster.
1450N/A */
1450N/A test_set_timer(&dev_priv->rps.delayed_resume_timer, DRM_HZ);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void ibx_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A /*
1450N/A * On Ibex Peak and Cougar Point, we need to disable clock
1450N/A * gating for the panel power sequencer or it will fail to
1450N/A * start up when no ports are active.
1450N/A */
1450N/A I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
1450N/A}
1450N/A
1450N/Astatic void g4x_disable_trickle_feed(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int pipe;
1450N/A
1450N/A for_each_pipe(pipe) {
1450N/A I915_WRITE(DSPCNTR(pipe),
1450N/A I915_READ(DSPCNTR(pipe)) |
1450N/A DISPPLANE_TRICKLE_FEED_DISABLE);
1450N/A intel_flush_display_plane(dev_priv, pipe);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void ironlake_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
1450N/A
1450N/A /* Required for FBC */
1450N/A dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
1450N/A ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
1450N/A ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
1450N/A
1450N/A I915_WRITE(PCH_3DCGDIS0,
1450N/A MARIUNIT_CLOCK_GATE_DISABLE |
1450N/A SVSMUNIT_CLOCK_GATE_DISABLE);
1450N/A I915_WRITE(PCH_3DCGDIS1,
1450N/A VFMUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A /*
1450N/A * According to the spec the following bits should be set in
1450N/A * order to enable memory self-refresh
1450N/A * The bit 22/21 of 0x42004
1450N/A * The bit 5 of 0x42020
1450N/A * The bit 15 of 0x45000
1450N/A */
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN2,
1450N/A (I915_READ(ILK_DISPLAY_CHICKEN2) |
1450N/A ILK_DPARB_GATE | ILK_VSDPFD_FULL));
1450N/A dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
1450N/A I915_WRITE(DISP_ARB_CTL,
1450N/A (I915_READ(DISP_ARB_CTL) |
1450N/A DISP_FBC_WM_DIS));
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A /*
1450N/A * Based on the document from hardware guys the following bits
1450N/A * should be set unconditionally in order to enable FBC.
1450N/A * The bit 22 of 0x42000
1450N/A * The bit 22 of 0x42004
1450N/A * The bit 7,8,9 of 0x42020.
1450N/A */
1450N/A if (IS_IRONLAKE_M(dev)) {
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN1,
1450N/A I915_READ(ILK_DISPLAY_CHICKEN1) |
1450N/A ILK_FBCQ_DIS);
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN2,
1450N/A I915_READ(ILK_DISPLAY_CHICKEN2) |
1450N/A ILK_DPARB_GATE);
1450N/A }
1450N/A
1450N/A I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
1450N/A
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN2,
1450N/A I915_READ(ILK_DISPLAY_CHICKEN2) |
1450N/A ILK_ELPIN_409_SELECT);
1450N/A I915_WRITE(_3D_CHICKEN2,
1450N/A _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
1450N/A _3D_CHICKEN2_WM_READ_PIPELINED);
1450N/A
1450N/A /* WaDisableRenderCachePipelinedFlush */
1450N/A I915_WRITE(CACHE_MODE_0,
1450N/A _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
1450N/A
1450N/A g4x_disable_trickle_feed(dev);
1450N/A
1450N/A ibx_init_clock_gating(dev);
1450N/A}
1450N/A
1450N/Astatic void cpt_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A int pipe;
1450N/A uint32_t val;
1450N/A
1450N/A /*
1450N/A * On Ibex Peak and Cougar Point, we need to disable clock
1450N/A * gating for the panel power sequencer or it will fail to
1450N/A * start up when no ports are active.
1450N/A */
1450N/A I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
1450N/A I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
1450N/A DPLS_EDP_PPS_FIX_DIS);
1450N/A /* The below fixes the weird display corruption, a few pixels shifted
1450N/A * downward, on (only) LVDS of some HP laptops with IVY.
1450N/A */
1450N/A for_each_pipe(pipe) {
1450N/A val = I915_READ(TRANS_CHICKEN2(pipe));
1450N/A val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1450N/A val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
1450N/A if (dev_priv->vbt.fdi_rx_polarity_inverted)
1450N/A val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
1450N/A val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1450N/A val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
1450N/A val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
1450N/A I915_WRITE(TRANS_CHICKEN2(pipe), val);
1450N/A }
1450N/A /* WADP0ClockGatingDisable */
1450N/A for_each_pipe(pipe) {
1450N/A I915_WRITE(TRANS_CHICKEN1(pipe),
1450N/A TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void gen6_check_mch_setup(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t tmp;
1450N/A
1450N/A tmp = I915_READ(MCH_SSKPD);
1450N/A if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
1450N/A DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
1450N/A DRM_INFO("This can cause pipe underruns and display issues.\n");
1450N/A DRM_INFO("Please upgrade your BIOS to fix this.\n");
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void gen6_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
1450N/A
1450N/A I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
1450N/A
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN2,
1450N/A I915_READ(ILK_DISPLAY_CHICKEN2) |
1450N/A ILK_ELPIN_409_SELECT);
1450N/A
1450N/A /* WaDisableHiZPlanesWhenMSAAEnabled */
1450N/A I915_WRITE(_3D_CHICKEN,
1450N/A _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
1450N/A
1450N/A /* WaSetupGtModeTdRowDispatch */
1450N/A if (IS_SNB_GT1(dev))
1450N/A I915_WRITE(GEN6_GT_MODE,
1450N/A _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
1450N/A
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A I915_WRITE(CACHE_MODE_0,
1450N/A _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1450N/A
1450N/A I915_WRITE(GEN6_UCGCTL1,
1450N/A I915_READ(GEN6_UCGCTL1) |
1450N/A GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN6_CSUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
1450N/A * gating disable must be set. Failure to set it results in
1450N/A * flickering pixels due to Z write ordering failures after
1450N/A * some amount of runtime in the Mesa "fire" demo, and Unigine
1450N/A * Sanctuary and Tropics, and apparently anything else with
1450N/A * alpha test or pixel discard.
1450N/A *
1450N/A * According to the spec, bit 11 (RCCUNIT) must also be set,
1450N/A * but we didn't debug actual testcases to find it out.
1450N/A *
1450N/A * Also apply WaDisableVDSUnitClockGating and
1450N/A * WaDisableRCPBUnitClockGating.
1450N/A */
1450N/A I915_WRITE(GEN6_UCGCTL2,
1450N/A GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A /* Bspec says we need to always set all mask bits. */
1450N/A I915_WRITE(_3D_CHICKEN3, (0xFFFFUL << 16) |
1450N/A _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
1450N/A
1450N/A /*
1450N/A * According to the spec the following bits should be
1450N/A * set in order to enable memory self-refresh and fbc:
1450N/A * The bit21 and bit22 of 0x42000
1450N/A * The bit21 and bit22 of 0x42004
1450N/A * The bit5 and bit7 of 0x42020
1450N/A * The bit14 of 0x70180
1450N/A * The bit14 of 0x71180
1450N/A */
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN1,
1450N/A I915_READ(ILK_DISPLAY_CHICKEN1) |
1450N/A ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
1450N/A I915_WRITE(ILK_DISPLAY_CHICKEN2,
1450N/A I915_READ(ILK_DISPLAY_CHICKEN2) |
1450N/A ILK_DPARB_GATE | ILK_VSDPFD_FULL);
1450N/A I915_WRITE(ILK_DSPCLK_GATE_D,
1450N/A I915_READ(ILK_DSPCLK_GATE_D) |
1450N/A ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
1450N/A ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
1450N/A
1450N/A /* WaMbcDriverBootEnable */
1450N/A I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
1450N/A GEN6_MBCTL_ENABLE_BOOT_FETCH);
1450N/A
1450N/A g4x_disable_trickle_feed(dev);
1450N/A
1450N/A /* The default value should be 0x200 according to docs, but the two
1450N/A * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
1450N/A I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffffUL));
1450N/A I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
1450N/A
1450N/A cpt_init_clock_gating(dev);
1450N/A
1450N/A gen6_check_mch_setup(dev);
1450N/A}
1450N/A
1450N/Astatic void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
1450N/A
1450N/A reg &= ~GEN7_FF_SCHED_MASK;
1450N/A reg |= GEN7_FF_TS_SCHED_HW;
1450N/A reg |= GEN7_FF_VS_SCHED_HW;
1450N/A reg |= GEN7_FF_DS_SCHED_HW;
1450N/A
1450N/A if (IS_HASWELL(dev_priv->dev))
1450N/A reg &= ~GEN7_FF_VS_REF_CNT_FFME;
1450N/A
1450N/A I915_WRITE(GEN7_FF_THREAD_MODE, reg);
1450N/A}
1450N/A
1450N/Astatic void lpt_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A /*
1450N/A * TODO: this bit should only be enabled when really needed, then
1450N/A * disabled when not needed anymore in order to save power.
1450N/A */
1450N/A if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
1450N/A I915_WRITE(SOUTH_DSPCLK_GATE_D,
1450N/A I915_READ(SOUTH_DSPCLK_GATE_D) |
1450N/A PCH_LP_PARTITION_LEVEL_DISABLE);
1450N/A
1450N/A /* WADPOClockGatingDisable:hsw */
1450N/A I915_WRITE(_TRANSA_CHICKEN1,
1450N/A I915_READ(_TRANSA_CHICKEN1) |
1450N/A TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
1450N/A}
1450N/A
1450N/Astatic void lpt_suspend_hw(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
1450N/A uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
1450N/A
1450N/A val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
1450N/A I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void haswell_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
1450N/A * This implements the WaDisableRCZUnitClockGating workaround.
1450N/A */
1450N/A I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
1450N/A I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
1450N/A GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
1450N/A
1450N/A /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
1450N/A I915_WRITE(GEN7_L3CNTLREG1,
1450N/A GEN7_WA_FOR_GEN7_L3_CONTROL);
1450N/A I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
1450N/A GEN7_WA_L3_CHICKEN_MODE);
1450N/A
1450N/A /* This is required by WaCatErrorRejectionIssue */
1450N/A I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
1450N/A I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
1450N/A GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
1450N/A
1450N/A g4x_disable_trickle_feed(dev);
1450N/A
1450N/A
1450N/A gen7_setup_fixed_func_scheduler(dev_priv);
1450N/A
1450N/A /* WaDisable4x2SubspanOptimization */
1450N/A I915_WRITE(CACHE_MODE_1,
1450N/A _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1450N/A
1450N/A /* WaMbcDriverBootEnable */
1450N/A I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
1450N/A GEN6_MBCTL_ENABLE_BOOT_FETCH);
1450N/A
1450N/A /* WaSwitchSolVfFArbitrationPriority:hsw */
1450N/A I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
1450N/A
1450N/A /* WaRsPkgCStateDisplayPMReq:hsw */
1450N/A I915_WRITE(CHICKEN_PAR1_1,
1450N/A I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1450N/A
1450N/A lpt_init_clock_gating(dev);
1450N/A}
1450N/A
1450N/Astatic void ivybridge_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t snpcr;
1450N/A
1450N/A I915_WRITE(WM3_LP_ILK, 0);
1450N/A I915_WRITE(WM2_LP_ILK, 0);
1450N/A I915_WRITE(WM1_LP_ILK, 0);
1450N/A
1450N/A I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A /* WaDisableEarlyCull */
1450N/A I915_WRITE(_3D_CHICKEN3,
1450N/A _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
1450N/A
1450N/A /* WaDisableBackToBackFlipFix */
1450N/A I915_WRITE(IVB_CHICKEN3,
1450N/A CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
1450N/A CHICKEN3_DGMG_DONE_FIX_DISABLE);
1450N/A
1450N/A /* WaDisablePSDDualDispatchEnable */
1450N/A if (IS_IVB_GT1(dev))
1450N/A I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
1450N/A _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
1450N/A else
1450N/A I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
1450N/A _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
1450N/A
1450N/A /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
1450N/A I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
1450N/A GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
1450N/A
1450N/A /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
1450N/A I915_WRITE(GEN7_L3CNTLREG1,
1450N/A GEN7_WA_FOR_GEN7_L3_CONTROL);
1450N/A I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
1450N/A GEN7_WA_L3_CHICKEN_MODE);
1450N/A if (IS_IVB_GT1(dev))
1450N/A I915_WRITE(GEN7_ROW_CHICKEN2,
1450N/A _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
1450N/A else
1450N/A I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
1450N/A _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
1450N/A
1450N/A
1450N/A /* WaForceL3Serialization */
1450N/A I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
1450N/A ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
1450N/A
1450N/A /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
1450N/A * gating disable must be set. Failure to set it results in
1450N/A * flickering pixels due to Z write ordering failures after
1450N/A * some amount of runtime in the Mesa "fire" demo, and Unigine
1450N/A * Sanctuary and Tropics, and apparently anything else with
1450N/A * alpha test or pixel discard.
1450N/A *
1450N/A * According to the spec, bit 11 (RCCUNIT) must also be set,
1450N/A * but we didn't debug actual testcases to find it out.
1450N/A *
1450N/A * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
1450N/A * This implements the WaDisableRCZUnitClockGating workaround.
1450N/A */
1450N/A I915_WRITE(GEN6_UCGCTL2,
1450N/A GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A /* This is required by WaCatErrorRejectionIssue */
1450N/A I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
1450N/A I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
1450N/A GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
1450N/A
1450N/A g4x_disable_trickle_feed(dev);
1450N/A
1450N/A /* WaMbcDriverBootEnable */
1450N/A I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
1450N/A GEN6_MBCTL_ENABLE_BOOT_FETCH);
1450N/A
1450N/A /* WaVSRefCountFullforceMissDisable:ivb */
1450N/A gen7_setup_fixed_func_scheduler(dev_priv);
1450N/A
1450N/A /* WaDisable4x2SubspanOptimization */
1450N/A I915_WRITE(CACHE_MODE_1,
1450N/A _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1450N/A
1450N/A snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1450N/A snpcr &= ~GEN6_MBC_SNPCR_MASK;
1450N/A snpcr |= GEN6_MBC_SNPCR_MED;
1450N/A I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1450N/A
1450N/A if (!HAS_PCH_NOP(dev))
1450N/A cpt_init_clock_gating(dev);
1450N/A
1450N/A gen6_check_mch_setup(dev);
1450N/A}
1450N/A
1450N/Astatic void valleyview_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A /* WaDisableEarlyCull */
1450N/A I915_WRITE(_3D_CHICKEN3,
1450N/A _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
1450N/A
1450N/A /* WaDisableBackToBackFlipFix */
1450N/A I915_WRITE(IVB_CHICKEN3,
1450N/A CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
1450N/A CHICKEN3_DGMG_DONE_FIX_DISABLE);
1450N/A
1450N/A I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
1450N/A _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
1450N/A GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
1450N/A
1450N/A /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
1450N/A I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
1450N/A GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
1450N/A
1450N/A /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
1450N/A I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
1450N/A I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
1450N/A
1450N/A /* WaForceL3Serialization */
1450N/A I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
1450N/A ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
1450N/A
1450N/A /* WaDisableDopClockGating */
1450N/A I915_WRITE(GEN7_ROW_CHICKEN2,
1450N/A _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
1450N/A
1450N/A /* This is required by WaCatErrorRejectionIssue */
1450N/A I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
1450N/A I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
1450N/A GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
1450N/A
1450N/A /* WaMbcDriverBootEnable */
1450N/A I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
1450N/A GEN6_MBCTL_ENABLE_BOOT_FETCH);
1450N/A
1450N/A
1450N/A /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
1450N/A * gating disable must be set. Failure to set it results in
1450N/A * flickering pixels due to Z write ordering failures after
1450N/A * some amount of runtime in the Mesa "fire" demo, and Unigine
1450N/A * Sanctuary and Tropics, and apparently anything else with
1450N/A * alpha test or pixel discard.
1450N/A *
1450N/A * According to the spec, bit 11 (RCCUNIT) must also be set,
1450N/A * but we didn't debug actual testcases to find it out.
1450N/A *
1450N/A * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
1450N/A * This implements the WaDisableRCZUnitClockGating workaround.
1450N/A *
1450N/A * Also apply WaDisableVDSUnitClockGating and
1450N/A * WaDisableRCPBUnitClockGating.
1450N/A */
1450N/A I915_WRITE(GEN6_UCGCTL2,
1450N/A GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
1450N/A GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
1450N/A
1450N/A I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
1450N/A
1450N/A I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1450N/A
1450N/A I915_WRITE(CACHE_MODE_1,
1450N/A _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1450N/A
1450N/A /*
1450N/A * On ValleyView, the GUnit needs to signal the GT
1450N/A * when flip and other events complete. So enable
1450N/A * all the GUnit->GT interrupts here
1450N/A */
1450N/A I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
1450N/A
1450N/A /* Conservative clock gating settings for now */
1450N/A I915_WRITE(0x9400, 0xffffffff);
1450N/A I915_WRITE(0x9404, 0xffffffff);
1450N/A I915_WRITE(0x9408, 0xffffffff);
1450N/A I915_WRITE(0x940c, 0xffffffff);
1450N/A I915_WRITE(0x9410, 0xffffffff);
1450N/A I915_WRITE(0x9414, 0xffffffff);
1450N/A I915_WRITE(0x9418, 0xffffffff);
1450N/A}
1450N/A
1450N/Astatic void g4x_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t dspclk_gate;
1450N/A
1450N/A I915_WRITE(RENCLK_GATE_D1, 0);
1450N/A I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
1450N/A GS_UNIT_CLOCK_GATE_DISABLE |
1450N/A CL_UNIT_CLOCK_GATE_DISABLE);
1450N/A I915_WRITE(RAMCLK_GATE_D, 0);
1450N/A dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
1450N/A OVRUNIT_CLOCK_GATE_DISABLE |
1450N/A OVCUNIT_CLOCK_GATE_DISABLE;
1450N/A if (IS_GM45(dev))
1450N/A dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
1450N/A I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
1450N/A
1450N/A /* WaDisableRenderCachePipelinedFlush */
1450N/A I915_WRITE(CACHE_MODE_0,
1450N/A _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
1450N/A
1450N/A g4x_disable_trickle_feed(dev);
1450N/A}
1450N/A
1450N/Astatic void crestline_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
1450N/A I915_WRITE(RENCLK_GATE_D2, 0);
1450N/A I915_WRITE(DSPCLK_GATE_D, 0);
1450N/A I915_WRITE(RAMCLK_GATE_D, 0);
1450N/A I915_WRITE16(DEUC, 0);
1450N/A I915_WRITE(MI_ARB_STATE,
1450N/A _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
1450N/A}
1450N/A
1450N/Astatic void broadwater_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
1450N/A I965_RCC_CLOCK_GATE_DISABLE |
1450N/A I965_RCPB_CLOCK_GATE_DISABLE |
1450N/A I965_ISC_CLOCK_GATE_DISABLE |
1450N/A I965_FBC_CLOCK_GATE_DISABLE);
1450N/A I915_WRITE(RENCLK_GATE_D2, 0);
1450N/A I915_WRITE(MI_ARB_STATE,
1450N/A _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
1450N/A}
1450N/A
1450N/Astatic void gen3_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 dstate = I915_READ(D_STATE);
1450N/A
1450N/A dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
1450N/A DSTATE_DOT_CLOCK_GATING;
1450N/A I915_WRITE(D_STATE, dstate);
1450N/A
1450N/A if (IS_PINEVIEW(dev))
1450N/A I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
1450N/A
1450N/A /* IIR "flip pending" means done if this bit is set */
1450N/A I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
1450N/A}
1450N/A
1450N/Astatic void i85x_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
1450N/A}
1450N/A
1450N/Astatic void i830_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1450N/A}
1450N/A
1450N/Avoid intel_init_clock_gating(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A dev_priv->display.init_clock_gating(dev);
1450N/A}
1450N/A
1450N/Avoid intel_suspend_hw(struct drm_device *dev)
1450N/A{
1450N/A if (HAS_PCH_LPT(dev))
1450N/A lpt_suspend_hw(dev);
1450N/A}
1450N/A
1450N/A/**
1450N/A * We should only use the power well if we explicitly asked the hardware to
1450N/A * enable it, so check if it's enabled and also check if we've requested it to
1450N/A * be enabled.
1450N/A */
1450N/Abool intel_display_power_enabled(struct drm_device *dev,
1450N/A enum intel_display_power_domain domain)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (!HAS_POWER_WELL(dev))
1450N/A return true;
1450N/A
1450N/A switch (domain) {
1450N/A case POWER_DOMAIN_PIPE_A:
1450N/A case POWER_DOMAIN_TRANSCODER_EDP:
1450N/A return true;
1450N/A case POWER_DOMAIN_PIPE_B:
1450N/A case POWER_DOMAIN_PIPE_C:
1450N/A case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
1450N/A case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
1450N/A case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
1450N/A case POWER_DOMAIN_TRANSCODER_A:
1450N/A case POWER_DOMAIN_TRANSCODER_B:
1450N/A case POWER_DOMAIN_TRANSCODER_C:
1450N/A return I915_READ(HSW_PWR_WELL_DRIVER) ==
1450N/A (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
1450N/A default:
1450N/A BUG();
1450N/A return false;
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void __intel_set_power_well(struct drm_device *dev, bool enable)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A bool is_enabled, enable_requested;
1450N/A uint32_t tmp;
1450N/A
1450N/A tmp = I915_READ(HSW_PWR_WELL_DRIVER);
1450N/A is_enabled = tmp & HSW_PWR_WELL_STATE;
1450N/A enable_requested = tmp & HSW_PWR_WELL_ENABLE;
1450N/A
1450N/A if (enable) {
1450N/A if (!enable_requested)
1450N/A I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
1450N/A
1450N/A if (!is_enabled) {
1450N/A DRM_DEBUG_KMS("Enabling power well\n");
1450N/A if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
1450N/A HSW_PWR_WELL_STATE), 20))
1450N/A DRM_ERROR("Timeout enabling power well\n");
1450N/A }
1450N/A } else {
1450N/A if (enable_requested) {
1450N/A unsigned long irqflags;
1450N/A enum pipe p;
1450N/A
1450N/A I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
1450N/A POSTING_READ(HSW_PWR_WELL_DRIVER);
1450N/A
1450N/A DRM_DEBUG_KMS("Requesting to disable the power well\n");
1450N/A /*
1450N/A * After this, the registers on the pipes that are part
1450N/A * of the power well will become zero, so we have to
1450N/A * adjust our counters according to that.
1450N/A *
1450N/A * FIXME: Should we do this in general in
1450N/A * drm_vblank_post_modeset?
1450N/A */
1450N/A spin_lock_irqsave(&dev->vbl_lock, irqflags);
1450N/A for_each_pipe(p)
1450N/A if (p != PIPE_A)
1450N/A dev->last_vblank[p] = 0;
1450N/A spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
1450N/A }
1450N/A }
1450N/A}
1450N/A
1450N/Astatic struct i915_power_well *hsw_pwr;
1450N/A
1450N/A/* Display audio driver power well request */
1450N/Avoid i915_request_power_well(void)
1450N/A{
1450N/A if (!hsw_pwr)
1450N/A return;
1450N/A
1450N/A spin_lock_irq(&hsw_pwr->lock);
1450N/A if (!hsw_pwr->count++ &&
1450N/A !hsw_pwr->i915_request)
1450N/A __intel_set_power_well(hsw_pwr->device, true);
1450N/A spin_unlock_irq(&hsw_pwr->lock);
1450N/A}
1450N/A
1450N/A/* Display audio driver power well release */
1450N/Avoid i915_release_power_well(void)
1450N/A{
1450N/A if (!hsw_pwr)
1450N/A return;
1450N/A
1450N/A spin_lock_irq(&hsw_pwr->lock);
1450N/A WARN_ON(!hsw_pwr->count);
1450N/A if (!--hsw_pwr->count &&
1450N/A !hsw_pwr->i915_request)
1450N/A __intel_set_power_well(hsw_pwr->device, false);
1450N/A spin_unlock_irq(&hsw_pwr->lock);
1450N/A}
1450N/A
1450N/Aint i915_init_power_well(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A hsw_pwr = &dev_priv->power_well;
1450N/A
1450N/A hsw_pwr->device = dev;
1450N/A spin_lock_init(&hsw_pwr->lock);
1450N/A hsw_pwr->count = 0;
1450N/A
1450N/A return 0;
1450N/A}
1450N/A
1450N/Avoid i915_remove_power_well(struct drm_device *dev)
1450N/A{
1450N/A hsw_pwr = NULL;
1450N/A}
1450N/A
1450N/Avoid intel_set_power_well(struct drm_device *dev, bool enable)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct i915_power_well *power_well = &dev_priv->power_well;
1450N/A
1450N/A if (!HAS_POWER_WELL(dev))
1450N/A return;
1450N/A
1450N/A if (!i915_disable_power_well && !enable)
1450N/A return;
1450N/A
1450N/A spin_lock_irq(&power_well->lock);
1450N/A power_well->i915_request = enable;
1450N/A
1450N/A /* only reject "disable" power well request */
1450N/A if (power_well->count && !enable) {
1450N/A spin_unlock_irq(&power_well->lock);
1450N/A return;
1450N/A }
1450N/A
1450N/A __intel_set_power_well(dev, enable);
1450N/A spin_unlock_irq(&power_well->lock);
1450N/A}
1450N/A
1450N/A/*
1450N/A * Starting with Haswell, we have a "Power Down Well" that can be turned off
1450N/A * when not needed anymore. We have 4 registers that can request the power well
1450N/A * to be enabled, and it will only be disabled if none of the registers is
1450N/A * requesting it to be enabled.
1450N/A */
1450N/Avoid intel_init_power_well(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (!HAS_POWER_WELL(dev))
1450N/A return;
1450N/A
1450N/A /* For now, we need the power well to be always enabled. */
1450N/A intel_set_power_well(dev, true);
1450N/A
1450N/A /* We're taking over the BIOS, so clear any requests made by it since
1450N/A * the driver is in charge now. */
1450N/A if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
1450N/A I915_WRITE(HSW_PWR_WELL_BIOS, 0);
1450N/A}
1450N/A
1450N/A/* Set up chip specific power management-related functions */
1450N/Avoid intel_init_pm(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (I915_HAS_FBC(dev)) {
1450N/A if (HAS_PCH_SPLIT(dev)) {
1450N/A dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
1450N/A if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1450N/A dev_priv->display.enable_fbc =
1450N/A gen7_enable_fbc;
1450N/A else
1450N/A dev_priv->display.enable_fbc =
1450N/A ironlake_enable_fbc;
1450N/A dev_priv->display.disable_fbc = ironlake_disable_fbc;
1450N/A } else if (IS_GM45(dev)) {
1450N/A dev_priv->display.fbc_enabled = g4x_fbc_enabled;
1450N/A dev_priv->display.enable_fbc = g4x_enable_fbc;
1450N/A dev_priv->display.disable_fbc = g4x_disable_fbc;
1450N/A } else if (IS_CRESTLINE(dev)) {
1450N/A dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
1450N/A dev_priv->display.enable_fbc = i8xx_enable_fbc;
1450N/A dev_priv->display.disable_fbc = i8xx_disable_fbc;
1450N/A }
1450N/A /* 855GM needs testing */
1450N/A }
1450N/A
1450N/A /* For cxsr */
1450N/A if (IS_PINEVIEW(dev))
1450N/A i915_pineview_get_mem_freq(dev);
1450N/A else if (IS_GEN5(dev))
1450N/A i915_ironlake_get_mem_freq(dev);
1450N/A
1450N/A /* For FIFO watermark updates */
1450N/A if (HAS_PCH_SPLIT(dev)) {
1450N/A if (IS_GEN5(dev)) {
1450N/A if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
1450N/A dev_priv->display.update_wm = ironlake_update_wm;
1450N/A else {
1450N/A DRM_DEBUG_KMS("Failed to get proper latency. "
1450N/A "Disable CxSR\n");
1450N/A dev_priv->display.update_wm = NULL;
1450N/A }
1450N/A dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1450N/A } else if (IS_GEN6(dev)) {
1450N/A if (SNB_READ_WM0_LATENCY()) {
1450N/A dev_priv->display.update_wm = sandybridge_update_wm;
1450N/A dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1450N/A } else {
1450N/A DRM_DEBUG_KMS("Failed to read display plane latency. "
1450N/A "Disable CxSR\n");
1450N/A dev_priv->display.update_wm = NULL;
1450N/A }
1450N/A dev_priv->display.init_clock_gating = gen6_init_clock_gating;
1450N/A } else if (IS_IVYBRIDGE(dev)) {
1450N/A /* FIXME: detect B0+ stepping and use auto training */
1450N/A if (SNB_READ_WM0_LATENCY()) {
1450N/A dev_priv->display.update_wm = ivybridge_update_wm;
1450N/A dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1450N/A } else {
1450N/A DRM_DEBUG_KMS("Failed to read display plane latency. "
1450N/A "Disable CxSR\n");
1450N/A dev_priv->display.update_wm = NULL;
1450N/A }
1450N/A dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
1450N/A } else if (IS_HASWELL(dev)) {
1450N/A if (I915_READ64(MCH_SSKPD)) {
1450N/A dev_priv->display.update_wm = haswell_update_wm;
1450N/A dev_priv->display.update_sprite_wm =
1450N/A haswell_update_sprite_wm;
1450N/A } else {
1450N/A DRM_DEBUG_KMS("Failed to read display plane latency. "
1450N/A "Disable CxSR\n");
1450N/A dev_priv->display.update_wm = NULL;
1450N/A }
1450N/A dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1450N/A } else
1450N/A dev_priv->display.update_wm = NULL;
1450N/A } else if (IS_VALLEYVIEW(dev)) {
1450N/A dev_priv->display.update_wm = valleyview_update_wm;
1450N/A dev_priv->display.init_clock_gating =
1450N/A valleyview_init_clock_gating;
1450N/A } else if (IS_PINEVIEW(dev)) {
1450N/A if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
1450N/A dev_priv->is_ddr3,
1450N/A dev_priv->fsb_freq,
1450N/A dev_priv->mem_freq)) {
1450N/A DRM_INFO("failed to find known CxSR latency "
1450N/A "(found ddr%s fsb freq %d, mem freq %d), "
1450N/A "disabling CxSR\n",
1450N/A (dev_priv->is_ddr3 == 1) ? "3" : "2",
1450N/A dev_priv->fsb_freq, dev_priv->mem_freq);
1450N/A /* Disable CxSR and never update its watermark again */
1450N/A pineview_disable_cxsr(dev);
1450N/A dev_priv->display.update_wm = NULL;
1450N/A } else
1450N/A dev_priv->display.update_wm = pineview_update_wm;
1450N/A dev_priv->display.init_clock_gating = gen3_init_clock_gating;
1450N/A } else if (IS_G4X(dev)) {
1450N/A dev_priv->display.update_wm = g4x_update_wm;
1450N/A dev_priv->display.init_clock_gating = g4x_init_clock_gating;
1450N/A } else if (IS_GEN4(dev)) {
1450N/A dev_priv->display.update_wm = i965_update_wm;
1450N/A if (IS_CRESTLINE(dev))
1450N/A dev_priv->display.init_clock_gating = crestline_init_clock_gating;
1450N/A else if (IS_BROADWATER(dev))
1450N/A dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
1450N/A } else if (IS_GEN3(dev)) {
1450N/A dev_priv->display.update_wm = i9xx_update_wm;
1450N/A dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
1450N/A dev_priv->display.init_clock_gating = gen3_init_clock_gating;
1450N/A } else if (IS_I865G(dev)) {
1450N/A dev_priv->display.update_wm = i830_update_wm;
1450N/A dev_priv->display.init_clock_gating = i85x_init_clock_gating;
1450N/A dev_priv->display.get_fifo_size = i830_get_fifo_size;
1450N/A } else if (IS_I85X(dev)) {
1450N/A dev_priv->display.update_wm = i9xx_update_wm;
1450N/A dev_priv->display.get_fifo_size = i85x_get_fifo_size;
1450N/A dev_priv->display.init_clock_gating = i85x_init_clock_gating;
1450N/A } else {
1450N/A dev_priv->display.update_wm = i830_update_wm;
1450N/A dev_priv->display.init_clock_gating = i830_init_clock_gating;
1450N/A if (IS_845G(dev))
1450N/A dev_priv->display.get_fifo_size = i845_get_fifo_size;
1450N/A else
1450N/A dev_priv->display.get_fifo_size = i830_get_fifo_size;
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A u32 gt_thread_status_mask;
1450N/A
1450N/A if (IS_HASWELL(dev_priv->dev))
1450N/A gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
1450N/A else
1450N/A gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
1450N/A
1450N/A /* w/a for a sporadic read returning 0 by waiting for the GT
1450N/A * thread to wake up.
1450N/A */
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 1))
1450N/A DRM_INFO("GT thread status wait timed out\n");
1450N/A}
1450N/A
1450N/Astatic void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A I915_WRITE_NOTRACE(FORCEWAKE, 0);
1450N/A POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
1450N/A}
1450N/A
1450N/Astatic void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
1450N/A FORCEWAKE_ACK_TIMEOUT_MS))
1450N/A DRM_INFO("Timed out waiting for forcewake old ack to clear.\n");
1450N/A
1450N/A I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
1450N/A POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
1450N/A
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
1450N/A FORCEWAKE_ACK_TIMEOUT_MS))
1450N/A DRM_INFO("Timed out waiting for forcewake to ack request.\n");
1450N/A
1450N/A __gen6_gt_wait_for_thread_c0(dev_priv);
1450N/A}
1450N/A
1450N/Astatic void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffffUL));
1450N/A POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
1450N/A}
1450N/A
1450N/Astatic void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A u32 forcewake_ack;
1450N/A
1450N/A if (IS_HASWELL(dev_priv->dev))
1450N/A forcewake_ack = FORCEWAKE_ACK_HSW;
1450N/A else
1450N/A forcewake_ack = FORCEWAKE_MT_ACK;
1450N/A
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
1450N/A FORCEWAKE_ACK_TIMEOUT_MS))
1450N/A DRM_INFO("Timed out waiting for forcewake old ack to clear.\n");
1450N/A
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
1450N/A /* something from same cacheline, but !FORCEWAKE_MT */
1450N/A POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
1450N/A
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
1450N/A FORCEWAKE_ACK_TIMEOUT_MS))
1450N/A DRM_INFO("Timed out waiting for forcewake to ack request.\n");
1450N/A
1450N/A __gen6_gt_wait_for_thread_c0(dev_priv);
1450N/A}
1450N/A
1450N/A/*
1450N/A * Generally this is called implicitly by the register read function. However,
1450N/A * if some sequence requires the GT to not power down then this function should
1450N/A * be called at the beginning of the sequence followed by a call to
1450N/A * gen6_gt_force_wake_put() at the end of the sequence.
1450N/A */
1450N/Avoid gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A unsigned long irqflags;
1450N/A
1450N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
1450N/A if (dev_priv->forcewake_count++ == 0)
1450N/A dev_priv->gt.force_wake_get(dev_priv);
1450N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
1450N/A}
1450N/A
1450N/Avoid gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A u32 gtfifodbg;
1450N/A gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
1450N/A if (gtfifodbg & GT_FIFO_CPU_ERROR_MASK) {
1450N/A DRM_ERROR("MMIO read or write has been dropped %x\n", gtfifodbg);
1450N/A I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A I915_WRITE_NOTRACE(FORCEWAKE, 0);
1450N/A /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
1450N/A POSTING_READ(ECOBUS);
1450N/A gen6_gt_check_fifodbg(dev_priv);
1450N/A}
1450N/A
1450N/Astatic void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
1450N/A /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
1450N/A POSTING_READ(ECOBUS);
1450N/A gen6_gt_check_fifodbg(dev_priv);
1450N/A}
1450N/A
1450N/A/*
1450N/A * see gen6_gt_force_wake_get()
1450N/A */
1450N/Avoid gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A unsigned long irqflags;
1450N/A
1450N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
1450N/A if (--dev_priv->forcewake_count == 0)
1450N/A dev_priv->gt.force_wake_put(dev_priv);
1450N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
1450N/A}
1450N/A
1450N/Aint __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A int ret = 0;
1450N/A
1450N/A if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
1450N/A int loop = 500;
1450N/A u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
1450N/A while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
1450N/A udelay(10);
1450N/A fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
1450N/A }
1450N/A if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
1450N/A ++ret;
1450N/A WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
1450N/A }
1450N/A dev_priv->gt_fifo_count = fifo;
1450N/A }
1450N/A dev_priv->gt_fifo_count--;
1450N/A
1450N/A return ret;
1450N/A}
1450N/A
1450N/Astatic void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffffUL));
1450N/A /* something from same cacheline, but !FORCEWAKE_VLV */
1450N/A POSTING_READ(FORCEWAKE_ACK_VLV);
1450N/A}
1450N/A
1450N/Astatic void vlv_force_wake_get(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
1450N/A FORCEWAKE_ACK_TIMEOUT_MS))
1450N/A DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
1450N/A
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
1450N/A _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
1450N/A
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
1450N/A FORCEWAKE_ACK_TIMEOUT_MS))
1450N/A DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
1450N/A
1450N/A if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
1450N/A FORCEWAKE_KERNEL),
1450N/A FORCEWAKE_ACK_TIMEOUT_MS))
1450N/A DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
1450N/A
1450N/A __gen6_gt_wait_for_thread_c0(dev_priv);
1450N/A}
1450N/A
1450N/Astatic void vlv_force_wake_put(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
1450N/A I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
1450N/A _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
1450N/A /* The below doubles as a POSTING_READ */
1450N/A POSTING_READ(FORCEWAKE_ACK_VLV);
1450N/A gen6_gt_check_fifodbg(dev_priv);
1450N/A}
1450N/A
1450N/Avoid intel_gt_sanitize(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (IS_VALLEYVIEW(dev)) {
1450N/A vlv_force_wake_reset(dev_priv);
1450N/A } else if (INTEL_INFO(dev)->gen >= 6) {
1450N/A __gen6_gt_force_wake_reset(dev_priv);
1450N/A if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1450N/A __gen6_gt_force_wake_mt_reset(dev_priv);
1450N/A }
1450N/A
1450N/A /* BIOS often leaves RC6 enabled, but disable it for hw init */
1450N/A if (INTEL_INFO(dev)->gen >= 6)
1450N/A intel_disable_gt_powersave(dev);
1450N/A}
1450N/A
1450N/Avoid intel_gt_init(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A if (IS_VALLEYVIEW(dev)) {
1450N/A dev_priv->gt.force_wake_get = vlv_force_wake_get;
1450N/A dev_priv->gt.force_wake_put = vlv_force_wake_put;
1450N/A } else if (IS_HASWELL(dev)) {
1450N/A dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
1450N/A dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
1450N/A } else if (IS_IVYBRIDGE(dev)) {
1450N/A u32 ecobus;
1450N/A
1450N/A /* IVB configs may use multi-threaded forcewake */
1450N/A
1450N/A /* A small trick here - if the bios hasn't configured
1450N/A * MT forcewake, and if the device is in RC6, then
1450N/A * force_wake_mt_get will not wake the device and the
1450N/A * ECOBUS read will return zero. Which will be
1450N/A * (correctly) interpreted by the test below as MT
1450N/A * forcewake being disabled.
1450N/A */
1450N/A mutex_lock(&dev->struct_mutex);
1450N/A __gen6_gt_force_wake_mt_get(dev_priv);
1450N/A ecobus = I915_READ_NOTRACE(ECOBUS);
1450N/A __gen6_gt_force_wake_mt_put(dev_priv);
1450N/A mutex_unlock(&dev->struct_mutex);
1450N/A
1450N/A if (ecobus & FORCEWAKE_MT_ENABLE) {
1450N/A dev_priv->gt.force_wake_get =
1450N/A __gen6_gt_force_wake_mt_get;
1450N/A dev_priv->gt.force_wake_put =
1450N/A __gen6_gt_force_wake_mt_put;
1450N/A } else {
1450N/A DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1450N/A DRM_INFO("when using vblank-synced partial screen updates.\n");
1450N/A dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
1450N/A dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
1450N/A }
1450N/A } else if (IS_GEN6(dev)) {
1450N/A dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
1450N/A dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
1450N/A }
1450N/A}
1450N/A
1450N/Avoid intel_pm_init(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A INIT_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work);
1450N/A setup_timer(&dev_priv->rps.delayed_resume_timer, intel_gen6_powersave_work_timer,
1450N/A (void *)dev);
1450N/A}
1450N/A
1450N/Aint sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
1450N/A{
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A
1450N/A if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
1450N/A DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
1450N/A return -EAGAIN;
1450N/A }
1450N/A
1450N/A I915_WRITE(GEN6_PCODE_DATA, *val);
1450N/A I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
1450N/A
1450N/A if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
1450N/A 500)) {
1450N/A DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
1450N/A return -ETIMEDOUT;
1450N/A }
1450N/A
1450N/A *val = I915_READ(GEN6_PCODE_DATA);
1450N/A I915_WRITE(GEN6_PCODE_DATA, 0);
1450N/A
1450N/A return 0;
1450N/A}
1450N/A
1450N/Aint sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
1450N/A{
1450N/A WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1450N/A
1450N/A if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
1450N/A DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
1450N/A return -EAGAIN;
1450N/A }
1450N/A
1450N/A I915_WRITE(GEN6_PCODE_DATA, val);
1450N/A I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
1450N/A
1450N/A if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
1450N/A 500)) {
1450N/A DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
1450N/A return -ETIMEDOUT;
1450N/A }
1450N/A
1450N/A I915_WRITE(GEN6_PCODE_DATA, 0);
1450N/A
1450N/A return 0;
1450N/A}
1450N/A
1450N/Aint vlv_gpu_freq(int ddr_freq, int val)
1450N/A{
1450N/A int mult, base;
1450N/A
1450N/A switch (ddr_freq) {
1450N/A case 800:
1450N/A mult = 20;
1450N/A base = 120;
1450N/A break;
1450N/A case 1066:
1450N/A mult = 22;
1450N/A base = 133;
1450N/A break;
1450N/A case 1333:
1450N/A mult = 21;
1450N/A base = 125;
1450N/A break;
1450N/A default:
1450N/A return -1;
1450N/A }
1450N/A
1450N/A return ((val - 0xbd) * mult) + base;
1450N/A}
1450N/A
1450N/Aint vlv_freq_opcode(int ddr_freq, int val)
1450N/A{
1450N/A int mult, base;
1450N/A
1450N/A switch (ddr_freq) {
1450N/A case 800:
1450N/A mult = 20;
1450N/A base = 120;
1450N/A break;
1450N/A case 1066:
1450N/A mult = 22;
1450N/A base = 133;
1450N/A break;
1450N/A case 1333:
1450N/A mult = 21;
1450N/A base = 125;
1450N/A break;
1450N/A default:
1450N/A return -1;
1450N/A }
1450N/A
1450N/A val /= mult;
1450N/A val -= base / mult;
1450N/A val += 0xbd;
1450N/A
1450N/A if (val > 0xea)
1450N/A val = 0xea;
1450N/A
1450N/A return val;
1450N/A}
1450N/A