1450N/A/*
1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A/*
1450N/A * Copyright (c) 2006-2013 Intel Corporation
1450N/A * Jesse Barnes <jesse.barnes@intel.com>
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice (including the next
1450N/A * paragraph) shall be included in all copies or substantial portions of the
1450N/A * Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
1450N/A * DEALINGS IN THE SOFTWARE.
1450N/A *
1450N/A * Authors:
1450N/A * Eric Anholt <eric@anholt.net>
1450N/A *
1450N/A */
1450N/A
1450N/A/** @file
1450N/A * Integrated TV-out support for the 915GM and 945GM.
1450N/A */
1450N/A
1450N/A#include <sys/ddi.h>
1450N/A#include "drmP.h"
1450N/A#include "drm.h"
1450N/A#include "drm_crtc.h"
1450N/A#include "drm_edid.h"
1450N/A#include "intel_drv.h"
1450N/A#include "i915_drm.h"
1450N/A#include "i915_drv.h"
1450N/A
1450N/Aenum tv_margin {
1450N/A TV_MARGIN_LEFT, TV_MARGIN_TOP,
1450N/A TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
1450N/A};
1450N/A
1450N/A/** Private structure for the integrated TV support */
1450N/Astruct intel_tv {
1450N/A struct intel_encoder base;
1450N/A
1450N/A int type;
1450N/A const char *tv_format;
1450N/A int margin[4];
1450N/A u32 save_TV_H_CTL_1;
1450N/A u32 save_TV_H_CTL_2;
1450N/A u32 save_TV_H_CTL_3;
1450N/A u32 save_TV_V_CTL_1;
1450N/A u32 save_TV_V_CTL_2;
1450N/A u32 save_TV_V_CTL_3;
1450N/A u32 save_TV_V_CTL_4;
1450N/A u32 save_TV_V_CTL_5;
1450N/A u32 save_TV_V_CTL_6;
1450N/A u32 save_TV_V_CTL_7;
1450N/A u32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3;
1450N/A
1450N/A u32 save_TV_CSC_Y;
1450N/A u32 save_TV_CSC_Y2;
1450N/A u32 save_TV_CSC_U;
1450N/A u32 save_TV_CSC_U2;
1450N/A u32 save_TV_CSC_V;
1450N/A u32 save_TV_CSC_V2;
1450N/A u32 save_TV_CLR_KNOBS;
1450N/A u32 save_TV_CLR_LEVEL;
1450N/A u32 save_TV_WIN_POS;
1450N/A u32 save_TV_WIN_SIZE;
1450N/A u32 save_TV_FILTER_CTL_1;
1450N/A u32 save_TV_FILTER_CTL_2;
1450N/A u32 save_TV_FILTER_CTL_3;
1450N/A
1450N/A u32 save_TV_H_LUMA[60];
1450N/A u32 save_TV_H_CHROMA[60];
1450N/A u32 save_TV_V_LUMA[43];
1450N/A u32 save_TV_V_CHROMA[43];
1450N/A
1450N/A u32 save_TV_DAC;
1450N/A u32 save_TV_CTL;
1450N/A};
1450N/A
1450N/Astruct video_levels {
1450N/A int blank, black, burst;
1450N/A};
1450N/A
1450N/Astruct color_conversion {
1450N/A u16 ry, gy, by, ay;
1450N/A u16 ru, gu, bu, au;
1450N/A u16 rv, gv, bv, av;
1450N/A};
1450N/A
1450N/Astatic const u32 filter_table[] = {
1450N/A 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
1450N/A 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
1450N/A 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
1450N/A 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
1450N/A 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
1450N/A 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
1450N/A 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
1450N/A 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
1450N/A 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
1450N/A 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
1450N/A 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
1450N/A 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
1450N/A 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
1450N/A 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
1450N/A 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
1450N/A 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
1450N/A 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
1450N/A 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
1450N/A 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
1450N/A 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
1450N/A 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
1450N/A 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
1450N/A 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
1450N/A 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
1450N/A 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
1450N/A 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
1450N/A 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
1450N/A 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
1450N/A 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
1450N/A 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
1450N/A 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
1450N/A 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
1450N/A 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
1450N/A 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
1450N/A 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
1450N/A 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
1450N/A 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
1450N/A 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
1450N/A 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
1450N/A 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
1450N/A 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
1450N/A 0x2D002CC0, 0x30003640, 0x2D0036C0,
1450N/A 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
1450N/A 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
1450N/A 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
1450N/A 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
1450N/A 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
1450N/A 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
1450N/A 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
1450N/A 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
1450N/A 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
1450N/A 0x28003100, 0x28002F00, 0x00003100,
1450N/A};
1450N/A
1450N/A/*
1450N/A * Color conversion values have 3 separate fixed point formats:
1450N/A *
1450N/A * 10 bit fields (ay, au)
1450N/A * 1.9 fixed point (b.bbbbbbbbb)
1450N/A * 11 bit fields (ry, by, ru, gu, gv)
1450N/A * exp.mantissa (ee.mmmmmmmmm)
1450N/A * ee = 00 = 10^-1 (0.mmmmmmmmm)
1450N/A * ee = 01 = 10^-2 (0.0mmmmmmmmm)
1450N/A * ee = 10 = 10^-3 (0.00mmmmmmmmm)
1450N/A * ee = 11 = 10^-4 (0.000mmmmmmmmm)
1450N/A * 12 bit fields (gy, rv, bu)
1450N/A * exp.mantissa (eee.mmmmmmmmm)
1450N/A * eee = 000 = 10^-1 (0.mmmmmmmmm)
1450N/A * eee = 001 = 10^-2 (0.0mmmmmmmmm)
1450N/A * eee = 010 = 10^-3 (0.00mmmmmmmmm)
1450N/A * eee = 011 = 10^-4 (0.000mmmmmmmmm)
1450N/A * eee = 100 = reserved
1450N/A * eee = 101 = reserved
1450N/A * eee = 110 = reserved
1450N/A * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
1450N/A *
1450N/A * Saturation and contrast are 8 bits, with their own representation:
1450N/A * 8 bit field (saturation, contrast)
1450N/A * exp.mantissa (ee.mmmmmm)
1450N/A * ee = 00 = 10^-1 (0.mmmmmm)
1450N/A * ee = 01 = 10^0 (m.mmmmm)
1450N/A * ee = 10 = 10^1 (mm.mmmm)
1450N/A * ee = 11 = 10^2 (mmm.mmm)
1450N/A *
1450N/A * Simple conversion function:
1450N/A *
1450N/A * static u32
1450N/A * float_to_csc_11(float f)
1450N/A * {
1450N/A * u32 exp;
1450N/A * u32 mant;
1450N/A * u32 ret;
1450N/A *
1450N/A * if (f < 0)
1450N/A * f = -f;
1450N/A *
1450N/A * if (f >= 1) {
1450N/A * exp = 0x7;
1450N/A * mant = 1 << 8;
1450N/A * } else {
1450N/A * for (exp = 0; exp < 3 && f < 0.5; exp++)
1450N/A * f *= 2.0;
1450N/A * mant = (f * (1 << 9) + 0.5);
1450N/A * if (mant >= (1 << 9))
1450N/A * mant = (1 << 9) - 1;
1450N/A * }
1450N/A * ret = (exp << 9) | mant;
1450N/A * return ret;
1450N/A * }
1450N/A */
1450N/A
1450N/A/*
1450N/A * Behold, magic numbers! If we plant them they might grow a big
1450N/A * s-video cable to the sky... or something.
1450N/A *
1450N/A * Pre-converted to appropriate hex value.
1450N/A */
1450N/A
1450N/A/*
1450N/A * PAL & NTSC values for composite & s-video connections
1450N/A */
1450N/Astatic const struct color_conversion ntsc_m_csc_composite = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
1450N/A .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
1450N/A .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels ntsc_m_levels_composite = {
1450N/A .blank = 225, .black = 267, .burst = 113,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion ntsc_m_csc_svideo = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
1450N/A .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
1450N/A .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels ntsc_m_levels_svideo = {
1450N/A .blank = 266, .black = 316, .burst = 133,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion ntsc_j_csc_composite = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
1450N/A .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
1450N/A .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels ntsc_j_levels_composite = {
1450N/A .blank = 225, .black = 225, .burst = 113,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion ntsc_j_csc_svideo = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
1450N/A .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
1450N/A .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels ntsc_j_levels_svideo = {
1450N/A .blank = 266, .black = 266, .burst = 133,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion pal_csc_composite = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
1450N/A .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
1450N/A .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels pal_levels_composite = {
1450N/A .blank = 237, .black = 237, .burst = 118,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion pal_csc_svideo = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
1450N/A .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
1450N/A .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels pal_levels_svideo = {
1450N/A .blank = 280, .black = 280, .burst = 139,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion pal_m_csc_composite = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
1450N/A .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
1450N/A .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels pal_m_levels_composite = {
1450N/A .blank = 225, .black = 267, .burst = 113,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion pal_m_csc_svideo = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
1450N/A .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
1450N/A .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels pal_m_levels_svideo = {
1450N/A .blank = 266, .black = 316, .burst = 133,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion pal_n_csc_composite = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
1450N/A .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
1450N/A .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels pal_n_levels_composite = {
1450N/A .blank = 225, .black = 267, .burst = 118,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion pal_n_csc_svideo = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
1450N/A .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
1450N/A .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels pal_n_levels_svideo = {
1450N/A .blank = 266, .black = 316, .burst = 139,
1450N/A};
1450N/A
1450N/A/*
1450N/A * Component connections
1450N/A */
1450N/Astatic const struct color_conversion sdtv_csc_yprpb = {
1450N/A .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
1450N/A .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
1450N/A .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion sdtv_csc_rgb = {
1450N/A .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
1450N/A .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
1450N/A .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion hdtv_csc_yprpb = {
1450N/A .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
1450N/A .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
1450N/A .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
1450N/A};
1450N/A
1450N/Astatic const struct color_conversion hdtv_csc_rgb = {
1450N/A .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
1450N/A .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
1450N/A .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
1450N/A};
1450N/A
1450N/Astatic const struct video_levels component_levels = {
1450N/A .blank = 279, .black = 279, .burst = 0,
1450N/A};
1450N/A
1450N/A
1450N/Astruct tv_mode {
1450N/A const char *name;
1450N/A int clock;
1450N/A int refresh; /* in millihertz (for precision) */
1450N/A u32 oversample;
1450N/A int hsync_end, hblank_start, hblank_end, htotal;
1450N/A bool progressive, trilevel_sync, component_only;
1450N/A int vsync_start_f1, vsync_start_f2, vsync_len;
1450N/A bool veq_ena;
1450N/A int veq_start_f1, veq_start_f2, veq_len;
1450N/A int vi_end_f1, vi_end_f2, nbr_end;
1450N/A bool burst_ena;
1450N/A int hburst_start, hburst_len;
1450N/A int vburst_start_f1, vburst_end_f1;
1450N/A int vburst_start_f2, vburst_end_f2;
1450N/A int vburst_start_f3, vburst_end_f3;
1450N/A int vburst_start_f4, vburst_end_f4;
1450N/A /*
1450N/A * subcarrier programming
1450N/A */
1450N/A int dda2_size, dda3_size, dda1_inc, dda2_inc, dda3_inc;
1450N/A u32 sc_reset;
1450N/A bool pal_burst;
1450N/A /*
1450N/A * blank/black levels
1450N/A */
1450N/A const struct video_levels *composite_levels, *svideo_levels;
1450N/A const struct color_conversion *composite_color, *svideo_color;
1450N/A const u32 *filter_table;
1450N/A int max_srcw;
1450N/A};
1450N/A
1450N/A
1450N/A/*
1450N/A * Sub carrier DDA
1450N/A *
1450N/A * I think this works as follows:
1450N/A *
1450N/A * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
1450N/A *
1450N/A * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
1450N/A *
1450N/A * So,
1450N/A * dda1_ideal = subcarrier/pixel * 4096
1450N/A * dda1_inc = floor (dda1_ideal)
1450N/A * dda2 = dda1_ideal - dda1_inc
1450N/A *
1450N/A * then pick a ratio for dda2 that gives the closest approximation. If
1450N/A * you can't get close enough, you can play with dda3 as well. This
1450N/A * seems likely to happen when dda2 is small as the jumps would be larger
1450N/A *
1450N/A * To invert this,
1450N/A *
1450N/A * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
1450N/A *
1450N/A * The constants below were all computed using a 107.520MHz clock
1450N/A */
1450N/A
1450N/A/**
1450N/A * Register programming values for TV modes.
1450N/A *
1450N/A * These values account for -1s required.
1450N/A */
1450N/A
1450N/Astatic const struct tv_mode tv_modes[] = {
1450N/A {
1450N/A .name = "NTSC-M",
1450N/A .clock = 108000,
1450N/A .refresh = 59940,
1450N/A .oversample = TV_OVERSAMPLE_8X,
1450N/A .component_only = 0,
1450N/A /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
1450N/A
1450N/A .hsync_end = 64, .hblank_end = 124,
1450N/A .hblank_start = 836, .htotal = 857,
1450N/A
1450N/A .progressive = false, .trilevel_sync = false,
1450N/A
1450N/A .vsync_start_f1 = 6, .vsync_start_f2 = 7,
1450N/A .vsync_len = 6,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 0,
1450N/A .veq_start_f2 = 1, .veq_len = 18,
1450N/A
1450N/A .vi_end_f1 = 20, .vi_end_f2 = 21,
1450N/A .nbr_end = 240,
1450N/A
1450N/A .burst_ena = true,
1450N/A .hburst_start = 72, .hburst_len = 34,
1450N/A .vburst_start_f1 = 9, .vburst_end_f1 = 240,
1450N/A .vburst_start_f2 = 10, .vburst_end_f2 = 240,
1450N/A .vburst_start_f3 = 9, .vburst_end_f3 = 240,
1450N/A .vburst_start_f4 = 10, .vburst_end_f4 = 240,
1450N/A
1450N/A /* desired 3.5800000 actual 3.5800000 clock 107.52 */
1450N/A .dda1_inc = 135,
1450N/A .dda2_inc = 20800, .dda2_size = 27456,
1450N/A .dda3_inc = 0, .dda3_size = 0,
1450N/A .sc_reset = TV_SC_RESET_EVERY_4,
1450N/A .pal_burst = false,
1450N/A
1450N/A .composite_levels = &ntsc_m_levels_composite,
1450N/A .composite_color = &ntsc_m_csc_composite,
1450N/A .svideo_levels = &ntsc_m_levels_svideo,
1450N/A .svideo_color = &ntsc_m_csc_svideo,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "NTSC-443",
1450N/A .clock = 108000,
1450N/A .refresh = 59940,
1450N/A .oversample = TV_OVERSAMPLE_8X,
1450N/A .component_only = 0,
1450N/A /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
1450N/A .hsync_end = 64, .hblank_end = 124,
1450N/A .hblank_start = 836, .htotal = 857,
1450N/A
1450N/A .progressive = false, .trilevel_sync = false,
1450N/A
1450N/A .vsync_start_f1 = 6, .vsync_start_f2 = 7,
1450N/A .vsync_len = 6,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 0,
1450N/A .veq_start_f2 = 1, .veq_len = 18,
1450N/A
1450N/A .vi_end_f1 = 20, .vi_end_f2 = 21,
1450N/A .nbr_end = 240,
1450N/A
1450N/A .burst_ena = true,
1450N/A .hburst_start = 72, .hburst_len = 34,
1450N/A .vburst_start_f1 = 9, .vburst_end_f1 = 240,
1450N/A .vburst_start_f2 = 10, .vburst_end_f2 = 240,
1450N/A .vburst_start_f3 = 9, .vburst_end_f3 = 240,
1450N/A .vburst_start_f4 = 10, .vburst_end_f4 = 240,
1450N/A
1450N/A /* desired 4.4336180 actual 4.4336180 clock 107.52 */
1450N/A .dda1_inc = 168,
1450N/A .dda2_inc = 4093, .dda2_size = 27456,
1450N/A .dda3_inc = 310, .dda3_size = 525,
1450N/A .sc_reset = TV_SC_RESET_NEVER,
1450N/A .pal_burst = false,
1450N/A
1450N/A .composite_levels = &ntsc_m_levels_composite,
1450N/A .composite_color = &ntsc_m_csc_composite,
1450N/A .svideo_levels = &ntsc_m_levels_svideo,
1450N/A .svideo_color = &ntsc_m_csc_svideo,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "NTSC-J",
1450N/A .clock = 108000,
1450N/A .refresh = 59940,
1450N/A .oversample = TV_OVERSAMPLE_8X,
1450N/A .component_only = 0,
1450N/A
1450N/A /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
1450N/A .hsync_end = 64, .hblank_end = 124,
1450N/A .hblank_start = 836, .htotal = 857,
1450N/A
1450N/A .progressive = false, .trilevel_sync = false,
1450N/A
1450N/A .vsync_start_f1 = 6, .vsync_start_f2 = 7,
1450N/A .vsync_len = 6,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 0,
1450N/A .veq_start_f2 = 1, .veq_len = 18,
1450N/A
1450N/A .vi_end_f1 = 20, .vi_end_f2 = 21,
1450N/A .nbr_end = 240,
1450N/A
1450N/A .burst_ena = true,
1450N/A .hburst_start = 72, .hburst_len = 34,
1450N/A .vburst_start_f1 = 9, .vburst_end_f1 = 240,
1450N/A .vburst_start_f2 = 10, .vburst_end_f2 = 240,
1450N/A .vburst_start_f3 = 9, .vburst_end_f3 = 240,
1450N/A .vburst_start_f4 = 10, .vburst_end_f4 = 240,
1450N/A
1450N/A /* desired 3.5800000 actual 3.5800000 clock 107.52 */
1450N/A .dda1_inc = 135,
1450N/A .dda2_inc = 20800, .dda2_size = 27456,
1450N/A .dda3_inc = 0, .dda3_size = 0,
1450N/A .sc_reset = TV_SC_RESET_EVERY_4,
1450N/A .pal_burst = false,
1450N/A
1450N/A .composite_levels = &ntsc_j_levels_composite,
1450N/A .composite_color = &ntsc_j_csc_composite,
1450N/A .svideo_levels = &ntsc_j_levels_svideo,
1450N/A .svideo_color = &ntsc_j_csc_svideo,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "PAL-M",
1450N/A .clock = 108000,
1450N/A .refresh = 59940,
1450N/A .oversample = TV_OVERSAMPLE_8X,
1450N/A .component_only = 0,
1450N/A
1450N/A /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
1450N/A .hsync_end = 64, .hblank_end = 124,
1450N/A .hblank_start = 836, .htotal = 857,
1450N/A
1450N/A .progressive = false, .trilevel_sync = false,
1450N/A
1450N/A .vsync_start_f1 = 6, .vsync_start_f2 = 7,
1450N/A .vsync_len = 6,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 0,
1450N/A .veq_start_f2 = 1, .veq_len = 18,
1450N/A
1450N/A .vi_end_f1 = 20, .vi_end_f2 = 21,
1450N/A .nbr_end = 240,
1450N/A
1450N/A .burst_ena = true,
1450N/A .hburst_start = 72, .hburst_len = 34,
1450N/A .vburst_start_f1 = 9, .vburst_end_f1 = 240,
1450N/A .vburst_start_f2 = 10, .vburst_end_f2 = 240,
1450N/A .vburst_start_f3 = 9, .vburst_end_f3 = 240,
1450N/A .vburst_start_f4 = 10, .vburst_end_f4 = 240,
1450N/A
1450N/A /* desired 3.5800000 actual 3.5800000 clock 107.52 */
1450N/A .dda1_inc = 135,
1450N/A .dda2_inc = 16704, .dda2_size = 27456,
1450N/A .dda3_inc = 0, .dda3_size = 0,
1450N/A .sc_reset = TV_SC_RESET_EVERY_8,
1450N/A .pal_burst = true,
1450N/A
1450N/A .composite_levels = &pal_m_levels_composite,
1450N/A .composite_color = &pal_m_csc_composite,
1450N/A .svideo_levels = &pal_m_levels_svideo,
1450N/A .svideo_color = &pal_m_csc_svideo,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
1450N/A .name = "PAL-N",
1450N/A .clock = 108000,
1450N/A .refresh = 50000,
1450N/A .oversample = TV_OVERSAMPLE_8X,
1450N/A .component_only = 0,
1450N/A
1450N/A .hsync_end = 64, .hblank_end = 128,
1450N/A .hblank_start = 844, .htotal = 863,
1450N/A
1450N/A .progressive = false, .trilevel_sync = false,
1450N/A
1450N/A
1450N/A .vsync_start_f1 = 6, .vsync_start_f2 = 7,
1450N/A .vsync_len = 6,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 0,
1450N/A .veq_start_f2 = 1, .veq_len = 18,
1450N/A
1450N/A .vi_end_f1 = 24, .vi_end_f2 = 25,
1450N/A .nbr_end = 286,
1450N/A
1450N/A .burst_ena = true,
1450N/A .hburst_start = 73, .hburst_len = 34,
1450N/A .vburst_start_f1 = 8, .vburst_end_f1 = 285,
1450N/A .vburst_start_f2 = 8, .vburst_end_f2 = 286,
1450N/A .vburst_start_f3 = 9, .vburst_end_f3 = 286,
1450N/A .vburst_start_f4 = 9, .vburst_end_f4 = 285,
1450N/A
1450N/A
1450N/A /* desired 4.4336180 actual 4.4336180 clock 107.52 */
1450N/A .dda1_inc = 135,
1450N/A .dda2_inc = 23578, .dda2_size = 27648,
1450N/A .dda3_inc = 134, .dda3_size = 625,
1450N/A .sc_reset = TV_SC_RESET_EVERY_8,
1450N/A .pal_burst = true,
1450N/A
1450N/A .composite_levels = &pal_n_levels_composite,
1450N/A .composite_color = &pal_n_csc_composite,
1450N/A .svideo_levels = &pal_n_levels_svideo,
1450N/A .svideo_color = &pal_n_csc_svideo,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
1450N/A .name = "PAL",
1450N/A .clock = 108000,
1450N/A .refresh = 50000,
1450N/A .oversample = TV_OVERSAMPLE_8X,
1450N/A .component_only = 0,
1450N/A
1450N/A .hsync_end = 64, .hblank_end = 142,
1450N/A .hblank_start = 844, .htotal = 863,
1450N/A
1450N/A .progressive = false, .trilevel_sync = false,
1450N/A
1450N/A .vsync_start_f1 = 5, .vsync_start_f2 = 6,
1450N/A .vsync_len = 5,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 0,
1450N/A .veq_start_f2 = 1, .veq_len = 15,
1450N/A
1450N/A .vi_end_f1 = 24, .vi_end_f2 = 25,
1450N/A .nbr_end = 286,
1450N/A
1450N/A .burst_ena = true,
1450N/A .hburst_start = 73, .hburst_len = 32,
1450N/A .vburst_start_f1 = 8, .vburst_end_f1 = 285,
1450N/A .vburst_start_f2 = 8, .vburst_end_f2 = 286,
1450N/A .vburst_start_f3 = 9, .vburst_end_f3 = 286,
1450N/A .vburst_start_f4 = 9, .vburst_end_f4 = 285,
1450N/A
1450N/A /* desired 4.4336180 actual 4.4336180 clock 107.52 */
1450N/A .dda1_inc = 168,
1450N/A .dda2_inc = 4122, .dda2_size = 27648,
1450N/A .dda3_inc = 67, .dda3_size = 625,
1450N/A .sc_reset = TV_SC_RESET_EVERY_8,
1450N/A .pal_burst = true,
1450N/A
1450N/A .composite_levels = &pal_levels_composite,
1450N/A .composite_color = &pal_csc_composite,
1450N/A .svideo_levels = &pal_levels_svideo,
1450N/A .svideo_color = &pal_csc_svideo,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "480p",
1450N/A .clock = 107520,
1450N/A .refresh = 59940,
1450N/A .oversample = TV_OVERSAMPLE_4X,
1450N/A .component_only = 1,
1450N/A
1450N/A .hsync_end = 64, .hblank_end = 122,
1450N/A .hblank_start = 842, .htotal = 857,
1450N/A
1450N/A .progressive = true, .trilevel_sync = false,
1450N/A
1450N/A .vsync_start_f1 = 12, .vsync_start_f2 = 12,
1450N/A .vsync_len = 12,
1450N/A
1450N/A .veq_ena = false,
1450N/A
1450N/A .vi_end_f1 = 44, .vi_end_f2 = 44,
1450N/A .nbr_end = 479,
1450N/A
1450N/A .burst_ena = false,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "576p",
1450N/A .clock = 107520,
1450N/A .refresh = 50000,
1450N/A .oversample = TV_OVERSAMPLE_4X,
1450N/A .component_only = 1,
1450N/A
1450N/A .hsync_end = 64, .hblank_end = 139,
1450N/A .hblank_start = 859, .htotal = 863,
1450N/A
1450N/A .progressive = true, .trilevel_sync = false,
1450N/A
1450N/A .vsync_start_f1 = 10, .vsync_start_f2 = 10,
1450N/A .vsync_len = 10,
1450N/A
1450N/A .veq_ena = false,
1450N/A
1450N/A .vi_end_f1 = 48, .vi_end_f2 = 48,
1450N/A .nbr_end = 575,
1450N/A
1450N/A .burst_ena = false,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "720p@60Hz",
1450N/A .clock = 148800,
1450N/A .refresh = 60000,
1450N/A .oversample = TV_OVERSAMPLE_2X,
1450N/A .component_only = 1,
1450N/A
1450N/A .hsync_end = 80, .hblank_end = 300,
1450N/A .hblank_start = 1580, .htotal = 1649,
1450N/A
1450N/A .progressive = true, .trilevel_sync = true,
1450N/A
1450N/A .vsync_start_f1 = 10, .vsync_start_f2 = 10,
1450N/A .vsync_len = 10,
1450N/A
1450N/A .veq_ena = false,
1450N/A
1450N/A .vi_end_f1 = 29, .vi_end_f2 = 29,
1450N/A .nbr_end = 719,
1450N/A
1450N/A .burst_ena = false,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "720p@50Hz",
1450N/A .clock = 148800,
1450N/A .refresh = 50000,
1450N/A .oversample = TV_OVERSAMPLE_2X,
1450N/A .component_only = 1,
1450N/A
1450N/A .hsync_end = 80, .hblank_end = 300,
1450N/A .hblank_start = 1580, .htotal = 1979,
1450N/A
1450N/A .progressive = true, .trilevel_sync = true,
1450N/A
1450N/A .vsync_start_f1 = 10, .vsync_start_f2 = 10,
1450N/A .vsync_len = 10,
1450N/A
1450N/A .veq_ena = false,
1450N/A
1450N/A .vi_end_f1 = 29, .vi_end_f2 = 29,
1450N/A .nbr_end = 719,
1450N/A
1450N/A .burst_ena = false,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A .max_srcw = 800
1450N/A },
1450N/A {
1450N/A .name = "1080i@50Hz",
1450N/A .clock = 148800,
1450N/A .refresh = 50000,
1450N/A .oversample = TV_OVERSAMPLE_2X,
1450N/A .component_only = 1,
1450N/A
1450N/A .hsync_end = 88, .hblank_end = 235,
1450N/A .hblank_start = 2155, .htotal = 2639,
1450N/A
1450N/A .progressive = false, .trilevel_sync = true,
1450N/A
1450N/A .vsync_start_f1 = 4, .vsync_start_f2 = 5,
1450N/A .vsync_len = 10,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 4,
1450N/A .veq_start_f2 = 4, .veq_len = 10,
1450N/A
1450N/A
1450N/A .vi_end_f1 = 21, .vi_end_f2 = 22,
1450N/A .nbr_end = 539,
1450N/A
1450N/A .burst_ena = false,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A {
1450N/A .name = "1080i@60Hz",
1450N/A .clock = 148800,
1450N/A .refresh = 60000,
1450N/A .oversample = TV_OVERSAMPLE_2X,
1450N/A .component_only = 1,
1450N/A
1450N/A .hsync_end = 88, .hblank_end = 235,
1450N/A .hblank_start = 2155, .htotal = 2199,
1450N/A
1450N/A .progressive = false, .trilevel_sync = true,
1450N/A
1450N/A .vsync_start_f1 = 4, .vsync_start_f2 = 5,
1450N/A .vsync_len = 10,
1450N/A
1450N/A .veq_ena = true, .veq_start_f1 = 4,
1450N/A .veq_start_f2 = 4, .veq_len = 10,
1450N/A
1450N/A
1450N/A .vi_end_f1 = 21, .vi_end_f2 = 22,
1450N/A .nbr_end = 539,
1450N/A
1450N/A .burst_ena = false,
1450N/A
1450N/A .filter_table = filter_table,
1450N/A },
1450N/A};
1450N/A
1450N/Astatic struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
1450N/A{
1450N/A return container_of(encoder, struct intel_tv, base.base);
1450N/A}
1450N/A
1450N/Astatic struct intel_tv *intel_attached_tv(struct drm_connector *connector)
1450N/A{
1450N/A return container_of(intel_attached_encoder(connector),
1450N/A struct intel_tv,
1450N/A base);
1450N/A}
1450N/A
1450N/Astatic bool
1450N/Aintel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
1450N/A{
1450N/A struct drm_device *dev = encoder->base.dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 tmp = I915_READ(TV_CTL);
1450N/A
1450N/A if (!(tmp & TV_ENC_ENABLE))
1450N/A return false;
1450N/A
1450N/A *pipe = PORT_TO_PIPE(tmp);
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/Astatic void
1450N/Aintel_enable_tv(struct intel_encoder *encoder)
1450N/A{
1450N/A struct drm_device *dev = encoder->base.dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
1450N/A}
1450N/A
1450N/Astatic void
1450N/Aintel_disable_tv(struct intel_encoder *encoder)
1450N/A{
1450N/A struct drm_device *dev = encoder->base.dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A
1450N/A I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
1450N/A}
1450N/A
1450N/Astatic const struct tv_mode *
1450N/Aintel_tv_mode_lookup(const char *tv_format)
1450N/A{
1450N/A int i;
1450N/A
1450N/A for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1450N/A const struct tv_mode *tv_mode = &tv_modes[i];
1450N/A
1450N/A if (!strcmp(tv_format, tv_mode->name))
1450N/A return tv_mode;
1450N/A }
1450N/A return NULL;
1450N/A}
1450N/A
1450N/Astatic const struct tv_mode *
1450N/Aintel_tv_mode_find(struct intel_tv *intel_tv)
1450N/A{
1450N/A return intel_tv_mode_lookup(intel_tv->tv_format);
1450N/A}
1450N/A
1450N/Astatic int /* OSOL_i915 */
1450N/Aintel_tv_mode_valid(struct drm_connector *connector,
1450N/A struct drm_display_mode *mode)
1450N/A{
1450N/A struct intel_tv *intel_tv = intel_attached_tv(connector);
1450N/A const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1450N/A
1450N/A /* Ensure TV refresh is close to desired refresh */
1450N/A if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
1450N/A < 1000)
1450N/A return MODE_OK;
1450N/A
1450N/A return MODE_CLOCK_RANGE;
1450N/A}
1450N/A
1450N/A
1450N/Astatic bool
1450N/Aintel_tv_compute_config(struct intel_encoder *encoder,
1450N/A struct intel_crtc_config *pipe_config)
1450N/A{
1450N/A struct intel_tv *intel_tv = enc_to_intel_tv(&encoder->base);
1450N/A const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1450N/A
1450N/A if (!tv_mode)
1450N/A return false;
1450N/A
1450N/A pipe_config->adjusted_mode.clock = tv_mode->clock;
1450N/A DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
1450N/A pipe_config->pipe_bpp = 8*3;
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/Astatic void
1450N/A/* LINTED */
1450N/Aintel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1450N/A /* LINTED */
1450N/A struct drm_display_mode *adjusted_mode)
1450N/A{
1450N/A struct drm_device *dev = encoder->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_crtc *crtc = encoder->crtc;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
1450N/A const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1450N/A u32 tv_ctl;
1450N/A u32 hctl1, hctl2, hctl3;
1450N/A u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
1450N/A u32 scctl1, scctl2, scctl3;
1450N/A int i, j;
1450N/A const struct video_levels *video_levels;
1450N/A const struct color_conversion *color_conversion;
1450N/A bool burst_ena;
1450N/A int pipe = intel_crtc->pipe;
1450N/A
1450N/A if (!tv_mode)
1450N/A return; /* can't happen (mode_prepare prevents this) */
1450N/A
1450N/A tv_ctl = I915_READ(TV_CTL);
1450N/A tv_ctl &= TV_CTL_SAVE;
1450N/A
1450N/A switch (intel_tv->type) {
1450N/A default:
1450N/A case DRM_MODE_CONNECTOR_Unknown:
1450N/A case DRM_MODE_CONNECTOR_Composite:
1450N/A tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1450N/A video_levels = tv_mode->composite_levels;
1450N/A color_conversion = tv_mode->composite_color;
1450N/A burst_ena = tv_mode->burst_ena;
1450N/A break;
1450N/A case DRM_MODE_CONNECTOR_Component:
1450N/A tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1450N/A video_levels = &component_levels;
1450N/A if (tv_mode->burst_ena)
1450N/A color_conversion = &sdtv_csc_yprpb;
1450N/A else
1450N/A color_conversion = &hdtv_csc_yprpb;
1450N/A burst_ena = false;
1450N/A break;
1450N/A case DRM_MODE_CONNECTOR_SVIDEO:
1450N/A tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1450N/A video_levels = tv_mode->svideo_levels;
1450N/A color_conversion = tv_mode->svideo_color;
1450N/A burst_ena = tv_mode->burst_ena;
1450N/A break;
1450N/A }
1450N/A hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
1450N/A (tv_mode->htotal << TV_HTOTAL_SHIFT);
1450N/A
1450N/A hctl2 = (tv_mode->hburst_start << 16) |
1450N/A (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
1450N/A
1450N/A if (burst_ena)
1450N/A hctl2 |= TV_BURST_ENA;
1450N/A
1450N/A hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
1450N/A (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
1450N/A
1450N/A vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
1450N/A (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
1450N/A (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
1450N/A
1450N/A vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
1450N/A (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
1450N/A (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
1450N/A
1450N/A vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
1450N/A (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1450N/A (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1450N/A
1450N/A if (tv_mode->veq_ena)
1450N/A vctl3 |= TV_EQUAL_ENA;
1450N/A
1450N/A vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1450N/A (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1450N/A
1450N/A vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1450N/A (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1450N/A
1450N/A vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1450N/A (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1450N/A
1450N/A vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1450N/A (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1450N/A
1450N/A if (intel_crtc->pipe == 1)
1450N/A tv_ctl |= TV_ENC_PIPEB_SELECT;
1450N/A tv_ctl |= tv_mode->oversample;
1450N/A
1450N/A if (tv_mode->progressive)
1450N/A tv_ctl |= TV_PROGRESSIVE;
1450N/A if (tv_mode->trilevel_sync)
1450N/A tv_ctl |= TV_TRILEVEL_SYNC;
1450N/A if (tv_mode->pal_burst)
1450N/A tv_ctl |= TV_PAL_BURST;
1450N/A
1450N/A scctl1 = 0;
1450N/A if (tv_mode->dda1_inc)
1450N/A scctl1 |= TV_SC_DDA1_EN;
1450N/A if (tv_mode->dda2_inc)
1450N/A scctl1 |= TV_SC_DDA2_EN;
1450N/A if (tv_mode->dda3_inc)
1450N/A scctl1 |= TV_SC_DDA3_EN;
1450N/A scctl1 |= tv_mode->sc_reset;
1450N/A if (video_levels)
1450N/A scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
1450N/A scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1450N/A
1450N/A scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1450N/A tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1450N/A
1450N/A scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1450N/A tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1450N/A
1450N/A /* Enable two fixes for the chips that need them. */
1450N/A if (dev->pci_device < 0x2772)
1450N/A tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1450N/A
1450N/A I915_WRITE(TV_H_CTL_1, hctl1);
1450N/A I915_WRITE(TV_H_CTL_2, hctl2);
1450N/A I915_WRITE(TV_H_CTL_3, hctl3);
1450N/A I915_WRITE(TV_V_CTL_1, vctl1);
1450N/A I915_WRITE(TV_V_CTL_2, vctl2);
1450N/A I915_WRITE(TV_V_CTL_3, vctl3);
1450N/A I915_WRITE(TV_V_CTL_4, vctl4);
1450N/A I915_WRITE(TV_V_CTL_5, vctl5);
1450N/A I915_WRITE(TV_V_CTL_6, vctl6);
1450N/A I915_WRITE(TV_V_CTL_7, vctl7);
1450N/A I915_WRITE(TV_SC_CTL_1, scctl1);
1450N/A I915_WRITE(TV_SC_CTL_2, scctl2);
1450N/A I915_WRITE(TV_SC_CTL_3, scctl3);
1450N/A
1450N/A if (color_conversion) {
1450N/A I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1450N/A color_conversion->gy);
1450N/A I915_WRITE(TV_CSC_Y2,(color_conversion->by << 16) |
1450N/A color_conversion->ay);
1450N/A I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1450N/A color_conversion->gu);
1450N/A I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
1450N/A color_conversion->au);
1450N/A I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
1450N/A color_conversion->gv);
1450N/A I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
1450N/A color_conversion->av);
1450N/A }
1450N/A
1450N/A if (INTEL_INFO(dev)->gen >= 4)
1450N/A I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1450N/A else
1450N/A I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1450N/A
1450N/A if (video_levels)
1450N/A I915_WRITE(TV_CLR_LEVEL,
1450N/A ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1450N/A (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1450N/A {
1450N/A int pipeconf_reg = PIPECONF(pipe);
1450N/A int dspcntr_reg = DSPCNTR(intel_crtc->plane);
1450N/A int pipeconf = I915_READ(pipeconf_reg);
1450N/A int dspcntr = I915_READ(dspcntr_reg);
1450N/A int xpos = 0x0, ypos = 0x0;
1450N/A unsigned int xsize, ysize;
1450N/A /* Pipe must be off here */
1450N/A I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
1450N/A intel_flush_display_plane(dev_priv, intel_crtc->plane);
1450N/A
1450N/A /* Wait for vblank for the disable to take effect */
1450N/A if (IS_GEN2(dev))
1450N/A intel_wait_for_vblank(dev, intel_crtc->pipe);
1450N/A
1450N/A I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
1450N/A /* Wait for vblank for the disable to take effect. */
1450N/A intel_wait_for_pipe_off(dev, intel_crtc->pipe);
1450N/A
1450N/A /* Filter ctl must be set before TV_WIN_SIZE */
1450N/A I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
1450N/A xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1450N/A if (tv_mode->progressive)
1450N/A ysize = tv_mode->nbr_end + 1;
1450N/A else
1450N/A ysize = 2*tv_mode->nbr_end + 1;
1450N/A
1450N/A xpos += intel_tv->margin[TV_MARGIN_LEFT];
1450N/A ypos += intel_tv->margin[TV_MARGIN_TOP];
1450N/A xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
1450N/A intel_tv->margin[TV_MARGIN_RIGHT]);
1450N/A ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
1450N/A intel_tv->margin[TV_MARGIN_BOTTOM]);
1450N/A I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1450N/A I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
1450N/A
1450N/A I915_WRITE(pipeconf_reg, pipeconf);
1450N/A I915_WRITE(dspcntr_reg, dspcntr);
1450N/A intel_flush_display_plane(dev_priv, intel_crtc->plane);
1450N/A }
1450N/A
1450N/A j = 0;
1450N/A for (i = 0; i < 60; i++)
1450N/A I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1450N/A for (i = 0; i < 60; i++)
1450N/A I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1450N/A for (i = 0; i < 43; i++)
1450N/A I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1450N/A for (i = 0; i < 43; i++)
1450N/A I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1450N/A I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
1450N/A I915_WRITE(TV_CTL, tv_ctl);
1450N/A}
1450N/A
1450N/Astatic const struct drm_display_mode reported_modes[] = {
1450N/A {
1450N/A .name = "NTSC 480i",
1450N/A .clock = 107520,
1450N/A .hdisplay = 1280,
1450N/A .hsync_start = 1368,
1450N/A .hsync_end = 1496,
1450N/A .htotal = 1712,
1450N/A
1450N/A .vdisplay = 1024,
1450N/A .vsync_start = 1027,
1450N/A .vsync_end = 1034,
1450N/A .vtotal = 1104,
1450N/A .type = DRM_MODE_TYPE_DRIVER,
1450N/A },
1450N/A};
1450N/A
1450N/A/**
1450N/A * Detects TV presence by checking for load.
1450N/A *
1450N/A * Requires that the current pipe's DPLL is active.
1450N/A
1450N/A * \return true if TV is connected.
1450N/A * \return false if TV is disconnected.
1450N/A */
1450N/Astatic int
1450N/Aintel_tv_detect_type (struct intel_tv *intel_tv,
1450N/A struct drm_connector *connector)
1450N/A{
1450N/A struct drm_encoder *encoder = &intel_tv->base.base;
1450N/A struct drm_crtc *crtc = encoder->crtc;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct drm_device *dev = encoder->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A unsigned long irqflags;
1450N/A u32 tv_ctl, save_tv_ctl;
1450N/A u32 tv_dac, save_tv_dac;
1450N/A int type;
1450N/A
1450N/A /* Disable TV interrupts around load detect or we'll recurse */
1450N/A if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1450N/A spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1450N/A i915_disable_pipestat(dev_priv, 0,
1450N/A PIPE_HOTPLUG_INTERRUPT_ENABLE |
1450N/A PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1450N/A spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1450N/A }
1450N/A
1450N/A save_tv_dac = tv_dac = I915_READ(TV_DAC);
1450N/A save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1450N/A
1450N/A /* Poll for TV detection */
1450N/A tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
1450N/A tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
1450N/A if (intel_crtc->pipe == 1)
1450N/A tv_ctl |= TV_ENC_PIPEB_SELECT;
1450N/A else
1450N/A tv_ctl &= ~TV_ENC_PIPEB_SELECT;
1450N/A
1450N/A tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
1450N/A tv_dac |= (TVDAC_STATE_CHG_EN |
1450N/A TVDAC_A_SENSE_CTL |
1450N/A TVDAC_B_SENSE_CTL |
1450N/A TVDAC_C_SENSE_CTL |
1450N/A DAC_CTL_OVERRIDE |
1450N/A DAC_A_0_7_V |
1450N/A DAC_B_0_7_V |
1450N/A DAC_C_0_7_V);
1450N/A
1450N/A
1450N/A /*
1450N/A * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1450N/A * the TV is misdetected. This is hardware requirement.
1450N/A */
1450N/A if (IS_GM45(dev))
1450N/A tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1450N/A TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1450N/A
1450N/A I915_WRITE(TV_CTL, tv_ctl);
1450N/A I915_WRITE(TV_DAC, tv_dac);
1450N/A POSTING_READ(TV_DAC);
1450N/A
1450N/A intel_wait_for_vblank(intel_tv->base.base.dev,
1450N/A to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1450N/A
1450N/A type = -1;
1450N/A tv_dac = I915_READ(TV_DAC);
1450N/A DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1450N/A /*
1450N/A * A B C
1450N/A * 0 1 1 Composite
1450N/A * 1 0 X svideo
1450N/A * 0 0 0 Component
1450N/A */
1450N/A if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1450N/A DRM_DEBUG_KMS("Detected Composite TV connection\n");
1450N/A type = DRM_MODE_CONNECTOR_Composite;
1450N/A } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1450N/A DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1450N/A type = DRM_MODE_CONNECTOR_SVIDEO;
1450N/A } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1450N/A DRM_DEBUG_KMS("Detected Component TV connection\n");
1450N/A type = DRM_MODE_CONNECTOR_Component;
1450N/A } else {
1450N/A DRM_DEBUG_KMS("Unrecognised TV connection\n");
1450N/A type = -1;
1450N/A }
1450N/A
1450N/A I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1450N/A I915_WRITE(TV_CTL, save_tv_ctl);
1450N/A POSTING_READ(TV_CTL);
1450N/A
1450N/A /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1450N/A intel_wait_for_vblank(intel_tv->base.base.dev,
1450N/A to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1450N/A
1450N/A /* Restore interrupt config */
1450N/A if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1450N/A spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1450N/A i915_enable_pipestat(dev_priv, 0,
1450N/A PIPE_HOTPLUG_INTERRUPT_ENABLE |
1450N/A PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1450N/A spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1450N/A }
1450N/A
1450N/A return type;
1450N/A}
1450N/A
1450N/A/*
1450N/A * Here we set accurate tv format according to connector type
1450N/A * i.e Component TV should not be assigned by NTSC or PAL
1450N/A */
1450N/Astatic void intel_tv_find_better_format(struct drm_connector *connector)
1450N/A{
1450N/A struct intel_tv *intel_tv = intel_attached_tv(connector);
1450N/A const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1450N/A int i;
1450N/A
1450N/A if (tv_mode == NULL ||
1450N/A (intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1450N/A tv_mode->component_only)
1450N/A return;
1450N/A
1450N/A
1450N/A for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
1450N/A tv_mode = tv_modes + i;
1450N/A
1450N/A if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1450N/A tv_mode->component_only)
1450N/A break;
1450N/A }
1450N/A
1450N/A intel_tv->tv_format = tv_mode->name;
1450N/A drm_object_property_set_value(&connector->base,
1450N/A connector->dev->mode_config.tv_mode_property, i);
1450N/A}
1450N/A
1450N/A/**
1450N/A * Detect the TV connection.
1450N/A *
1450N/A * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure
1450N/A * we have a pipe programmed in order to probe the TV.
1450N/A */
1450N/Astatic enum drm_connector_status
1450N/Aintel_tv_detect(struct drm_connector *connector, bool force)
1450N/A{
1450N/A struct drm_display_mode mode;
1450N/A struct intel_tv *intel_tv = intel_attached_tv(connector);
1450N/A int type;
1450N/A
1450N/A mode = reported_modes[0];
1450N/A
1450N/A if (force) {
1450N/A struct intel_load_detect_pipe tmp;
1450N/A
1450N/A if (intel_get_load_detect_pipe(connector, &mode, &tmp)) {
1450N/A type = intel_tv_detect_type(intel_tv, connector);
1450N/A intel_release_load_detect_pipe(connector, &tmp);
1450N/A } else
1450N/A return connector_status_unknown;
1450N/A } else
1450N/A return connector->status;
1450N/A
1450N/A if (type < 0)
1450N/A return connector_status_disconnected;
1450N/A
1450N/A intel_tv->type = type;
1450N/A intel_tv_find_better_format(connector);
1450N/A
1450N/A return connector_status_connected;
1450N/A}
1450N/A
1450N/Astatic const struct input_res {
1450N/A const char *name;
1450N/A int w, h;
1450N/A} input_res_table[] = {
1450N/A {"640x480", 640, 480},
1450N/A {"800x600", 800, 600},
1450N/A {"1024x768", 1024, 768},
1450N/A {"1280x1024", 1280, 1024},
1450N/A {"848x480", 848, 480},
1450N/A {"1280x720", 1280, 720},
1450N/A {"1920x1080", 1920, 1080},
1450N/A};
1450N/A
1450N/A/*
1450N/A * Chose preferred mode according to line number of TV format
1450N/A */
1450N/Astatic void
1450N/Aintel_tv_chose_preferred_modes(struct drm_connector *connector,
1450N/A struct drm_display_mode *mode_ptr)
1450N/A{
1450N/A struct intel_tv *intel_tv = intel_attached_tv(connector);
1450N/A const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1450N/A
1450N/A if (tv_mode == NULL)
1450N/A mode_ptr->type |= DRM_MODE_TYPE_BUILTIN;
1450N/A else if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1450N/A mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1450N/A else if (tv_mode->nbr_end > 480) {
1450N/A if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
1450N/A if (mode_ptr->vdisplay == 720)
1450N/A mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1450N/A } else if (mode_ptr->vdisplay == 1080)
1450N/A mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1450N/A }
1450N/A}
1450N/A
1450N/A/**
1450N/A * Stub get_modes function.
1450N/A *
1450N/A * This should probably return a set of fixed modes, unless we can figure out
1450N/A * how to probe modes off of TV connections.
1450N/A */
1450N/A
1450N/Astatic int
1450N/Aintel_tv_get_modes(struct drm_connector *connector)
1450N/A{
1450N/A struct drm_display_mode *mode_ptr;
1450N/A struct intel_tv *intel_tv = intel_attached_tv(connector);
1450N/A const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1450N/A int j, count = 0;
1450N/A u64 tmp;
1450N/A
1450N/A if(tv_mode == NULL)
1450N/A return 0;
1450N/A
1450N/A for (j = 0; j < ARRAY_SIZE(input_res_table);
1450N/A j++) {
1450N/A const struct input_res *input = &input_res_table[j];
1450N/A unsigned int hactive_s = input->w;
1450N/A unsigned int vactive_s = input->h;
1450N/A
1450N/A if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
1450N/A continue;
1450N/A
1450N/A if (input->w > 1024 && (!tv_mode->progressive
1450N/A && !tv_mode->component_only))
1450N/A continue;
1450N/A
1450N/A mode_ptr = drm_mode_create(connector->dev);
1450N/A if (!mode_ptr)
1450N/A continue;
1450N/A (void) strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN);
1450N/A
1450N/A mode_ptr->hdisplay = hactive_s;
1450N/A mode_ptr->hsync_start = hactive_s + 1;
1450N/A mode_ptr->hsync_end = hactive_s + 64;
1450N/A if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
1450N/A mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
1450N/A mode_ptr->htotal = hactive_s + 96;
1450N/A
1450N/A mode_ptr->vdisplay = vactive_s;
1450N/A mode_ptr->vsync_start = vactive_s + 1;
1450N/A mode_ptr->vsync_end = vactive_s + 32;
1450N/A if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
1450N/A mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
1450N/A mode_ptr->vtotal = vactive_s + 33;
1450N/A
1450N/A tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
1450N/A tmp *= mode_ptr->htotal;
1450N/A tmp = div_u64(tmp, 1000000);
1450N/A mode_ptr->clock = (int) tmp;
1450N/A
1450N/A mode_ptr->type = DRM_MODE_TYPE_DRIVER;
1450N/A intel_tv_chose_preferred_modes(connector, mode_ptr);
1450N/A drm_mode_probed_add(connector, mode_ptr);
1450N/A count++;
1450N/A }
1450N/A
1450N/A return count;
1450N/A}
1450N/A
1450N/Astatic void
1450N/Aintel_tv_destroy (struct drm_connector *connector)
1450N/A{
1450N/A drm_connector_cleanup(connector);
1450N/A kfree(connector, sizeof(struct intel_connector));
1450N/A}
1450N/A
1450N/A
1450N/Astatic int
1450N/Aintel_tv_set_property(struct drm_connector *connector, struct drm_property *property,
1450N/A uint64_t val)
1450N/A{
1450N/A struct drm_device *dev = connector->dev;
1450N/A struct intel_tv *intel_tv = intel_attached_tv(connector);
1450N/A struct drm_crtc *crtc = intel_tv->base.base.crtc;
1450N/A int ret = 0;
1450N/A bool changed = false;
1450N/A
1450N/A ret = drm_object_property_set_value(&connector->base, property, val);
1450N/A if (ret < 0)
1450N/A goto out;
1450N/A
1450N/A if (property == dev->mode_config.tv_left_margin_property &&
1450N/A intel_tv->margin[TV_MARGIN_LEFT] != val) {
1450N/A intel_tv->margin[TV_MARGIN_LEFT] = (int) val;
1450N/A changed = true;
1450N/A } else if (property == dev->mode_config.tv_right_margin_property &&
1450N/A intel_tv->margin[TV_MARGIN_RIGHT] != val) {
1450N/A intel_tv->margin[TV_MARGIN_RIGHT] = (int) val;
1450N/A changed = true;
1450N/A } else if (property == dev->mode_config.tv_top_margin_property &&
1450N/A intel_tv->margin[TV_MARGIN_TOP] != val) {
1450N/A intel_tv->margin[TV_MARGIN_TOP] = (int) val;
1450N/A changed = true;
1450N/A } else if (property == dev->mode_config.tv_bottom_margin_property &&
1450N/A intel_tv->margin[TV_MARGIN_BOTTOM] != val) {
1450N/A intel_tv->margin[TV_MARGIN_BOTTOM] = (int) val;
1450N/A changed = true;
1450N/A } else if (property == dev->mode_config.tv_mode_property) {
1450N/A if (val >= ARRAY_SIZE(tv_modes)) {
1450N/A ret = -EINVAL;
1450N/A goto out;
1450N/A }
1450N/A if (!strcmp(intel_tv->tv_format, tv_modes[val].name))
1450N/A goto out;
1450N/A
1450N/A intel_tv->tv_format = tv_modes[val].name;
1450N/A changed = true;
1450N/A } else {
1450N/A ret = -EINVAL;
1450N/A goto out;
1450N/A }
1450N/A
1450N/A if (changed && crtc)
1450N/A intel_crtc_restore_mode(crtc);
1450N/Aout:
1450N/A return ret;
1450N/A}
1450N/A
1450N/Astatic const struct drm_encoder_helper_funcs intel_tv_helper_funcs = {
1450N/A .mode_set = intel_tv_mode_set,
1450N/A};
1450N/A
1450N/Astatic const struct drm_connector_funcs intel_tv_connector_funcs = {
1450N/A .dpms = intel_connector_dpms,
1450N/A .detect = intel_tv_detect,
1450N/A .destroy = intel_tv_destroy,
1450N/A .set_property = intel_tv_set_property,
1450N/A .fill_modes = drm_helper_probe_single_connector_modes,
1450N/A};
1450N/A
1450N/Astatic const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1450N/A .mode_valid = intel_tv_mode_valid,
1450N/A .get_modes = intel_tv_get_modes,
1450N/A .best_encoder = intel_best_encoder,
1450N/A};
1450N/A
1450N/Astatic const struct drm_encoder_funcs intel_tv_enc_funcs = {
1450N/A .destroy = intel_encoder_destroy,
1450N/A};
1450N/A
1450N/A/*
1450N/A * Enumerate the child dev array parsed from VBT to check whether
1450N/A * the integrated TV is present.
1450N/A * If it is present, return 1.
1450N/A * If it is not present, return false.
1450N/A * If no child dev is parsed from VBT, it assumes that the TV is present.
1450N/A */
1450N/Astatic int tv_is_present_in_vbt(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct child_device_config *p_child;
1450N/A int i, ret;
1450N/A
1450N/A if (!dev_priv->vbt.child_dev_num)
1450N/A return 1;
1450N/A
1450N/A ret = 0;
1450N/A for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1450N/A p_child = dev_priv->vbt.child_dev + i;
1450N/A /*
1450N/A * If the device type is not TV, continue.
1450N/A */
1450N/A if (p_child->device_type != DEVICE_TYPE_INT_TV &&
1450N/A p_child->device_type != DEVICE_TYPE_TV)
1450N/A continue;
1450N/A /* Only when the addin_offset is non-zero, it is regarded
1450N/A * as present.
1450N/A */
1450N/A if (p_child->addin_offset) {
1450N/A ret = 1;
1450N/A break;
1450N/A }
1450N/A }
1450N/A return ret;
1450N/A}
1450N/A
1450N/Avoid
1450N/Aintel_tv_init(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct drm_connector *connector;
1450N/A struct intel_tv *intel_tv;
1450N/A struct intel_encoder *intel_encoder;
1450N/A struct intel_connector *intel_connector;
1450N/A u32 tv_dac_on, tv_dac_off, save_tv_dac;
1450N/A char *tv_format_names[ARRAY_SIZE(tv_modes)];
1450N/A int i, initial_mode = 0;
1450N/A
1450N/A if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1450N/A return;
1450N/A
1450N/A if (!tv_is_present_in_vbt(dev)) {
1450N/A DRM_DEBUG_KMS("Integrated TV is not present.\n");
1450N/A return;
1450N/A }
1450N/A /* Even if we have an encoder we may not have a connector */
1450N/A if (!dev_priv->vbt.int_tv_support)
1450N/A return;
1450N/A
1450N/A /*
1450N/A * Sanity check the TV output by checking to see if the
1450N/A * DAC register holds a value
1450N/A */
1450N/A save_tv_dac = I915_READ(TV_DAC);
1450N/A
1450N/A I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1450N/A tv_dac_on = I915_READ(TV_DAC);
1450N/A
1450N/A I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1450N/A tv_dac_off = I915_READ(TV_DAC);
1450N/A
1450N/A I915_WRITE(TV_DAC, save_tv_dac);
1450N/A
1450N/A /*
1450N/A * If the register does not hold the state change enable
1450N/A * bit, (either as a 0 or a 1), assume it doesn't really
1450N/A * exist
1450N/A */
1450N/A if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1450N/A (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1450N/A return;
1450N/A
1450N/A intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL);
1450N/A if (!intel_tv) {
1450N/A return;
1450N/A }
1450N/A
1450N/A intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1450N/A if (!intel_connector) {
1450N/A kfree(intel_tv, sizeof(*intel_tv));
1450N/A return;
1450N/A }
1450N/A
1450N/A intel_encoder = &intel_tv->base;
1450N/A connector = &intel_connector->base;
1450N/A
1450N/A /* The documentation, for the older chipsets at least, recommend
1450N/A * using a polling method rather than hotplug detection for TVs.
1450N/A * This is because in order to perform the hotplug detection, the PLLs
1450N/A * for the TV must be kept alive increasing power drain and starving
1450N/A * bandwidth from other encoders. Notably for instance, it causes
1450N/A * pipe underruns on Crestline when this encoder is supposedly idle.
1450N/A *
1450N/A * More recent chipsets favour HDMI rather than integrated S-Video.
1450N/A */
1450N/A connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1450N/A
1450N/A (void) drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1450N/A DRM_MODE_CONNECTOR_SVIDEO);
1450N/A
1450N/A (void) drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
1450N/A DRM_MODE_ENCODER_TVDAC);
1450N/A
1450N/A intel_encoder->compute_config = intel_tv_compute_config;
1450N/A intel_encoder->enable = intel_enable_tv;
1450N/A intel_encoder->disable = intel_disable_tv;
1450N/A intel_encoder->get_hw_state = intel_tv_get_hw_state;
1450N/A intel_connector->get_hw_state = intel_connector_get_hw_state;
1450N/A
1450N/A intel_connector_attach_encoder(intel_connector, intel_encoder);
1450N/A intel_encoder->type = INTEL_OUTPUT_TVOUT;
1450N/A intel_encoder->type_size = sizeof(struct intel_tv);
1450N/A intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1450N/A intel_encoder->cloneable = false;
1450N/A intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
1450N/A intel_encoder->base.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
1450N/A intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
1450N/A
1450N/A /* BIOS margin values */
1450N/A intel_tv->margin[TV_MARGIN_LEFT] = 54;
1450N/A intel_tv->margin[TV_MARGIN_TOP] = 36;
1450N/A intel_tv->margin[TV_MARGIN_RIGHT] = 46;
1450N/A intel_tv->margin[TV_MARGIN_BOTTOM] = 37;
1450N/A
1450N/A intel_tv->tv_format = tv_modes[initial_mode].name;
1450N/A
1450N/A drm_encoder_helper_add(&intel_encoder->base, &intel_tv_helper_funcs);
1450N/A (void) drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1450N/A connector->interlace_allowed = false;
1450N/A connector->doublescan_allowed = false;
1450N/A
1450N/A /* Create TV properties then attach current values */
1450N/A for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
1450N/A tv_format_names[i] = (char *)tv_modes[i].name;
1450N/A (void) drm_mode_create_tv_properties(dev,
1450N/A ARRAY_SIZE(tv_modes),
1450N/A tv_format_names);
1450N/A
1450N/A drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property,
1450N/A initial_mode);
1450N/A drm_object_attach_property(&connector->base,
1450N/A dev->mode_config.tv_left_margin_property,
1450N/A intel_tv->margin[TV_MARGIN_LEFT]);
1450N/A drm_object_attach_property(&connector->base,
1450N/A dev->mode_config.tv_top_margin_property,
1450N/A intel_tv->margin[TV_MARGIN_TOP]);
1450N/A drm_object_attach_property(&connector->base,
1450N/A dev->mode_config.tv_right_margin_property,
1450N/A intel_tv->margin[TV_MARGIN_RIGHT]);
1450N/A drm_object_attach_property(&connector->base,
1450N/A dev->mode_config.tv_bottom_margin_property,
1450N/A intel_tv->margin[TV_MARGIN_BOTTOM]);
1450N/A}