Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:I915_READ
197 	clkcfg = I915_READ(CLKCFG);
227 	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
237 	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
256 				I915_READ(pp_stat_reg),
257 				I915_READ(pp_ctrl_reg));
348 			  I915_READ(ch_ctl));
375 			status = I915_READ(ch_ctl);
426 		unpack_aux(I915_READ(ch_data + i),
804 	dpa_ctl = I915_READ(DP_A);
856 	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
929 			I915_READ(pp_stat_reg),
930 			I915_READ(pp_ctrl_reg));
932 	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
934 				I915_READ(pp_stat_reg),
935 				I915_READ(pp_ctrl_reg));
970 	control = I915_READ(pp_ctrl_reg);
1010 			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1042 		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1220 	dpa_ctl = I915_READ(DP_A);
1247 	dpa_ctl = I915_READ(DP_A);
1299 	u32 tmp = I915_READ(intel_dp->output_reg);
1328 			trans_dp = I915_READ(TRANS_DP_CTL(i));
1353 		tmp = I915_READ(intel_dp->output_reg);
1364 		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1415 	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1926 		uint32_t temp = I915_READ(DP_TP_CTL(port));
2021 	val = I915_READ(DP_TP_CTL(port));
2036 	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2228 	if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
2246 	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2503 	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2873 	pp_on = I915_READ(pp_on_reg);
2874 	pp_off = I915_READ(pp_off_reg);
2875 	pp_div = I915_READ(pp_div_reg);
2978 		port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2993 		      I915_READ(pp_on_reg),
2994 		      I915_READ(pp_off_reg),
2995 		      I915_READ(pp_div_reg));
3090 	intel_dp->DP = I915_READ(intel_dp->output_reg);
3210 		u32 temp = I915_READ(PEG_BAND_GAP_DATA);