Lines Matching refs:I915_READ
69 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
77 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
742 frame = I915_READ(frame_reg);
780 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
783 if (wait_for(I915_READ(pipestat_reg) &
816 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
831 last_line = I915_READ(reg) & line_mask;
833 } while (((I915_READ(reg) & line_mask) != last_line) &&
882 return I915_READ(SDEISR) & bit;
899 val = I915_READ(reg);
957 val = I915_READ(reg);
961 val = I915_READ(reg);
979 val = I915_READ(reg);
1003 val = I915_READ(reg);
1015 val = I915_READ(reg);
1036 val = I915_READ(pp_reg);
1041 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1067 val = I915_READ(reg);
1084 val = I915_READ(reg);
1105 val = I915_READ(reg);
1115 val = I915_READ(reg);
1134 val = I915_READ(reg);
1141 val = I915_READ(reg);
1147 val = I915_READ(reg);
1164 val = I915_READ(PCH_DREF_CONTROL);
1179 val = I915_READ(reg);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 u32 val = I915_READ(reg);
1267 u32 val = I915_READ(reg);
1288 val = I915_READ(reg);
1294 val = I915_READ(reg);
1332 val = I915_READ(reg);
1369 val = I915_READ(reg);
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1386 'B' + port, I915_READ(DPLL(0)));
1488 val = I915_READ(reg);
1494 val = I915_READ(reg);
1495 pipeconf_val = I915_READ(PIPECONF(pipe));
1517 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1534 val = I915_READ(_TRANSA_CHICKEN2);
1539 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1548 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1566 val = I915_READ(reg);
1570 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1576 val = I915_READ(reg);
1586 val = I915_READ(LPT_TRANSCONF);
1590 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1594 val = I915_READ(_TRANSA_CHICKEN2);
1648 val = I915_READ(reg);
1688 val = I915_READ(reg);
1704 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1706 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1727 val = I915_READ(reg);
1751 val = I915_READ(reg);
1895 dspcntr = I915_READ(reg);
1996 dspcntr = I915_READ(reg);
2233 temp = I915_READ(reg);
2244 temp = I915_READ(reg);
2260 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2285 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2286 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2288 temp = I915_READ(SOUTH_CHICKEN1);
2312 temp = I915_READ(reg);
2321 temp = I915_READ(reg);
2329 temp = I915_READ(reg);
2344 temp = I915_READ(reg);
2358 temp = I915_READ(reg);
2364 temp = I915_READ(reg);
2374 temp = I915_READ(reg);
2409 temp = I915_READ(reg);
2419 temp = I915_READ(reg);
2433 temp = I915_READ(reg);
2448 temp = I915_READ(reg);
2458 temp = I915_READ(reg);
2475 temp = I915_READ(reg);
2486 temp = I915_READ(reg);
2501 temp = I915_READ(reg);
2511 temp = I915_READ(reg);
2541 temp = I915_READ(reg);
2550 I915_READ(FDI_RX_IIR(pipe)));
2554 temp = I915_READ(reg);
2568 temp = I915_READ(reg);
2580 temp = I915_READ(reg);
2589 temp = I915_READ(reg);
2593 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2604 temp = I915_READ(reg);
2612 temp = I915_READ(reg);
2622 temp = I915_READ(reg);
2631 temp = I915_READ(reg);
2656 temp = I915_READ(reg);
2659 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2666 temp = I915_READ(reg);
2674 temp = I915_READ(reg);
2692 temp = I915_READ(reg);
2697 temp = I915_READ(reg);
2704 temp = I915_READ(reg);
2722 temp = I915_READ(reg);
2727 temp = I915_READ(reg);
2729 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2742 temp = I915_READ(reg);
2748 temp = I915_READ(reg);
2758 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2901 I915_READ(HTOTAL(cpu_transcoder)));
2903 I915_READ(HBLANK(cpu_transcoder)));
2905 I915_READ(HSYNC(cpu_transcoder)));
2908 I915_READ(VTOTAL(cpu_transcoder)));
2910 I915_READ(VBLANK(cpu_transcoder)));
2912 I915_READ(VSYNC(cpu_transcoder)));
2914 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2938 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2955 temp = I915_READ(PCH_DPLL_SEL);
2975 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2977 temp = I915_READ(reg);
3079 if ((dpll & 0x7fffffff) == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3080 fp == I915_READ(PCH_FP0(pll->id))) {
3133 temp = I915_READ(dslreg);
3135 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3136 if (wait_for(I915_READ(dslreg) != temp, 5))
3207 temp = I915_READ(PCH_LVDS);
3434 temp = I915_READ(reg);
3441 temp = I915_READ(PCH_DPLL_SEL);
3556 u32 cntl = I915_READ(CURCNTR(pipe));
3559 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3565 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3583 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3696 I915_READ(PFIT_CONTROL));
4510 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4734 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4751 tmp = I915_READ(HTOTAL(cpu_transcoder));
4754 tmp = I915_READ(HBLANK(cpu_transcoder));
4757 tmp = I915_READ(HSYNC(cpu_transcoder));
4761 tmp = I915_READ(VTOTAL(cpu_transcoder));
4764 tmp = I915_READ(VBLANK(cpu_transcoder));
4767 tmp = I915_READ(VSYNC(cpu_transcoder));
4771 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4777 tmp = I915_READ(PIPESRC(crtc->pipe));
4967 tmp = I915_READ(PFIT_CONTROL);
4981 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4984 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4997 tmp = I915_READ(PIPECONF(crtc->pipe));
5006 tmp = I915_READ(DPLL_MD(crtc->pipe));
5011 tmp = I915_READ(DPLL(crtc->pipe));
5069 val = I915_READ(PCH_DREF_CONTROL);
5213 tmp = I915_READ(SOUTH_CHICKEN2);
5217 if (wait_for_atomic(I915_READ(SOUTH_CHICKEN2) &
5221 tmp = I915_READ(SOUTH_CHICKEN2);
5225 if (wait_for_atomic((I915_READ(SOUTH_CHICKEN2) &
5559 temp = I915_READ(SOUTH_CHICKEN1);
5563 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5564 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5582 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5583 DRM_DEBUG_KMS("bc_bifurcation select 0x%x", I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5842 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5843 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5844 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5846 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5847 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5858 tmp = I915_READ(PF_CTL(crtc->pipe));
5861 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5862 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5885 tmp = I915_READ(PIPECONF(crtc->pipe));
5889 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5895 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5908 tmp = I915_READ(PCH_DPLL_SEL);
6001 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6027 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6036 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6038 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6041 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6055 (I915_READ(IPS_CTL) & IPS_ENABLE);
6111 i = I915_READ(reg_eldv);
6120 i = I915_READ(reg_elda);
6125 if (I915_READ(reg_edid) != *((uint32_t *)(uintptr_t)eld + i))
6140 i = I915_READ(G4X_AUD_VID_DID);
6153 i = I915_READ(G4X_AUD_CNTL_ST);
6166 i = I915_READ(G4X_AUD_CNTL_ST);
6194 tmp = I915_READ(aud_cntrl_st2);
6202 tmp = I915_READ(aud_cntrl_st2);
6206 tmp = I915_READ(aud_cntrl_st2);
6210 tmp = I915_READ(aud_config);
6234 i = I915_READ(aud_cntrl_st2);
6241 i = I915_READ(aud_cntl_st);
6252 i = I915_READ(aud_cntrl_st2);
6286 i = I915_READ(aud_cntl_st);
6312 i = I915_READ(aud_cntrl_st2);
6319 i = I915_READ(aud_cntl_st);
6328 i = I915_READ(aud_cntrl_st2);
6383 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6411 cntl = I915_READ(_CURACNTR);
6439 uint32_t cntl = I915_READ(CURCNTR(pipe));
6465 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6947 u32 dpll = I915_READ(DPLL(pipe));
6952 fp = I915_READ(FP0(pipe));
6954 fp = I915_READ(FP1(pipe));
6993 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7038 int htot = I915_READ(HTOTAL(cpu_transcoder));
7039 int hsync = I915_READ(HSYNC(cpu_transcoder));
7040 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7041 int vsync = I915_READ(VSYNC(cpu_transcoder));
7077 dpll = I915_READ(dpll_reg);
7087 dpll = I915_READ(dpll_reg);
7118 dpll = I915_READ(dpll_reg);
7122 dpll = I915_READ(dpll_reg);
7409 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7412 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7453 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7456 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8860 val = I915_READ(PCH_DPLL(pll->id));
8862 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8863 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8877 val = I915_READ(reg);
8898 val = I915_READ(reg);
9030 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9034 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9055 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9062 found = I915_READ(SFUSE_STRAP);
9077 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9082 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9086 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9089 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9092 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9095 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9099 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9102 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9105 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9111 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9125 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9130 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9141 (I915_READ(DP_D) & DP_DETECTED))
9717 val = I915_READ(reg);
9734 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9855 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10163 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10168 error->cursor[i].control = I915_READ(CURCNTR(i));
10169 error->cursor[i].position = I915_READ(CURPOS(i));
10170 error->cursor[i].base = I915_READ(CURBASE(i));
10172 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10173 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10174 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10177 error->plane[i].control = I915_READ(DSPCNTR(i));
10178 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10180 error->plane[i].size = I915_READ(DSPSIZE(i));
10181 error->plane[i].pos = I915_READ(DSPPOS(i));
10184 error->plane[i].addr = I915_READ(DSPADDR(i));
10186 error->plane[i].surface = I915_READ(DSPSURF(i));
10187 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10190 error->pipe[i].source = I915_READ(PIPESRC(i));
10201 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10202 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10203 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10204 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10205 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10206 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10207 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));