1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 1450N/A * Copyright (c) 2006-2008, 2013, Intel Corporation 1450N/A * Jesse Barnes <jesse.barnes@intel.com> 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 1450N/A * DEALINGS IN THE SOFTWARE. 1450N/A * Eric Anholt <eric@anholt.net> 1450N/A/* Intel GPIO access functions */ 1450N/A /* When using bit bashing for I2C, this bit needs to be set to 1 */ 1450N/A /* On most chips, these bits must be preserved in software. */ 1450N/A /* -1 to map pin pair to gmbus index */ 1450N/A * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI 1450N/A * mode. This results in spurious interrupt warnings if the legacy irq no. is 1450N/A * shared with another device. The kernel then disables that interrupt source 1450N/A * and so prevents the other device from working properly. 1450N/A /* Important: The hw handles only the first bit, so set only one! Since 1450N/A * need to wake up periodically and check that ourselves. */ 1450N/A /* Important: The hw handles only the first bit, so set only one! */ 1450N/A * The gmbus controller can combine a 1 or 2 byte write with a read that 1450N/A * immediately follows it by using an "INDEX" cycle. 1450N/A /* GMBUS5 holds 16-bit index */ 1450N/A /* Clear GMBUS5 after each index transfer */ 1450N/A i +=
1;
/* set i to the index of the read xfer */ 1450N/A /* Generate a STOP condition on the bus. Note that gmbus can't generata 1450N/A * a STOP on the very first cycle. To simplify the code we 1450N/A * unconditionally generate the STOP condition with an additional gmbus 1450N/A /* Mark the GMBUS interface as disabled after waiting for idle. 1450N/A * We will re-enable it at the start of the next xfer, 1450N/A * Wait for bus to IDLE before clearing NAK. 1450N/A * If we clear the NAK while bus is still active, then it will stay 1450N/A * active and the next transaction may fail. 1450N/A * If no ACK is received during the address phase of a transaction, the 1450N/A * adapter must report -ENXIO. It is not clear what to return if no ACK 1450N/A * is received at other times. But we have to be careful to not return 1450N/A * spurious -ENXIO because that will prevent i2c and drm edid functions 1450N/A * from retrying. So return -ENXIO only when gmbus properly quiescents - 1450N/A * timing out seems to happen when there _is_ a ddc chip present, but 1450N/A * it's slow responding and only answers on the 2nd retry. 1450N/A /* Toggle the Software Clear Interrupt bit. This has the effect 1450N/A * of resetting the GMBUS controller and so clearing the 1450N/A * BUS_ERROR raised by the slave's NAK. 1450N/A DRM_INFO(
"GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
1450N/A /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 1450N/A * intel_gmbus_setup - instantiate all Intel i2c GMBuses 1450N/A// bus->adapter.dev.parent = &dev->pdev->dev; 1450N/A /* By default use a conservative clock rate */ 1450N/A /* gmbus seems to be broken on i830 */ 1450N/A /* -1 to map pin pair to gmbus index */ 1450N/A for (i = 0; i < GMBUS_NUM_PORTS; i++) { 1450N/A struct intel_gmbus *bus = &dev_priv->gmbus[i]; 1450N/A// i2c_del_adapter(&bus->adapter); 1450N/A/* workaround for fixing hdmi issue */