1450N/A/*
1450N/A * Copyright © 2012-2013 Intel Corporation
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice (including the next
1450N/A * paragraph) shall be included in all copies or substantial portions of the
1450N/A * Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
1450N/A * IN THE SOFTWARE.
1450N/A *
1450N/A * Authors:
1450N/A * Eugeni Dodonov <eugeni.dodonov@intel.com>
1450N/A *
1450N/A */
1450N/A
1450N/A/*
1450N/A * Copyright (c) 2013, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A#include "i915_drv.h"
1450N/A#include "intel_drv.h"
1450N/A
1450N/A/* HDMI/DVI modes ignore everything but the last 2 items. So we share
1450N/A * them for both DP and FDI transports, allowing those ports to
1450N/A * automatically adapt to HDMI connections as well
1450N/A */
1450N/Astatic const u32 hsw_ddi_translations_dp[] = {
1450N/A 0x00FFFFFF, 0x0006000E, /* DP parameters */
1450N/A 0x00D75FFF, 0x0005000A,
1450N/A 0x00C30FFF, 0x00040006,
1450N/A 0x80AAAFFF, 0x000B0000,
1450N/A 0x00FFFFFF, 0x0005000A,
1450N/A 0x00D75FFF, 0x000C0004,
1450N/A 0x80C30FFF, 0x000B0000,
1450N/A 0x00FFFFFF, 0x00040006,
1450N/A 0x80D75FFF, 0x000B0000,
1450N/A 0x00FFFFFF, 0x00040006 /* HDMI parameters */
1450N/A};
1450N/A
1450N/Astatic const u32 hsw_ddi_translations_fdi[] = {
1450N/A 0x00FFFFFF, 0x0007000E, /* FDI parameters */
1450N/A 0x00D75FFF, 0x000F000A,
1450N/A 0x00C30FFF, 0x00060006,
1450N/A 0x00AAAFFF, 0x001E0000,
1450N/A 0x00FFFFFF, 0x000F000A,
1450N/A 0x00D75FFF, 0x00160004,
1450N/A 0x00C30FFF, 0x001E0000,
1450N/A 0x00FFFFFF, 0x00060006,
1450N/A 0x00D75FFF, 0x001E0000,
1450N/A 0x00FFFFFF, 0x00040006 /* HDMI parameters */
1450N/A};
1450N/A
1450N/Astatic enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
1450N/A{
1450N/A struct drm_encoder *encoder = &intel_encoder->base;
1450N/A int type = intel_encoder->type;
1450N/A
1450N/A if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
1450N/A type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
1450N/A struct intel_digital_port *intel_dig_port =
1450N/A enc_to_dig_port(encoder);
1450N/A return intel_dig_port->port;
1450N/A } else if (type == INTEL_OUTPUT_ANALOG) {
1450N/A return PORT_E;
1450N/A } else {
1450N/A DRM_ERROR("Invalid DDI encoder type %d\n", type);
1450N/A BUG();
1450N/A }
1450N/A return I915_MAX_PORTS;
1450N/A}
1450N/A
1450N/A/* On Haswell, DDI port buffers must be programmed with correct values
1450N/A * in advance. The buffer values are different for FDI and DP modes,
1450N/A * but the HDMI/DVI fields are shared among those. So we program the DDI
1450N/A * in either FDI or DP modes only, as HDMI connections will work with both
1450N/A * of those
1450N/A */
1450N/Astatic void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
1450N/A bool use_fdi_mode)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A u32 reg;
1450N/A int i;
1450N/A const u32 *ddi_translations = ((use_fdi_mode) ?
1450N/A hsw_ddi_translations_fdi :
1450N/A hsw_ddi_translations_dp);
1450N/A
1450N/A DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
1450N/A port_name(port),
1450N/A use_fdi_mode ? "FDI" : "DP");
1450N/A
1450N/A if (use_fdi_mode && (port != PORT_E))
1450N/A DRM_ERROR("Programming port %c in FDI mode, this probably will not work.",
1450N/A port_name(port));
1450N/A
1450N/A for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
1450N/A I915_WRITE(reg, ddi_translations[i]);
1450N/A reg += 4;
1450N/A }
1450N/A}
1450N/A
1450N/A/* Program DDI buffers translations for DP. By default, program ports A-D in DP
1450N/A * mode and port E for FDI.
1450N/A */
1450N/Avoid intel_prepare_ddi(struct drm_device *dev)
1450N/A{
1450N/A int port;
1450N/A
1450N/A if (!HAS_DDI(dev))
1450N/A return;
1450N/A
1450N/A for (port = PORT_A; port < PORT_E; port++)
1450N/A intel_prepare_ddi_buffers(dev, port, false);
1450N/A
1450N/A /* DDI E is the suggested one to work in FDI mode, so program is as such
1450N/A * by default. It will have to be re-programmed in case a digital DP
1450N/A * output will be detected on it
1450N/A */
1450N/A intel_prepare_ddi_buffers(dev, PORT_E, true);
1450N/A}
1450N/A
1450N/Astatic const long hsw_ddi_buf_ctl_values[] = {
1450N/A DDI_BUF_EMP_400MV_0DB_HSW,
1450N/A DDI_BUF_EMP_400MV_3_5DB_HSW,
1450N/A DDI_BUF_EMP_400MV_6DB_HSW,
1450N/A DDI_BUF_EMP_400MV_9_5DB_HSW,
1450N/A DDI_BUF_EMP_600MV_0DB_HSW,
1450N/A DDI_BUF_EMP_600MV_3_5DB_HSW,
1450N/A DDI_BUF_EMP_600MV_6DB_HSW,
1450N/A DDI_BUF_EMP_800MV_0DB_HSW,
1450N/A DDI_BUF_EMP_800MV_3_5DB_HSW
1450N/A};
1450N/A
1450N/Astatic void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1450N/A enum port port)
1450N/A{
1450N/A uint32_t reg = DDI_BUF_CTL(port);
1450N/A int i;
1450N/A
1450N/A for (i = 0; i < 8; i++) {
1450N/A udelay(1);
1450N/A if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1450N/A return;
1450N/A }
1450N/A DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1450N/A}
1450N/A
1450N/A/* Starting with Haswell, different DDI ports can work in FDI mode for
1450N/A * connection to the PCH-located connectors. For this, it is necessary to train
1450N/A * both the DDI port and PCH receiver for the desired DDI buffer settings.
1450N/A *
1450N/A * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1450N/A * please note that when FDI mode is active on DDI E, it shares 2 lines with
1450N/A * DDI A (which is used for eDP)
1450N/A */
1450N/A
1450N/Avoid hsw_fdi_link_train(struct drm_crtc *crtc)
1450N/A{
1450N/A struct drm_device *dev = crtc->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A u32 temp, i, rx_ctl_val;
1450N/A
1450N/A /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1450N/A * mode set "sequence for CRT port" document:
1450N/A * - TP1 to TP2 time with the default value
1450N/A * - FDI delay to 90h
1450N/A *
1450N/A * WaFDIAutoLinkSetTimingOverrride:hsw
1450N/A */
1450N/A I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
1450N/A FDI_RX_PWRDN_LANE0_VAL(2) |
1450N/A FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1450N/A
1450N/A /* Enable the PCH Receiver FDI PLL */
1450N/A rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1450N/A FDI_RX_PLL_ENABLE |
1450N/A FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
1450N/A I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
1450N/A POSTING_READ(_FDI_RXA_CTL);
1450N/A udelay(220);
1450N/A
1450N/A /* Switch from Rawclk to PCDclk */
1450N/A rx_ctl_val |= FDI_PCDCLK;
1450N/A I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
1450N/A
1450N/A /* Configure Port Clock Select */
1450N/A I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
1450N/A
1450N/A /* Start the training iterating through available voltages and emphasis,
1450N/A * testing each value twice. */
1450N/A for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
1450N/A /* Configure DP_TP_CTL with auto-training */
1450N/A I915_WRITE(DP_TP_CTL(PORT_E),
1450N/A DP_TP_CTL_FDI_AUTOTRAIN |
1450N/A DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1450N/A DP_TP_CTL_LINK_TRAIN_PAT1 |
1450N/A DP_TP_CTL_ENABLE);
1450N/A
1450N/A /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1450N/A * DDI E does not support port reversal, the functionality is
1450N/A * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1450N/A * port reversal bit */
1450N/A I915_WRITE(DDI_BUF_CTL(PORT_E),
1450N/A DDI_BUF_CTL_ENABLE |
1450N/A ((intel_crtc->config.fdi_lanes - 1) << 1) |
1450N/A hsw_ddi_buf_ctl_values[i / 2]);
1450N/A POSTING_READ(DDI_BUF_CTL(PORT_E));
1450N/A
1450N/A udelay(600);
1450N/A
1450N/A /* Program PCH FDI Receiver TU */
1450N/A I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
1450N/A
1450N/A /* Enable PCH FDI Receiver with auto-training */
1450N/A rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1450N/A I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
1450N/A POSTING_READ(_FDI_RXA_CTL);
1450N/A
1450N/A /* Wait for FDI receiver lane calibration */
1450N/A udelay(30);
1450N/A
1450N/A /* Unset FDI_RX_MISC pwrdn lanes */
1450N/A temp = I915_READ(_FDI_RXA_MISC);
1450N/A temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1450N/A I915_WRITE(_FDI_RXA_MISC, temp);
1450N/A POSTING_READ(_FDI_RXA_MISC);
1450N/A
1450N/A /* Wait for FDI auto training time */
1450N/A udelay(5);
1450N/A
1450N/A temp = I915_READ(DP_TP_STATUS(PORT_E));
1450N/A if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1450N/A DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1450N/A
1450N/A /* Enable normal pixel sending for FDI */
1450N/A I915_WRITE(DP_TP_CTL(PORT_E),
1450N/A DP_TP_CTL_FDI_AUTOTRAIN |
1450N/A DP_TP_CTL_LINK_TRAIN_NORMAL |
1450N/A DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1450N/A DP_TP_CTL_ENABLE);
1450N/A
1450N/A return;
1450N/A }
1450N/A
1450N/A temp = I915_READ(DDI_BUF_CTL(PORT_E));
1450N/A temp &= ~DDI_BUF_CTL_ENABLE;
1450N/A I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1450N/A POSTING_READ(DDI_BUF_CTL(PORT_E));
1450N/A
1450N/A /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1450N/A temp = I915_READ(DP_TP_CTL(PORT_E));
1450N/A temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1450N/A temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1450N/A I915_WRITE(DP_TP_CTL(PORT_E), temp);
1450N/A POSTING_READ(DP_TP_CTL(PORT_E));
1450N/A
1450N/A intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1450N/A
1450N/A rx_ctl_val &= ~FDI_RX_ENABLE;
1450N/A I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
1450N/A POSTING_READ(_FDI_RXA_CTL);
1450N/A
1450N/A /* Reset FDI_RX_MISC pwrdn lanes */
1450N/A temp = I915_READ(_FDI_RXA_MISC);
1450N/A temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1450N/A temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1450N/A I915_WRITE(_FDI_RXA_MISC, temp);
1450N/A POSTING_READ(_FDI_RXA_MISC);
1450N/A }
1450N/A
1450N/A DRM_ERROR("FDI link training failed!\n");
1450N/A}
1450N/A
1450N/Astatic void intel_ddi_mode_set(struct drm_encoder *encoder,
1450N/A struct drm_display_mode *mode,
1450N/A struct drm_display_mode *adjusted_mode)
1450N/A{
1450N/A struct drm_crtc *crtc = encoder->crtc;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1450N/A int port = intel_ddi_get_encoder_port(intel_encoder);
1450N/A int pipe = intel_crtc->pipe;
1450N/A int type = intel_encoder->type;
1450N/A
1450N/A DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
1450N/A port_name(port), pipe_name(pipe));
1450N/A
1450N/A intel_crtc->eld_vld = false;
1450N/A if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A struct intel_digital_port *intel_dig_port =
1450N/A enc_to_dig_port(encoder);
1450N/A
1450N/A intel_dp->DP = intel_dig_port->saved_port_bits |
1450N/A DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
1450N/A intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1450N/A
1450N/A if (intel_dp->has_audio) {
1450N/A DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
1450N/A pipe_name(intel_crtc->pipe));
1450N/A
1450N/A /* write eld */
1450N/A DRM_DEBUG_DRIVER("DP audio: write eld information\n");
1450N/A intel_write_eld(encoder, adjusted_mode);
1450N/A }
1450N/A
1450N/A intel_dp_init_link_config(intel_dp);
1450N/A
1450N/A } else if (type == INTEL_OUTPUT_HDMI) {
1450N/A struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1450N/A
1450N/A if (intel_hdmi->has_audio) {
1450N/A /* Proper support for digital audio needs a new logic
1450N/A * and a new set of registers, so we leave it for future
1450N/A * patch bombing.
1450N/A */
1450N/A DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
1450N/A pipe_name(intel_crtc->pipe));
1450N/A
1450N/A /* write eld */
1450N/A DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
1450N/A intel_write_eld(encoder, adjusted_mode);
1450N/A }
1450N/A
1450N/A intel_hdmi->set_infoframes(encoder, adjusted_mode);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic struct intel_encoder *
1450N/Aintel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
1450N/A{
1450N/A struct drm_device *dev = crtc->dev;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct intel_encoder *intel_encoder, *ret = NULL;
1450N/A int num_encoders = 0;
1450N/A
1450N/A for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
1450N/A ret = intel_encoder;
1450N/A num_encoders++;
1450N/A }
1450N/A
1450N/A if (num_encoders != 1) {
1450N/A DRM_ERROR("%d encoders on crtc for pipe %c\n", num_encoders,
1450N/A pipe_name(intel_crtc->pipe));
1450N/A }
1450N/A
1450N/A BUG_ON(ret == NULL);
1450N/A return ret;
1450N/A}
1450N/A
1450N/Avoid intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1450N/A struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A uint32_t val;
1450N/A
1450N/A switch (intel_crtc->ddi_pll_sel) {
1450N/A case PORT_CLK_SEL_SPLL:
1450N/A plls->spll_refcount--;
1450N/A if (plls->spll_refcount == 0) {
1450N/A DRM_DEBUG_KMS("Disabling SPLL\n");
1450N/A val = I915_READ(SPLL_CTL);
1450N/A WARN_ON(!(val & SPLL_PLL_ENABLE));
1450N/A I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
1450N/A POSTING_READ(SPLL_CTL);
1450N/A }
1450N/A break;
1450N/A case PORT_CLK_SEL_WRPLL1:
1450N/A plls->wrpll1_refcount--;
1450N/A if (plls->wrpll1_refcount == 0) {
1450N/A DRM_DEBUG_KMS("Disabling WRPLL 1\n");
1450N/A val = I915_READ(WRPLL_CTL1);
1450N/A WARN_ON(!(val & WRPLL_PLL_ENABLE));
1450N/A I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
1450N/A POSTING_READ(WRPLL_CTL1);
1450N/A }
1450N/A break;
1450N/A case PORT_CLK_SEL_WRPLL2:
1450N/A plls->wrpll2_refcount--;
1450N/A if (plls->wrpll2_refcount == 0) {
1450N/A DRM_DEBUG_KMS("Disabling WRPLL 2\n");
1450N/A val = I915_READ(WRPLL_CTL2);
1450N/A WARN_ON(!(val & WRPLL_PLL_ENABLE));
1450N/A I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
1450N/A POSTING_READ(WRPLL_CTL2);
1450N/A }
1450N/A break;
1450N/A }
1450N/A
1450N/A if(plls->spll_refcount < 0)
1450N/A DRM_ERROR("Invalid SPLL refcount\n");
1450N/A if(plls->wrpll1_refcount < 0)
1450N/A DRM_ERROR("Invalid WRPLL1 refcount\n");
1450N/A if(plls->wrpll2_refcount < 0)
1450N/A DRM_ERROR("Invalid WRPLL2 refcount\n");
1450N/A
1450N/A intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
1450N/A}
1450N/A
1450N/A#define LC_FREQ 2700
1450N/A#define LC_FREQ_2K (LC_FREQ * 2000)
1450N/A
1450N/A#define P_MIN 2
1450N/A#define P_MAX 64
1450N/A#define P_INC 2
1450N/A
1450N/A/* Constraints for PLL good behavior */
1450N/A#define REF_MIN 48
1450N/A#define REF_MAX 400
1450N/A#define VCO_MIN 2400
1450N/A#define VCO_MAX 4800
1450N/A
1450N/A#define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
1450N/A
1450N/Astruct wrpll_rnp {
1450N/A unsigned p, n2, r2;
1450N/A};
1450N/A
1450N/Astatic unsigned wrpll_get_budget_for_freq(int clock)
1450N/A{
1450N/A unsigned budget;
1450N/A
1450N/A switch (clock) {
1450N/A case 25175000:
1450N/A case 25200000:
1450N/A case 27000000:
1450N/A case 27027000:
1450N/A case 37762500:
1450N/A case 37800000:
1450N/A case 40500000:
1450N/A case 40541000:
1450N/A case 54000000:
1450N/A case 54054000:
1450N/A case 59341000:
1450N/A case 59400000:
1450N/A case 72000000:
1450N/A case 74176000:
1450N/A case 74250000:
1450N/A case 81000000:
1450N/A case 81081000:
1450N/A case 89012000:
1450N/A case 89100000:
1450N/A case 108000000:
1450N/A case 108108000:
1450N/A case 111264000:
1450N/A case 111375000:
1450N/A case 148352000:
1450N/A case 148500000:
1450N/A case 162000000:
1450N/A case 162162000:
1450N/A case 222525000:
1450N/A case 222750000:
1450N/A case 296703000:
1450N/A case 297000000:
1450N/A budget = 0;
1450N/A break;
1450N/A case 233500000:
1450N/A case 245250000:
1450N/A case 247750000:
1450N/A case 253250000:
1450N/A case 298000000:
1450N/A budget = 1500;
1450N/A break;
1450N/A case 169128000:
1450N/A case 169500000:
1450N/A case 179500000:
1450N/A case 202000000:
1450N/A budget = 2000;
1450N/A break;
1450N/A case 256250000:
1450N/A case 262500000:
1450N/A case 270000000:
1450N/A case 272500000:
1450N/A case 273750000:
1450N/A case 280750000:
1450N/A case 281250000:
1450N/A case 286000000:
1450N/A case 291750000:
1450N/A budget = 4000;
1450N/A break;
1450N/A case 267250000:
1450N/A case 268500000:
1450N/A budget = 5000;
1450N/A break;
1450N/A default:
1450N/A budget = 1000;
1450N/A break;
1450N/A }
1450N/A
1450N/A return budget;
1450N/A}
1450N/A
1450N/Astatic void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
1450N/A unsigned r2, unsigned n2, unsigned p,
1450N/A struct wrpll_rnp *best)
1450N/A{
1450N/A uint64_t a, b, c, d, diff, diff_best;
1450N/A
1450N/A /* No best (r,n,p) yet */
1450N/A if (best->p == 0) {
1450N/A best->p = p;
1450N/A best->n2 = n2;
1450N/A best->r2 = r2;
1450N/A return;
1450N/A }
1450N/A
1450N/A /*
1450N/A * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
1450N/A * freq2k.
1450N/A *
1450N/A * delta = 1e6 *
1450N/A * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
1450N/A * freq2k;
1450N/A *
1450N/A * and we would like delta <= budget.
1450N/A *
1450N/A * If the discrepancy is above the PPM-based budget, always prefer to
1450N/A * improve upon the previous solution. However, if you're within the
1450N/A * budget, try to maximize Ref * VCO, that is N / (P * R^2).
1450N/A */
1450N/A a = freq2k * budget * p * r2;
1450N/A b = freq2k * budget * best->p * best->r2;
1450N/A diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
1450N/A diff_best = ABS_DIFF((freq2k * best->p * best->r2),
1450N/A (LC_FREQ_2K * best->n2));
1450N/A c = 1000000 * diff;
1450N/A d = 1000000 * diff_best;
1450N/A
1450N/A if (a < c && b < d) {
1450N/A /* If both are above the budget, pick the closer */
1450N/A if (best->p * best->r2 * diff < p * r2 * diff_best) {
1450N/A best->p = p;
1450N/A best->n2 = n2;
1450N/A best->r2 = r2;
1450N/A }
1450N/A } else if (a >= c && b < d) {
1450N/A /* If A is below the threshold but B is above it? Update. */
1450N/A best->p = p;
1450N/A best->n2 = n2;
1450N/A best->r2 = r2;
1450N/A } else if (a >= c && b >= d) {
1450N/A /* Both are below the limit, so pick the higher n2/(r2*r2) */
1450N/A if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
1450N/A best->p = p;
1450N/A best->n2 = n2;
1450N/A best->r2 = r2;
1450N/A }
1450N/A }
1450N/A /* Otherwise a < c && b >= d, do nothing */
1450N/A}
1450N/A
1450N/Astatic void
1450N/Aintel_ddi_calculate_wrpll(int clock /* in Hz */,
1450N/A unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1450N/A{
1450N/A uint64_t freq2k;
1450N/A unsigned p, n2, r2;
1450N/A struct wrpll_rnp best = { 0, 0, 0 };
1450N/A unsigned budget;
1450N/A
1450N/A freq2k = clock / 100;
1450N/A
1450N/A budget = wrpll_get_budget_for_freq(clock);
1450N/A
1450N/A /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1450N/A * and directly pass the LC PLL to it. */
1450N/A if (freq2k == 5400000) {
1450N/A *n2_out = 2;
1450N/A *p_out = 1;
1450N/A *r2_out = 2;
1450N/A return;
1450N/A }
1450N/A
1450N/A /*
1450N/A * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1450N/A * the WR PLL.
1450N/A *
1450N/A * We want R so that REF_MIN <= Ref <= REF_MAX.
1450N/A * Injecting R2 = 2 * R gives:
1450N/A * REF_MAX * r2 > LC_FREQ * 2 and
1450N/A * REF_MIN * r2 < LC_FREQ * 2
1450N/A *
1450N/A * Which means the desired boundaries for r2 are:
1450N/A * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1450N/A *
1450N/A */
1450N/A for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1450N/A r2 <= LC_FREQ * 2 / REF_MIN;
1450N/A r2++) {
1450N/A
1450N/A /*
1450N/A * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1450N/A *
1450N/A * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1450N/A * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1450N/A * VCO_MAX * r2 > n2 * LC_FREQ and
1450N/A * VCO_MIN * r2 < n2 * LC_FREQ)
1450N/A *
1450N/A * Which means the desired boundaries for n2 are:
1450N/A * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1450N/A */
1450N/A for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1450N/A n2 <= VCO_MAX * r2 / LC_FREQ;
1450N/A n2++) {
1450N/A
1450N/A for (p = P_MIN; p <= P_MAX; p += P_INC)
1450N/A wrpll_update_rnp(freq2k, budget,
1450N/A r2, n2, p, &best);
1450N/A }
1450N/A }
1450N/A
1450N/A *n2_out = best.n2;
1450N/A *p_out = best.p;
1450N/A *r2_out = best.r2;
1450N/A
1450N/A DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
1450N/A clock, *p_out, *n2_out, *r2_out);
1450N/A}
1450N/A
1450N/Abool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
1450N/A{
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1450N/A struct drm_encoder *encoder = &intel_encoder->base;
1450N/A struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1450N/A struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
1450N/A int type = intel_encoder->type;
1450N/A enum pipe pipe = intel_crtc->pipe;
1450N/A uint32_t reg, val;
1450N/A int clock = intel_crtc->config.port_clock;
1450N/A
1450N/A /* TODO: reuse PLLs when possible (compare values) */
1450N/A
1450N/A intel_ddi_put_crtc_pll(crtc);
1450N/A
1450N/A if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A
1450N/A switch (intel_dp->link_bw) {
1450N/A case DP_LINK_BW_1_62:
1450N/A intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1450N/A break;
1450N/A case DP_LINK_BW_2_7:
1450N/A intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1450N/A break;
1450N/A case DP_LINK_BW_5_4:
1450N/A intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1450N/A break;
1450N/A default:
1450N/A DRM_ERROR("Link bandwidth %d unsupported\n",
1450N/A intel_dp->link_bw);
1450N/A return false;
1450N/A }
1450N/A
1450N/A /* We don't need to turn any PLL on because we'll use LCPLL. */
1450N/A return true;
1450N/A
1450N/A } else if (type == INTEL_OUTPUT_HDMI) {
1450N/A unsigned p, n2, r2;
1450N/A
1450N/A if (plls->wrpll1_refcount == 0) {
1450N/A DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A plls->wrpll1_refcount++;
1450N/A reg = WRPLL_CTL1;
1450N/A intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
1450N/A } else if (plls->wrpll2_refcount == 0) {
1450N/A DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A plls->wrpll2_refcount++;
1450N/A reg = WRPLL_CTL2;
1450N/A intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
1450N/A } else {
1450N/A DRM_ERROR("No WRPLLs available!\n");
1450N/A return false;
1450N/A }
1450N/A
1450N/A if(I915_READ(reg) & WRPLL_PLL_ENABLE)
1450N/A DRM_ERROR("WRPLL already enabled\n");
1450N/A
1450N/A intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1450N/A
1450N/A val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
1450N/A WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1450N/A WRPLL_DIVIDER_POST(p);
1450N/A
1450N/A } else if (type == INTEL_OUTPUT_ANALOG) {
1450N/A if (plls->spll_refcount == 0) {
1450N/A DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
1450N/A pipe_name(pipe));
1450N/A plls->spll_refcount++;
1450N/A reg = SPLL_CTL;
1450N/A intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
1450N/A } else {
1450N/A DRM_ERROR("SPLL already in use\n");
1450N/A return false;
1450N/A }
1450N/A
1450N/A if(I915_READ(reg) & SPLL_PLL_ENABLE)
1450N/A DRM_ERROR("SPLL already enabled\n");
1450N/A
1450N/A val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
1450N/A
1450N/A } else {
1450N/A DRM_ERROR("Invalid DDI encoder type %d\n", type);
1450N/A BUG_ON(1);
1450N/A return false;
1450N/A }
1450N/A
1450N/A I915_WRITE(reg, val);
1450N/A udelay(20);
1450N/A
1450N/A return true;
1450N/A}
1450N/A
1450N/Avoid intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1450N/A enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1450N/A int type = intel_encoder->type;
1450N/A uint32_t temp;
1450N/A
1450N/A if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1450N/A
1450N/A temp = TRANS_MSA_SYNC_CLK;
1450N/A switch (intel_crtc->config.pipe_bpp) {
1450N/A case 18:
1450N/A temp |= TRANS_MSA_6_BPC;
1450N/A break;
1450N/A case 24:
1450N/A temp |= TRANS_MSA_8_BPC;
1450N/A break;
1450N/A case 30:
1450N/A temp |= TRANS_MSA_10_BPC;
1450N/A break;
1450N/A case 36:
1450N/A temp |= TRANS_MSA_12_BPC;
1450N/A break;
1450N/A default:
1450N/A BUG_ON(1);
1450N/A }
1450N/A I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1450N/A }
1450N/A}
1450N/A
1450N/Avoid intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1450N/A{
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1450N/A struct drm_encoder *encoder = &intel_encoder->base;
1450N/A struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1450N/A enum pipe pipe = intel_crtc->pipe;
1450N/A enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1450N/A enum port port = intel_ddi_get_encoder_port(intel_encoder);
1450N/A int type = intel_encoder->type;
1450N/A uint32_t temp;
1450N/A
1450N/A /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1450N/A temp = TRANS_DDI_FUNC_ENABLE;
1450N/A temp |= TRANS_DDI_SELECT_PORT(port);
1450N/A
1450N/A switch (intel_crtc->config.pipe_bpp) {
1450N/A case 18:
1450N/A temp |= TRANS_DDI_BPC_6;
1450N/A break;
1450N/A case 24:
1450N/A temp |= TRANS_DDI_BPC_8;
1450N/A break;
1450N/A case 30:
1450N/A temp |= TRANS_DDI_BPC_10;
1450N/A break;
1450N/A case 36:
1450N/A temp |= TRANS_DDI_BPC_12;
1450N/A break;
1450N/A default:
1450N/A BUG_ON(1);
1450N/A }
1450N/A
1450N/A if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
1450N/A temp |= TRANS_DDI_PVSYNC;
1450N/A if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
1450N/A temp |= TRANS_DDI_PHSYNC;
1450N/A
1450N/A if (cpu_transcoder == TRANSCODER_EDP) {
1450N/A switch (pipe) {
1450N/A case PIPE_A:
1450N/A /* Can only use the always-on power well for eDP when
1450N/A * not using the panel fitter, and when not using motion
1450N/A * blur mitigation (which we don't support). */
1450N/A if (intel_crtc->config.pch_pfit.size)
1450N/A temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1450N/A else
1450N/A temp |= TRANS_DDI_EDP_INPUT_A_ON;
1450N/A break;
1450N/A case PIPE_B:
1450N/A temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1450N/A break;
1450N/A case PIPE_C:
1450N/A temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1450N/A break;
1450N/A default:
1450N/A BUG();
1450N/A break;
1450N/A }
1450N/A }
1450N/A
1450N/A if (type == INTEL_OUTPUT_HDMI) {
1450N/A struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1450N/A
1450N/A if (intel_hdmi->has_hdmi_sink)
1450N/A temp |= TRANS_DDI_MODE_SELECT_HDMI;
1450N/A else
1450N/A temp |= TRANS_DDI_MODE_SELECT_DVI;
1450N/A
1450N/A } else if (type == INTEL_OUTPUT_ANALOG) {
1450N/A temp |= TRANS_DDI_MODE_SELECT_FDI;
1450N/A temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1450N/A } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1450N/A type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A
1450N/A temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1450N/A
1450N/A temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1450N/A } else {
1450N/A DRM_ERROR("Invalid encoder type %d for pipe %c\n",
1450N/A intel_encoder->type, pipe_name(pipe));
1450N/A BUG_ON(1);
1450N/A }
1450N/A
1450N/A I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1450N/A}
1450N/A
1450N/Avoid intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1450N/A enum transcoder cpu_transcoder)
1450N/A{
1450N/A uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1450N/A uint32_t val = I915_READ(reg);
1450N/A
1450N/A val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1450N/A val |= TRANS_DDI_PORT_NONE;
1450N/A I915_WRITE(reg, val);
1450N/A}
1450N/A
1450N/Abool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1450N/A{
1450N/A struct drm_device *dev = intel_connector->base.dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct intel_encoder *intel_encoder = intel_connector->encoder;
1450N/A int type = intel_connector->base.connector_type;
1450N/A enum port port = intel_ddi_get_encoder_port(intel_encoder);
1450N/A enum pipe pipe = 0;
1450N/A enum transcoder cpu_transcoder;
1450N/A uint32_t tmp;
1450N/A
1450N/A if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1450N/A return false;
1450N/A
1450N/A if (port == PORT_A)
1450N/A cpu_transcoder = TRANSCODER_EDP;
1450N/A else
1450N/A cpu_transcoder = (enum transcoder)pipe;
1450N/A
1450N/A tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1450N/A
1450N/A switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1450N/A case TRANS_DDI_MODE_SELECT_HDMI:
1450N/A case TRANS_DDI_MODE_SELECT_DVI:
1450N/A return (type == DRM_MODE_CONNECTOR_HDMIA);
1450N/A
1450N/A case TRANS_DDI_MODE_SELECT_DP_SST:
1450N/A if (type == DRM_MODE_CONNECTOR_eDP)
1450N/A return true;
1450N/A case TRANS_DDI_MODE_SELECT_DP_MST:
1450N/A return (type == DRM_MODE_CONNECTOR_DisplayPort);
1450N/A
1450N/A case TRANS_DDI_MODE_SELECT_FDI:
1450N/A return (type == DRM_MODE_CONNECTOR_VGA);
1450N/A
1450N/A default:
1450N/A return false;
1450N/A }
1450N/A}
1450N/A
1450N/Abool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1450N/A enum pipe *pipe)
1450N/A{
1450N/A struct drm_device *dev = encoder->base.dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A enum port port = intel_ddi_get_encoder_port(encoder);
1450N/A u32 tmp;
1450N/A int i;
1450N/A
1450N/A tmp = I915_READ(DDI_BUF_CTL(port));
1450N/A
1450N/A if (!(tmp & DDI_BUF_CTL_ENABLE))
1450N/A return false;
1450N/A
1450N/A if (port == PORT_A) {
1450N/A tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1450N/A
1450N/A switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1450N/A case TRANS_DDI_EDP_INPUT_A_ON:
1450N/A case TRANS_DDI_EDP_INPUT_A_ONOFF:
1450N/A *pipe = PIPE_A;
1450N/A break;
1450N/A case TRANS_DDI_EDP_INPUT_B_ONOFF:
1450N/A *pipe = PIPE_B;
1450N/A break;
1450N/A case TRANS_DDI_EDP_INPUT_C_ONOFF:
1450N/A *pipe = PIPE_C;
1450N/A break;
1450N/A }
1450N/A
1450N/A return true;
1450N/A } else {
1450N/A for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1450N/A tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1450N/A
1450N/A if ((tmp & TRANS_DDI_PORT_MASK)
1450N/A == TRANS_DDI_SELECT_PORT(port)) {
1450N/A *pipe = i;
1450N/A return true;
1450N/A }
1450N/A }
1450N/A }
1450N/A
1450N/A DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1450N/A
1450N/A return false;
1450N/A}
1450N/A
1450N/Astatic uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1450N/A enum pipe pipe)
1450N/A{
1450N/A uint32_t temp, ret;
1450N/A enum port port = I915_MAX_PORTS;
1450N/A enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1450N/A pipe);
1450N/A int i;
1450N/A
1450N/A if (cpu_transcoder == TRANSCODER_EDP) {
1450N/A port = PORT_A;
1450N/A } else {
1450N/A temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1450N/A temp &= TRANS_DDI_PORT_MASK;
1450N/A
1450N/A for (i = PORT_B; i <= PORT_E; i++)
1450N/A if (temp == TRANS_DDI_SELECT_PORT(i))
1450N/A port = i;
1450N/A }
1450N/A
1450N/A if (port == I915_MAX_PORTS) {
1450N/A DRM_ERROR("Pipe %c enabled on an unknown port\n",
1450N/A pipe_name(pipe));
1450N/A ret = PORT_CLK_SEL_NONE;
1450N/A } else {
1450N/A ret = I915_READ(PORT_CLK_SEL(port));
1450N/A DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1450N/A "0x%08x\n", pipe_name(pipe), port_name(port),
1450N/A ret);
1450N/A }
1450N/A
1450N/A return ret;
1450N/A}
1450N/A
1450N/Avoid intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A enum pipe pipe;
1450N/A struct intel_crtc *intel_crtc;
1450N/A
1450N/A for_each_pipe(pipe) {
1450N/A intel_crtc =
1450N/A to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1450N/A
1450N/A if (!intel_crtc->active)
1450N/A continue;
1450N/A
1450N/A intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1450N/A pipe);
1450N/A
1450N/A switch (intel_crtc->ddi_pll_sel) {
1450N/A case PORT_CLK_SEL_SPLL:
1450N/A dev_priv->ddi_plls.spll_refcount++;
1450N/A break;
1450N/A case PORT_CLK_SEL_WRPLL1:
1450N/A dev_priv->ddi_plls.wrpll1_refcount++;
1450N/A break;
1450N/A case PORT_CLK_SEL_WRPLL2:
1450N/A dev_priv->ddi_plls.wrpll2_refcount++;
1450N/A break;
1450N/A }
1450N/A }
1450N/A}
1450N/A
1450N/Avoid intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1450N/A{
1450N/A struct drm_crtc *crtc = &intel_crtc->base;
1450N/A struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1450N/A struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1450N/A enum port port = intel_ddi_get_encoder_port(intel_encoder);
1450N/A enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1450N/A
1450N/A if (cpu_transcoder != TRANSCODER_EDP)
1450N/A I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1450N/A TRANS_CLK_SEL_PORT(port));
1450N/A}
1450N/A
1450N/Avoid intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1450N/A enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1450N/A
1450N/A if (cpu_transcoder != TRANSCODER_EDP)
1450N/A I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1450N/A TRANS_CLK_SEL_DISABLED);
1450N/A}
1450N/A
1450N/Astatic void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1450N/A{
1450N/A struct drm_encoder *encoder = &intel_encoder->base;
1450N/A struct drm_crtc *crtc = encoder->crtc;
1450N/A struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A enum port port = intel_ddi_get_encoder_port(intel_encoder);
1450N/A int type = intel_encoder->type;
1450N/A
1450N/A if (type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A ironlake_edp_panel_vdd_on(intel_dp);
1450N/A ironlake_edp_panel_on(intel_dp);
1450N/A ironlake_edp_panel_vdd_off(intel_dp, true);
1450N/A }
1450N/A
1450N/A WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1450N/A I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1450N/A
1450N/A if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A
1450N/A intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1450N/A intel_dp_start_link_train(intel_dp);
1450N/A intel_dp_complete_link_train(intel_dp);
1450N/A if (port != PORT_A)
1450N/A intel_dp_stop_link_train(intel_dp);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1450N/A{
1450N/A struct drm_encoder *encoder = &intel_encoder->base;
1450N/A struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1450N/A enum port port = intel_ddi_get_encoder_port(intel_encoder);
1450N/A int type = intel_encoder->type;
1450N/A uint32_t val;
1450N/A bool wait = false;
1450N/A
1450N/A val = I915_READ(DDI_BUF_CTL(port));
1450N/A if (val & DDI_BUF_CTL_ENABLE) {
1450N/A val &= ~DDI_BUF_CTL_ENABLE;
1450N/A I915_WRITE(DDI_BUF_CTL(port), val);
1450N/A wait = true;
1450N/A }
1450N/A
1450N/A val = I915_READ(DP_TP_CTL(port));
1450N/A val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1450N/A val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1450N/A I915_WRITE(DP_TP_CTL(port), val);
1450N/A
1450N/A if (wait)
1450N/A intel_wait_ddi_buf_idle(dev_priv, port);
1450N/A
1450N/A if (type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A ironlake_edp_panel_vdd_on(intel_dp);
1450N/A ironlake_edp_panel_off(intel_dp);
1450N/A }
1450N/A
1450N/A I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1450N/A}
1450N/A
1450N/Astatic void intel_enable_ddi(struct intel_encoder *intel_encoder)
1450N/A{
1450N/A struct drm_encoder *encoder = &intel_encoder->base;
1450N/A struct drm_crtc *crtc = encoder->crtc;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A int pipe = intel_crtc->pipe;
1450N/A struct drm_device *dev = encoder->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A enum port port = intel_ddi_get_encoder_port(intel_encoder);
1450N/A int type = intel_encoder->type;
1450N/A uint32_t tmp;
1450N/A
1450N/A if (type == INTEL_OUTPUT_HDMI) {
1450N/A struct intel_digital_port *intel_dig_port =
1450N/A enc_to_dig_port(encoder);
1450N/A
1450N/A /* In HDMI/DVI mode, the port width, and swing/emphasis values
1450N/A * are ignored so nothing special needs to be done besides
1450N/A * enabling the port.
1450N/A */
1450N/A I915_WRITE(DDI_BUF_CTL(port),
1450N/A intel_dig_port->saved_port_bits |
1450N/A DDI_BUF_CTL_ENABLE);
1450N/A } else if (type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A
1450N/A if (port == PORT_A)
1450N/A intel_dp_stop_link_train(intel_dp);
1450N/A
1450N/A ironlake_edp_backlight_on(intel_dp);
1450N/A }
1450N/A
1450N/A if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1450N/A tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1450N/A tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1450N/A I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1450N/A }
1450N/A}
1450N/A
1450N/Astatic void intel_disable_ddi(struct intel_encoder *intel_encoder)
1450N/A{
1450N/A struct drm_encoder *encoder = &intel_encoder->base;
1450N/A struct drm_crtc *crtc = encoder->crtc;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450N/A int pipe = intel_crtc->pipe;
1450N/A int type = intel_encoder->type;
1450N/A struct drm_device *dev = encoder->dev;
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t tmp;
1450N/A
1450N/A if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1450N/A tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1450N/A tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1450N/A (pipe * 4));
1450N/A I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1450N/A }
1450N/A
1450N/A if (type == INTEL_OUTPUT_EDP) {
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1450N/A
1450N/A ironlake_edp_backlight_off(intel_dp);
1450N/A }
1450N/A}
1450N/A
1450N/Aint intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1450N/A{
1450N/A if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1450N/A return 450000;
1450N/A else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1450N/A LCPLL_CLK_FREQ_450)
1450N/A return 450000;
1450N/A else if (IS_ULT(dev_priv->dev))
1450N/A return 337500;
1450N/A else
1450N/A return 540000;
1450N/A}
1450N/A
1450N/Avoid intel_ddi_pll_init(struct drm_device *dev)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A uint32_t val = I915_READ(LCPLL_CTL);
1450N/A
1450N/A /* The LCPLL register should be turned on by the BIOS. For now let's
1450N/A * just check its state and print errors in case something is wrong.
1450N/A * Don't even try to turn it on.
1450N/A */
1450N/A
1450N/A DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1450N/A intel_ddi_get_cdclk_freq(dev_priv));
1450N/A
1450N/A if (val & LCPLL_CD_SOURCE_FCLK)
1450N/A DRM_ERROR("CDCLK source is not LCPLL\n");
1450N/A
1450N/A if (val & LCPLL_PLL_DISABLE)
1450N/A DRM_ERROR("LCPLL is disabled\n");
1450N/A}
1450N/A
1450N/Avoid intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1450N/A{
1450N/A struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1450N/A struct intel_dp *intel_dp = &intel_dig_port->dp;
1450N/A struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1450N/A enum port port = intel_dig_port->port;
1450N/A uint32_t val;
1450N/A bool wait = false;
1450N/A
1450N/A if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1450N/A val = I915_READ(DDI_BUF_CTL(port));
1450N/A if (val & DDI_BUF_CTL_ENABLE) {
1450N/A val &= ~DDI_BUF_CTL_ENABLE;
1450N/A I915_WRITE(DDI_BUF_CTL(port), val);
1450N/A wait = true;
1450N/A }
1450N/A
1450N/A val = I915_READ(DP_TP_CTL(port));
1450N/A val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1450N/A val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1450N/A I915_WRITE(DP_TP_CTL(port), val);
1450N/A POSTING_READ(DP_TP_CTL(port));
1450N/A
1450N/A if (wait)
1450N/A intel_wait_ddi_buf_idle(dev_priv, port);
1450N/A }
1450N/A
1450N/A val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1450N/A DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1450N/A if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1450N/A val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1450N/A I915_WRITE(DP_TP_CTL(port), val);
1450N/A POSTING_READ(DP_TP_CTL(port));
1450N/A
1450N/A intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1450N/A I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1450N/A POSTING_READ(DDI_BUF_CTL(port));
1450N/A
1450N/A udelay(600);
1450N/A}
1450N/A
1450N/Avoid intel_ddi_fdi_disable(struct drm_crtc *crtc)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1450N/A struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1450N/A uint32_t val;
1450N/A
1450N/A intel_ddi_post_disable(intel_encoder);
1450N/A
1450N/A val = I915_READ(_FDI_RXA_CTL);
1450N/A val &= ~FDI_RX_ENABLE;
1450N/A I915_WRITE(_FDI_RXA_CTL, val);
1450N/A
1450N/A val = I915_READ(_FDI_RXA_MISC);
1450N/A val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1450N/A val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1450N/A I915_WRITE(_FDI_RXA_MISC, val);
1450N/A
1450N/A val = I915_READ(_FDI_RXA_CTL);
1450N/A val &= ~FDI_PCDCLK;
1450N/A I915_WRITE(_FDI_RXA_CTL, val);
1450N/A
1450N/A val = I915_READ(_FDI_RXA_CTL);
1450N/A val &= ~FDI_RX_PLL_ENABLE;
1450N/A I915_WRITE(_FDI_RXA_CTL, val);
1450N/A}
1450N/A
1450N/Astatic void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1450N/A{
1450N/A struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1450N/A int type = intel_encoder->type;
1450N/A
1450N/A if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1450N/A intel_dp_check_link_status(intel_dp);
1450N/A}
1450N/A
1450N/Astatic void intel_ddi_get_config(struct intel_encoder *encoder,
1450N/A struct intel_crtc_config *pipe_config)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1450N/A struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1450N/A enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1450N/A u32 temp, flags = 0;
1450N/A
1450N/A temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1450N/A if (temp & TRANS_DDI_PHSYNC)
1450N/A flags |= DRM_MODE_FLAG_PHSYNC;
1450N/A else
1450N/A flags |= DRM_MODE_FLAG_NHSYNC;
1450N/A if (temp & TRANS_DDI_PVSYNC)
1450N/A flags |= DRM_MODE_FLAG_PVSYNC;
1450N/A else
1450N/A flags |= DRM_MODE_FLAG_NVSYNC;
1450N/A
1450N/A pipe_config->adjusted_mode.flags |= flags;
1450N/A}
1450N/A
1450N/Astatic void intel_ddi_destroy(struct drm_encoder *encoder)
1450N/A{
1450N/A /* HDMI has nothing special to destroy, so we can go with this. */
1450N/A intel_dp_encoder_destroy(encoder);
1450N/A}
1450N/A
1450N/Astatic bool intel_ddi_compute_config(struct intel_encoder *encoder,
1450N/A struct intel_crtc_config *pipe_config)
1450N/A{
1450N/A int type = encoder->type;
1450N/A int port = intel_ddi_get_encoder_port(encoder);
1450N/A
1450N/A if(type == INTEL_OUTPUT_UNKNOWN)
1450N/A DRM_ERROR("mode_fixup() on unknown output!");
1450N/A
1450N/A if (port == PORT_A)
1450N/A pipe_config->cpu_transcoder = TRANSCODER_EDP;
1450N/A
1450N/A if (type == INTEL_OUTPUT_HDMI)
1450N/A return intel_hdmi_compute_config(encoder, pipe_config);
1450N/A else
1450N/A return intel_dp_compute_config(encoder, pipe_config);
1450N/A}
1450N/A
1450N/Astatic const struct drm_encoder_funcs intel_ddi_funcs = {
1450N/A .destroy = intel_ddi_destroy,
1450N/A};
1450N/A
1450N/Astatic const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1450N/A .mode_set = intel_ddi_mode_set,
1450N/A};
1450N/A
1450N/Avoid intel_ddi_init(struct drm_device *dev, enum port port)
1450N/A{
1450N/A struct drm_i915_private *dev_priv = dev->dev_private;
1450N/A struct intel_digital_port *intel_dig_port;
1450N/A struct intel_encoder *intel_encoder;
1450N/A struct drm_encoder *encoder;
1450N/A struct intel_connector *hdmi_connector = NULL;
1450N/A struct intel_connector *dp_connector = NULL;
1450N/A
1450N/A intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1450N/A if (!intel_dig_port)
1450N/A return;
1450N/A
1450N/A dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1450N/A if (!dp_connector) {
1450N/A kfree(intel_dig_port, sizeof(struct intel_digital_port));
1450N/A
1450N/A return;
1450N/A }
1450N/A
1450N/A intel_encoder = &intel_dig_port->base;
1450N/A encoder = &intel_encoder->base;
1450N/A
1450N/A drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1450N/A DRM_MODE_ENCODER_TMDS);
1450N/A drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1450N/A
1450N/A intel_encoder->compute_config = intel_ddi_compute_config;
1450N/A intel_encoder->enable = intel_enable_ddi;
1450N/A intel_encoder->pre_enable = intel_ddi_pre_enable;
1450N/A intel_encoder->disable = intel_disable_ddi;
1450N/A intel_encoder->post_disable = intel_ddi_post_disable;
1450N/A intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1450N/A intel_encoder->get_config = intel_ddi_get_config;
1450N/A
1450N/A intel_dig_port->port = port;
1450N/A intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1450N/A (DDI_BUF_PORT_REVERSAL |
1450N/A DDI_A_4_LANES);
1450N/A intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1450N/A
1450N/A intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1450N/A intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1450N/A intel_encoder->cloneable = false;
1450N/A intel_encoder->hot_plug = intel_ddi_hot_plug;
1450N/A
1450N/A if (!intel_dp_init_connector(intel_dig_port, dp_connector)) {
1450N/A drm_encoder_cleanup(encoder);
1450N/A kfree(intel_dig_port, sizeof(struct intel_digital_port));
1450N/A kfree(dp_connector, sizeof(struct intel_connector));
1450N/A return;
1450N/A }
1450N/A
1450N/A if (intel_encoder->type != INTEL_OUTPUT_EDP) {
1450N/A hdmi_connector = kzalloc(sizeof(struct intel_connector),
1450N/A GFP_KERNEL);
1450N/A if (!hdmi_connector) {
1450N/A return;
1450N/A }
1450N/A
1450N/A intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1450N/A intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1450N/A }
1450N/A}