551N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 551N/A * Copyright (c) 2008, 2013, Intel Corporation 919N/A * Permission is hereby granted, free of charge, to any person obtaining a 919N/A * copy of this software and associated documentation files (the "Software"), 919N/A * to deal in the Software without restriction, including without limitation 919N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 551N/A * and/or sell copies of the Software, and to permit persons to whom the 919N/A * Software is furnished to do so, subject to the following conditions: 919N/A * The above copyright notice and this permission notice (including the next 551N/A * paragraph) shall be included in all copies or substantial portions of the 919N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 919N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 919N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 919N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 919N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 551N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 551N/A * Keith Packard <keithp@keithp.com> 551N/A * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 551N/A * If a CPU or PCH DP output is attached to an eDP panel, this function 551N/A * will return true, and false otherwise. 551N/A * The units on the numbers in the next two are... bizarre. Examples will 551N/A * make it clearer; this one parallels an example in the eDP spec. 551N/A * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 551N/A * 270000 * 1 * 8 / 10 == 216000 551N/A * The actual data capacity of that configuration is 2.16Gbit/s, so the 551N/A * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 551N/A * or equivalently, kilopixels per second - so for 1680x1050R it'd be 551N/A * 119000. At 18bpp that's 2142000 kilobits per second. 551N/A * Thus the strange-looking division by 10 in intel_dp_link_required, to 551N/A * get the result in decakilobits instead of kilobits. 551N/A/* hrawclock is 1/4 the FSB frequency */ 551N/A /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 551N/A /* these two are just a guess; one of them might be right */ 551N/A DRM_ERROR(
"eDP powered off while attempting aux channel communication.");
551N/A /* dp aux is extremely sensitive to irq latency, hence request the 551N/A * lowest possible wakeup latency and so prevent the cpu from going into 551N/A /* The clock divider is based off the hrawclk, 551N/A * and would like to run at 2MHz. So, take the 551N/A * hrawclk value and divide by 2 and use that 551N/A * Note that PCH attached eDP panels should use a 125MHz input 551N/A /* Workaround for non-ULT HSW */ 551N/A /* Try to wait for any previous AUX channel activity */ 551N/A /* Must try at least 3 times according to DP spec */ 551N/A /* Load the send data into the aux channel data registers */ 551N/A /* Send the command and wait for it to complete */ 551N/A /* workaround: edp and dp doesn't work with intel_dp_aux_wait_done */ 551N/A// status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 551N/A /* Clear done status and any errors */ 551N/A /* Check for timeout or receive error. 551N/A * Timeouts occur when the sink is not connected 551N/A /* Timeouts occur when the device isn't connected, so they're 551N/A * "normal" -- don't fill the kernel log with these */ 551N/A /* Unload any bytes sent back from the other side */ 551N/A/* Write data to the aux channel in native mode */ 551N/A/* Write a single byte to the aux channel in native mode */ 551N/A/* read bytes from a native aux channel */ 551N/A /* Set up the command byte */ 551N/A /* I2C-over-AUX Reply field is only valid 551N/A * when paired with AUX ACK. 551N/A /* OSOL_i915: dp_priv->adapter.owner = THIS_MODULE; */ 551N/A /* OSOL_i915: dp_priv->adapter.dev.parent = &intel_encoder->base.kdev; */ 551N/A// } else if (IS_HASWELL(dev)) { 551N/A /* Haswell has special-purpose DP DDI clocks. */ 551N/A// } else if (IS_VALLEYVIEW(dev)) { 551N/A /* FIXME: Need to figure out optimized DP clocks for vlv. */ 551N/A "max bw %02x pixel clock %iKHz\n",
551N/A /* Walk through all bpp values. Luckily they're all nicely spaced with 2 551N/A * CEA-861-E - 5.1 Default Encoding Parameters 551N/A * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 551N/A * Check for DPCD version > 1.1 and enhanced framing support 551N/A /* For a long time we've carried around a ILK-DevA w/a for the 551N/A * 160MHz clock. If we're really unlucky, it's still required. 551N/A * There are four kinds of DP registers: 551N/A * IBX PCH and CPU are the same for almost everything, 551N/A * except that the CPU DP PLL is configured in this 551N/A * CPT PCH is quite different, having many bits moved 551N/A * to the TRANS_DP_CTL register instead. That 551N/A * configuration happens (oddly) in ironlake_pch_enable 551N/A /* Preserve the BIOS-computed detected bit. This is 551N/A * supposed to be read-only. 551N/A /* Handle DP bits in common between all three register formats */ 551N/A/* Read the current pp_control value, unlocking the register if it 551N/A * If the panel wasn't on, delay before accessing aux channel 551N/A /* fix me: crash on mode switch */ 551N/A// WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 551N/A /* Make sure sequencer is idle before allowing subsequent activity */ 551N/A * Queue the timer to fire a long 551N/A * time from now (relative to the power down delay) 551N/A * to keep the panel power up across a sequence of operations 551N/A /* ILK workaround: disable reset around power sequence */ 551N/A * If we enable the backlight right away following a panel power 551N/A * on, we may see slight flicker as the panel syncs with the eDP 551N/A * link. So delay a bit to make sure the image is solid before 551N/A * allowing it to appear. 551N/A /* We don't adjust intel_dp->DP while tearing down the link, to 551N/A * facilitate link retraining (e.g. after hotplug). Hence clear all 551N/A * enable bits here to ensure that we don't enable too much. */ 551N/A /* We can't rely on the value tracked for the DP register in 551N/A * intel_dp->DP because link_down must not change that (otherwise link 551N/A * re-training will fail. */ 551N/A/* If the sink supports it, try to set the power state appropriately */ 551N/A /* Should have a valid DPCD by this point */ 551N/A * When turning on, we need to retry for 1ms to give the sink 551N/A for (i = 0; i <
3; i++) {
551N/A /* Make sure the panel is off before trying to change the mode. But also 551N/A * ensure that we have vdd while we switch off the panel. */ 551N/A /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 551N/A /* Program Tx lane resets to default */ 551N/A /* Fix up inter-pair skew failure */ 551N/A * Native read with retry for link status and receiver capability reads for 551N/A * cases where the sink may still be asleep. 551N/A * Sinks are *supposed* to come up within 1ms from an off state, 551N/A * but we're also supposed to retry 3 times per the spec. 551N/A for (i = 0; i <
3; i++) {
551N/A * Fetch AUX CH registers 0x202 - 0x207 which contain 551N/A * link status information 551N/A "0.4V",
"0.6V",
"0.8V",
"1.2V" 551N/A "0dB",
"3.5dB",
"6dB",
"9.5dB" 551N/A "pattern 1",
"pattern 2",
"idle",
"off" 551N/A * These are source-specific values; current Intel hardware supports 551N/A * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 551N/A/* Gen6's DP voltage swing and pre-emphasis control */ 551N/A/* Gen7's DP voltage swing and pre-emphasis control */ 551N/A/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 551N/A/* Properly updates "DP" with the correct signal levels. */ 551N/A * On PORT_A we can have only eDP in SST mode. There the only reason 551N/A * we need to set idle transmission mode is to work around a HW issue 551N/A * where we enable the pipe while not in idle link-training mode. 551N/A * In this case there is requirement to wait for a minimum number of 551N/A * idle patterns to be sent. 551N/A/* Enable corresponding port and start training pattern 1 */ 551N/A /* Write the link configuration data */ 551N/A /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 551N/A /* Set training pattern 1 */ 551N/A /* Check to see if we've tried the max voltage */ 551N/A /* Check to see if we've tried the same voltage 5 times */ 551N/A /* Compute new train_set as requested by target */ 551N/A /* channel equalization */ 551N/A /* channel eq pattern */ 551N/A /* Make sure clock is still ok */ 551N/A /* Try 5 times, then try clock recovery if that fails */ 551N/A /* Compute new train_set as requested by target */ 551N/A * DDI code has a strict mode set sequence and we should try to respect 551N/A * it, otherwise we might hang the machine in many different ways. So we 551N/A * really should be disabling the port only on a complete crtc_disable 551N/A * sequence. This function is just called under two conditions on DDI 551N/A * - Link train failed while doing crtc_enable, and on this case we 551N/A * really should respect the mode set sequence and wait for a 551N/A * - Someone turned the monitor off and intel_dp_check_link_status 551N/A * called us. We don't need to disable the whole port on this case, so 551N/A * when someone turns the monitor on again, 551N/A * intel_ddi_prepare_link_retrain will take care of redoing the link 551N/A /* We don't really know why we're doing this */ 551N/A /* Hardware workaround: leaving our transcoder select 551N/A * set to transcoder B while it's off will prevent the 551N/A * corresponding HDMI output on transcoder A. 551N/A * Combine this with another hardware workaround: 551N/A * transcoder select bit can only be cleared while the 551N/A /* Changes to enable or select take place the vblank 551N/A /* We should never try to disable a port without a crtc 551N/A * attached. For paranoia keep the code around for a 551N/A// char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 551N/A return false;
/* aux transfer failed */ 551N/A hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 551N/A 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 551N/A DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 551N/A return false;
/* DPCD not present */ 551N/A return true;
/* native DP sink */ 551N/A return true;
/* no per-port downstream info */ 551N/A return false;
/* downstream port status fetch failed */ 551N/A * 2. Configure link according to Receiver Capabilities 551N/A * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 551N/A * 4. Check link status on receipt of hot-plug interrupt 551N/A /* Try to read receiver status if the link appears to be up */ 551N/A /* Now read the DPCD to see if it's actually running */ 551N/A /* Try to read the source of the interrupt */ 551N/A /* Clear interrupt source */ 551N/A/* XXX this is probably wrong for multiple downstream ports */ 551N/A /* if there's no downstream port, we're done */ 551N/A /* If we're HPD-aware, SINK_COUNT changes dynamically */ 551N/A /* If no HPD, poke DDC gently */ 551N/A /* Well we tried, say unknown for unreliable port types */ 551N/A /* Anything else is out of spec, warn and ignore */ 551N/A /* Can't disconnect eDP */ 551N/A /* Can't disconnect eDP, but you can close the lid... */ 551N/A /* use cached edid if we have one */ 551N/A /* use cached edid if we have one */ 551N/A /* We should parse the EDID data and find out if it has an audio sink 551N/A /* if eDP has no EDID, fall back to fixed mode */ 551N/A /* the eDP scaling property is not changed */ 551N/A /* Can't call is_edp() since the encoder may have been destroyed 551N/A// i2c_del_adapter(&intel_dp->adapter); 551N/A/* Return which DP Port should be selected for Transcoder DP control */ 551N/A/* check the VBT to see whether the eDP is on DP-D port */ 551N/A /* Workaround: Need to write PP_CONTROL with the unlock key as 551N/A * the very first thing. */ 551N/A /* Pull timing values out of registers */ 551N/A /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 551N/A * our hw here, which are all in 100usec. */ 551N/A spec.
t8 =
50 *
10;
/* no limit for t8, use t7 instead */ 551N/A spec.
t9 =
50 *
10;
/* no limit for t9, make it symmetric with t8 */ 551N/A /* This one is special and actually in units of 100ms, but zero 551N/A * based in the hw (so we need to add 100 ms). But the sw vbt 551N/A * table multiplies it with 1000 to make it in units of 100usec, 551N/A /* Use the max of the register settings and vbt. If both are 551N/A * unset, fall back to the spec limits. */ 551N/A /* And finally store the new values in the power sequencer. */ 551N/A /* Compute the divisor for the pp clock, simply match the Bspec 551N/A /* Haswell doesn't have any port selection bits for the panel 551N/A * power sequencer any more. */ 551N/A DRM_DEBUG_KMS(
"panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
551N/A /* Cache DPCD and EDID for edp. */ 551N/A /* if this fails, presume the device is a ghost */ 551N/A /* We now know it's not a ghost, init power sequence regs. */ 551N/A /* prefer fixed mode from EDID if available */ 551N/A /* fallback to VBT if available for eDP */ 551N/A /* Preserve the current hw state. */ 551N/A * FIXME : We need to initialize built-in panels before external panels. 551N/A * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup 551N/A default:
/* silence GCC warning */ 551N/A * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 551N/A * for DP the encoder type can be set by the caller to 551N/A * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 551N/A /* Set up the DDC bus. */ 551N/A //i2c_del_adapter(&intel_dp->adapter); 551N/A /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 551N/A * 0xd. Failure to do so will result in spurious interrupts being 551N/A * generated on the port when a cable is not attached.