1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 1450N/A * Copyright (c) 2009, 2012, Intel Corporation. 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the 1450N/A * "Software"), to deal in the Software without restriction, including 1450N/A * without limitation the rights to use, copy, modify, merge, publish, 1450N/A * distribute, sub license, and/or sell copies of the Software, and to 1450N/A * permit persons to whom the Software is furnished to do so, subject to 1450N/A * the following conditions: 1450N/A * The above copyright notice and this permission notice (including the 1450N/A * next paragraph) shall be included in all copies or substantial portions 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1450N/A * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1450N/A * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 1450N/A * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 1450N/A * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 1450N/A * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 1450N/A * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 1450N/A/* For display hotplug interrupt */ 1450N/A * @enable: true if we want to report FIFO underrun errors, false otherwise 1450N/A * This function makes us disable or enable CPU fifo underruns for a specific 1450N/A * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun 1450N/A * reporting for one pipe may also disable all the other CPU error interruts for 1450N/A * the other pipes, due to the fact that there's just one interrupt mask/enable 1450N/A * Returns the previous state of underrun reporting. 1450N/A * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 1450N/A * @enable: true if we want to report FIFO underrun errors, false otherwise 1450N/A * This function makes us disable or enable PCH fifo underruns for a specific 1450N/A * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 1450N/A * underrun reporting for one transcoder may also disable all the other PCH 1450N/A * error interruts for the other transcoders, due to the fact that there's just 1450N/A * Returns the previous state of underrun reporting. 1450N/A /* Enable the interrupt, clear any pending status */ 1450N/A * i915_pipe_enabled - check if a pipe is enabled 1450N/A * Reading certain registers when the pipe is disabled can hang the chip. 1450N/A * Use this routine to make sure the PLL is running and the pipe is active 1450N/A * before reading such registers if unsure. 1450N/A /* Locking is horribly broken here, but whatever. */ 1450N/A/* Called from drm generic code, passed a 'crtc', which 1450N/A * High & low register fields aren't synchronized, so make sure 1450N/A * we get a low value that's stable across two reads of the high 1450N/A /* No obvious pixelcount register. Only query vertical 1450N/A * scanout position from Display scan line register. 1450N/A /* Decode into vertical scanout position. Don't have 1450N/A * horizontal scanout position. 1450N/A /* Have access to pixelcount since start of frame. 1450N/A * We can split this into vertical and horizontal 1450N/A /* Test position against vblank region. */ 1450N/A /* Inside "upper part" of vblank area? Apply corrective offset: */ 1450N/A /* Get drm_crtc to timestamp: */ 1450N/A /* Helper routine in DRM core does all the work: */ 1450N/A * Handle hotplug events outside the interrupt handler proper. 1450N/A /* HPD irq before everything is fully set up. */ 1450N/A "switching from hotplug detection to polling\n",
1450N/A /* if there were no outputs to poll, poll was disabled, 1450N/A * therefore make sure it's enabled when disabling HPD on 1450N/A /* Handle RCS change request from hw */ 1450N/A * For better performance, jump directly 1450N/A * to RPe if we're below it. 1450N/A /* sysfs frequency interfaces may have snuck in while servicing the 1450N/A * ivybridge_parity_work - Workqueue called when a parity error interrupt 1450N/A * Doesn't actually do anything except notify userspace. As a consequence of 1450N/A * this event, userspace should try to remap the bad rows since statistically 1450N/A * it is likely the same row is more likely to go bad again. 1450N/A /* We must turn off DOP level clock gating to access the L3 registers. 1450N/A * In order to prevent a get/put style interface, acquire struct mutex 1450N/A * any time we access those registers. 1450N/A * IIR bits should never already be set because IMR should 1450N/A * prevent an interrupt from being shown in IIR. The warning 1450N/A * displays a case where we've unsafely cleared 1450N/A * dev_priv->rps.pm_iir. Although missing an interrupt of the same 1450N/A * type is not a problem, it displays a problem in the logic. 1450N/A * The mask bit in IMR is cleared by dev_priv->rps.work. 1450N/A/* Unlike gen6_queue_rps_work() from which this function is originally derived, 1450N/A * we must be able to deal with other PM interrupts. This is complicated because 1450N/A * of the way in which we use the masks to defer the RPS work (which for 1450N/A * posterity is necessary because of forcewake). 1450N/A /* never want to mask useful interrupts. (also posting read) */ 1450N/A /* TODO: if queue_work is slow, move it out of the spinlock */ 1450N/A * Clear the PIPE*STAT regs before the IIR 1450N/A /* Consume port. Then clear IIR or we'll miss events */ 1450N/A /* We get interrupts on unclaimed registers, so check for this before we 1450N/A * do any I915_{READ,WRITE}. */ 1450N/A /* disable master interrupt before clearing iir */ 1450N/A /* Disable south interrupts. We'll only write to SDEIIR once, so further 1450N/A * interrupts will will be stored on its back queue, and then we'll be 1450N/A * able to process them after we restore SDEIER (as soon as we restore 1450N/A * it, we'll get an interrupt if SDEIIR still has something to process 1450N/A * due to its back queue). */ 1450N/A /* On Haswell, also mask ERR_INT because we don't want to risk 1450N/A * generating "unclaimed register" interrupts from inside the interrupt 1450N/A /* clear PCH hotplug event before clear CPU irq */ 1450N/A /* disable master interrupt before clearing iir */ 1450N/A /* Disable south interrupts. We'll only write to SDEIIR once, so further 1450N/A * interrupts will will be stored on its back queue, and then we'll be 1450N/A * able to process them after we restore SDEIER (as soon as we restore 1450N/A * it, we'll get an interrupt if SDEIIR still has something to process 1450N/A * due to its back queue). */ 1450N/A /* should clear PCH hotplug event before clear CPU irq */ 1450N/A * i915_error_work_func - do process context error handling work 1450N/A * Fire an error uevent so userspace can see that a hang or error 1450N/A /* OSOL_i915: kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */ 1450N/A * Note that there's only one work item which does gpu resets, so we 1450N/A * need not worry about concurrent gpu resets potentially incrementing 1450N/A * error->reset_counter twice. We only need to take care of another 1450N/A * quick check for that is good enough: schedule_work ensures the 1450N/A * correct ordering between hang detection and this work item, and since 1450N/A * the reset in-progress bit is only ever set by code outside of this 1450N/A * work we don't need to worry about any other races. 1450N/A /* OSOL_i915: kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */ 1450N/A * After all the gem state is reset, increment the reset 1450N/A * counter and wake up everyone waiting for the reset to 1450N/A * Since unlock operations are a one-sided barrier only, 1450N/A * we need to insert a barrier here to order any seqno 1450N/A/* NB: please notice the memset */ 1450N/A /* Simply ignore tiling or any overlapping fence. 1450N/A * It's part of the error state, and this hopefully 1450N/A * captures what the GPU read. 1450N/A /* We need to copy these to an anonymous buffer as the simplest 1450N/A * method to avoid being overwritten by userspace. 1450N/A /* Currently render ring is the only HW context user */ 1450N/A * i915_capture_error_state - capture an error record for later analysis 1450N/A * Should be called when an error is detected (either a hang or an error 1450N/A * interrupt) to capture error state from the time of the error. Fills 1450N/A * out a structure which becomes available in debugfs for user level tools 1450N/A /* Account for pipe specific data like PIPE*STAT */ 1450N/A /* Record buffers on the active and pinned lists. */ 1450N/A /* pipestat has already been acked */ 1450N/A * some errors might have become stuck, 1450N/A * i915_handle_error - handle an error interrupt 1450N/A * Do some basic checking of regsiter state at error interrupt time and 1450N/A * dump it to the syslog. Also call i915_capture_error_state() to make 1450N/A * sure we get a record and make it available in debugfs. Fire a uevent 1450N/A * so userspace knows something bad happened (should trigger collection 1450N/A * Wakeup waiting processes so they don't hang 1450N/A /* Ignore early vblank irqs */ 1450N/A /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 1450N/A /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1450N/A/* Called from drm generic code, passed 'crtc' which 1450N/A /* maintain vblank delivery even in deep C-states */ 1450N/A/* Called from drm generic code, passed 'crtc' which 1450N/A /* ACTHD is likely pointing to the dword after the actual command, 1450N/A * so scan backwards until we find the MBOX. 1450N/A /* cursory check for an unkickable deadlock */ 1450N/A /* Is the chip hanging on a WAIT_FOR_EVENT? 1450N/A * If so we can simply poke the RB_WAIT bit 1450N/A * and break the hang. This should work on 1450N/A * all but the second generation chipsets. 1450N/A * This is called when the chip hasn't reported back with completed 1450N/A * batchbuffers in a long time. The first time this is called we simply record 1450N/A * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1450N/A * Further, acthd is inspected to see if the ring is stuck. On stuck case 1450N/A * we kick the ring. If we see no progress on three subsequent calls 1450N/A * again, we assume the chip is wedged and try to fix it. 1450N/A /* Issue a wake-up to catch stuck h/w. */ 1450N/A /* We always increment the hangcheck score 1450N/A * if the ring is busy and still processing 1450N/A * the same request, so that no single request 1450N/A * can run indefinitely (such as a chain of 1450N/A * batches). The only time we do not increment 1450N/A * the hangcheck score on this ring, if this 1450N/A * ring is in a legitimate wait for another 1450N/A * ring. In that case the waiting ring is a 1450N/A * victim and we want to be sure we catch the 1450N/A * right culprit. Then every time we do kick 1450N/A * the ring, add a small increment to the 1450N/A * score so that we can catch a batch that is 1450N/A * being repeatedly kicked and so responsible 1450N/A * for stalling the machine. 1450N/A /* Gradually reduce the count so that we catch DoS 1450N/A * attempts across multiple batches. 1450N/A /* Reset timer case chip hangs without another request 1450N/A * SDEIER is also touched by the interrupt handler to work around missed 1450N/A * PCH interrupts. Hence we can't update it after the interrupt handler 1450N/A * is enabled - instead we unconditionally enable all PCH interrupt 1450N/A * sources here, but then only unmask them as needed with SDEIMR. 1450N/A * Enable digital hotplug on the PCH, and configure the DP short pulse 1450N/A * duration to 2ms (which is the minimum in the Display Port spec) 1450N/A * This register is the same on all known PCH chips. 1450N/A /* enable kind of interrupts always enabled */ 1450N/A /* should always can generate irq */ 1450N/A /* Enable PCU event interrupts 1450N/A * spinlocking not required here for correctness since interrupt 1450N/A * setup is guaranteed to run in single-threaded context. But we 1450N/A * need it to make the assert_spin_locked happy. */ 1450N/A /* enable kind of interrupts always enabled */ 1450N/A /* should always can generate irq */ 1450N/A * make sure to set a known state for only the non-RPS bits. 1450N/A * The RMW is extra paranoia since this should be called after being set 1450N/A * to a known state in preinstall. 1450N/A * toggle them based on usage. 1450N/A /* ack & enable invalid PTE error interrupts */ 1450N/A#
if 0
/* FIXME: add support to irq handler for checking these bits */ 1450N/A /* Unmask the interrupts that we always want on. */ 1450N/A * Returns true when a page flip has completed. 1450N/A /* We detect FlipDone by looking for the change in PendingFlip from '1' 1450N/A * to '0' on the following vblank, i.e. IIR has the Pendingflip 1450N/A * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 1450N/A * the flip is completed (no longer pending). Since this doesn't raise 1450N/A * an interrupt per se, we watch for the change at vblank. 1450N/A /* Can't rely on pipestat interrupt bit in iir as it might 1450N/A * have been cleared after the pipestat interrupt was received. 1450N/A * It doesn't set the bit in iir again, but it still produces 1450N/A * interrupts (for non-MSI). 1450N/A * Clear the PIPE*STAT regs before the IIR 1450N/A /* Clear enable bits; then clear status bits */ 1450N/A /* Unmask the interrupts that we always want on. */ 1450N/A * Returns true when a page flip has completed. 1450N/A /* We detect FlipDone by looking for the change in PendingFlip from '1' 1450N/A * to '0' on the following vblank, i.e. IIR has the Pendingflip 1450N/A * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 1450N/A * the flip is completed (no longer pending). Since this doesn't raise 1450N/A * an interrupt per se, we watch for the change at vblank. 1450N/A /* Can't rely on pipestat interrupt bit in iir as it might 1450N/A * have been cleared after the pipestat interrupt was received. 1450N/A * It doesn't set the bit in iir again, but it still produces 1450N/A * interrupts (for non-MSI). 1450N/A /* Clear the PIPE*STAT regs before the IIR */ 1450N/A /* Consume port. Then clear IIR or we'll miss events */ 1450N/A /* With MSI, interrupts are only generated when iir 1450N/A * transitions from zero to nonzero. If another bit got 1450N/A * set while we were handling the existing iir bits, then 1450N/A * we would never get another interrupt. 1450N/A * This is fine on non-MSI as well, as if we hit this path 1450N/A * we avoid exiting the interrupt handler only to generate 1450N/A * Note that for MSI this could cause a stray interrupt report 1450N/A * if an interrupt landed in the time between writing IIR and 1450N/A * the posting read. This should be rare enough to never 1450N/A * trigger the 99% of 100,000 interrupts test for disabling 1450N/A /* Clear enable bits; then clear status bits */ 1450N/A /* Unmask the interrupts that we always want on. */ 1450N/A * Enable some error detection, note the instruction error mask 1450N/A * bit is reserved, so we leave it masked. 1450N/A /* Note HDMI and DP share hotplug bits */ 1450N/A /* enable bits are the same for all generations */ 1450N/A /* Programming the CRT detection parameters tends 1450N/A to generate a spurious hotplug event about three 1450N/A seconds later. So just do it once. 1450N/A /* Ignore TV since it's buggy */ 1450N/A /* Can't rely on pipestat interrupt bit in iir as it might 1450N/A * have been cleared after the pipestat interrupt was received. 1450N/A * It doesn't set the bit in iir again, but it still produces 1450N/A * interrupts (for non-MSI). 1450N/A * Clear the PIPE*STAT regs before the IIR 1450N/A /* Consume port. Then clear IIR or we'll miss events */ 1450N/A /* With MSI, interrupts are only generated when iir 1450N/A * transitions from zero to nonzero. If another bit got 1450N/A * set while we were handling the existing iir bits, then 1450N/A * we would never get another interrupt. 1450N/A * This is fine on non-MSI as well, as if we hit this path 1450N/A * we avoid exiting the interrupt handler only to generate 1450N/A * Note that for MSI this could cause a stray interrupt report 1450N/A * if an interrupt landed in the time between writing IIR and 1450N/A * the posting read. This should be rare enough to never 1450N/A * trigger the 99% of 100,000 interrupts test for disabling 1450N/A /* Interrupt setup is already guaranteed to be single-threaded, this is 1450N/A * just to make the assert_spin_locked checks happy. */