Lines Matching refs:I915_READ
154 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
236 temp = I915_READ(_FDI_RXA_MISC);
244 temp = I915_READ(DP_TP_STATUS(PORT_E));
258 temp = I915_READ(DDI_BUF_CTL(PORT_E));
264 temp = I915_READ(DP_TP_CTL(PORT_E));
277 temp = I915_READ(_FDI_RXA_MISC);
376 val = I915_READ(SPLL_CTL);
386 val = I915_READ(WRPLL_CTL1);
396 val = I915_READ(WRPLL_CTL2);
692 if(I915_READ(reg) & WRPLL_PLL_ENABLE)
713 if(I915_READ(reg) & SPLL_PLL_ENABLE)
854 uint32_t val = I915_READ(reg);
880 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
910 tmp = I915_READ(DDI_BUF_CTL(port));
916 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
934 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
961 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
974 ret = I915_READ(PORT_CLK_SEL(port));
1075 val = I915_READ(DDI_BUF_CTL(port));
1082 val = I915_READ(DP_TP_CTL(port));
1132 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1150 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1165 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1167 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1179 uint32_t val = I915_READ(LCPLL_CTL);
1205 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1206 val = I915_READ(DDI_BUF_CTL(port));
1213 val = I915_READ(DP_TP_CTL(port));
1245 val = I915_READ(_FDI_RXA_CTL);
1249 val = I915_READ(_FDI_RXA_MISC);
1254 val = I915_READ(_FDI_RXA_CTL);
1258 val = I915_READ(_FDI_RXA_CTL);
1280 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1361 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &