1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright 2006 Dave Airlie <airlied@linux.ie> 1450N/A * Copyright (c) 2006-2009, 2013, Intel Corporation 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 1450N/A * DEALINGS IN THE SOFTWARE. 1450N/A * Eric Anholt <eric@anholt.net> 1450N/A * Jesse Barnes <jesse.barnes@intel.com> 1450N/A /* Write every possible data byte to force correct ECC calculation. */ 1450N/A /* Write every possible data byte to force correct ECC calculation. */ 1450N/A /* The DIP control register spec says that we need to update the AVI 1450N/A * infoframe without clearing its enable bit */ 1450N/A /* Write every possible data byte to force correct ECC calculation. */ 1450N/A /* Write every possible data byte to force correct ECC calculation. */ 1450N/A /* Write every possible data byte to force correct ECC calculation. */ 1450N/A /* If the registers were not initialized yet, they might be zeroes, 1450N/A * which means we're selecting the AVI DIP and we're setting its 1450N/A * frequency to once. This seems to really confuse the HW and make 1450N/A * things stop working (the register spec says the AVI always needs to 1450N/A * be sent every VSync). So here we avoid writing to the register more 1450N/A * than we need and also explicitly select the AVI DIP and explicitly 1450N/A * set its frequency to every VSync. Avoiding to write it twice seems to 1450N/A * be enough to solve the problem, but being defensive shouldn't hurt us 1450N/A /* See the big comment in g4x_set_infoframes() */ 1450N/A /* See the big comment in g4x_set_infoframes() */ 1450N/A /* Set both together, unset both together: see the spec. */ 1450N/A /* See the big comment in g4x_set_infoframes() */ 1450N/A /* HW workaround for IBX, we need to move the port to transcoder A 1450N/A * before disabling it, so restore the transcoder select bit here. */ 1450N/A /* HW workaround, need to toggle enable bit off and on for 12bpc, but 1450N/A * we do this anyway which shows more stable in testing. 1450N/A /* HW workaround, need to write this twice for issue that may result 1450N/A * in first write getting masked. 1450N/A /* HW workaround for IBX, we need to move the port to transcoder A 1450N/A /* Again we need to write this twice. */ 1450N/A /* Transcoder selection bits only update 1450N/A * effectively on vblank. */ 1450N/A /* HW workaround, need to toggle enable bit off and on for 12bpc, but 1450N/A * we do this anyway which shows more stable in testing. 1450N/A /* HW workaround, need to write this twice for issue that may result 1450N/A * in first write getting masked. 1450N/A /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1450N/A * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1450N/A * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1450N/A * outputs. We also need to check that the higher clock still fits 1450N/A /* Need to adjust the port link by 1.5x for 12bpc. */ 1450N/A /* We should parse the EDID data and find out if it's an HDMI sink so 1450N/A /* Enable clock channels for this port */ 1450N/A /* Program Tx lane resets to default */ 1450N/A /* Fix up inter-pair skew failure */ 1450N/A /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1450N/A /* Internal port only for eDP. */ 1450N/A// drm_sysfs_connector_add(connector); 1450N/A /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1450N/A * 0xd. Failure to do so will result in spurious interrupts being 1450N/A * generated on the port when a cable is not attached.