749N/A/*
749N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
749N/A */
749N/A
749N/A/*
749N/A * i915_drv.c -- Intel i915 driver -*- linux-c -*-
749N/A * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
749N/A */
749N/A
749N/A/*
749N/A * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
749N/A * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
749N/A * Copyright (c) 2009, 2013, Intel Corporation.
749N/A * All Rights Reserved.
749N/A *
749N/A * Permission is hereby granted, free of charge, to any person obtaining a
749N/A * copy of this software and associated documentation files (the "Software"),
749N/A * to deal in the Software without restriction, including without limitation
749N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
749N/A * and/or sell copies of the Software, and to permit persons to whom the
749N/A * Software is furnished to do so, subject to the following conditions:
749N/A *
749N/A * The above copyright notice and this permission notice (including the next
749N/A * paragraph) shall be included in all copies or substantial portions of the
749N/A * Software.
749N/A *
749N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
749N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
749N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
749N/A * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
749N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
749N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
749N/A * OTHER DEALINGS IN THE SOFTWARE.
749N/A *
749N/A * Authors:
749N/A * Gareth Hughes <gareth@valinux.com>
749N/A *
749N/A */
749N/A
749N/A/*
749N/A * I915 DRM Driver for Solaris
749N/A *
749N/A * This driver provides the hardware 3D acceleration support for Intel
749N/A * integrated video devices (e.g. i8xx/i915/i945 series chipsets), under the
749N/A * DRI (Direct Rendering Infrastructure). DRM (Direct Rendering Manager) here
749N/A * means the kernel device driver in DRI.
749N/A *
749N/A * I915 driver is a device dependent driver only, it depends on a misc module
749N/A * named drm for generic DRM operations.
749N/A */
749N/A
749N/A#include "drmP.h"
749N/A#include "i915_drm.h"
749N/A#include "i915_drv.h"
749N/A#include "drm_crtc_helper.h"
749N/A#include "intel_drv.h"
749N/A
749N/Astatic int i915_modeset = -1;
749N/Aunsigned int i915_fbpercrtc = 0;
749N/Aint i915_panel_ignore_lid = 1;
749N/Aunsigned int i915_powersave = 1;
749N/A
749N/Aint i915_semaphores = -1;
749N/A
749N/Aint i915_enable_rc6 = 0;
749N/Aint i915_enable_fbc = -1;
749N/A
749N/Aunsigned int i915_lvds_downclock = 0;
749N/Aint i915_lvds_channel_mode;
749N/A
749N/Aint i915_panel_use_ssc = -1;
749N/Aint i915_vbt_sdvo_panel_type = -1;
749N/A
749N/Abool i915_try_reset = false;
749N/Abool i915_enable_hangcheck = true;
749N/Aint i915_enable_ppgtt = -1;
749N/A
749N/Aint i915_disable_power_well = 1;
749N/Aint i915_enable_ips = 1;
749N/A
749N/Astatic void *i915_statep;
749N/A
749N/Astatic int i915_info(dev_info_t *, ddi_info_cmd_t, void *, void **);
749N/Astatic int i915_attach(dev_info_t *, ddi_attach_cmd_t);
749N/Astatic int i915_detach(dev_info_t *, ddi_detach_cmd_t);
749N/Astatic int i915_quiesce(dev_info_t *);
749N/A
749N/Aextern struct cb_ops drm_cb_ops;
749N/Aextern int intel_agp_enabled;
749N/A
749N/Astatic struct dev_ops i915_dev_ops = {
749N/A DEVO_REV, /* devo_rev */
749N/A 0, /* devo_refcnt */
749N/A i915_info, /* devo_getinfo */
749N/A nulldev, /* devo_identify */
749N/A nulldev, /* devo_probe */
749N/A i915_attach, /* devo_attach */
749N/A i915_detach, /* devo_detach */
749N/A nodev, /* devo_reset */
749N/A &drm_cb_ops, /* devo_cb_ops */
749N/A NULL, /* devo_bus_ops */
749N/A NULL, /* power */
749N/A i915_quiesce, /* devo_quiesce */
749N/A};
749N/A
749N/Astatic struct modldrv modldrv = {
749N/A &mod_driverops, /* drv_modops */
749N/A "I915 DRM driver", /* drv_linkinfo */
749N/A &i915_dev_ops, /* drv_dev_ops */
749N/A};
749N/A
749N/Astatic struct modlinkage modlinkage = {
749N/A MODREV_1, (void *) &modldrv, NULL
749N/A};
749N/A
749N/A#define INTEL_VGA_DEVICE(id, info) { \
749N/A .vendor = 0x8086, \
749N/A .device = id, \
749N/A .driver_data = (unsigned long) info }
749N/A
749N/Astatic const struct intel_device_info intel_i830_info = {
749N/A .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_845g_info = {
749N/A .gen = 2, .num_pipes = 1,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_i85x_info = {
749N/A .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
749N/A .cursor_needs_physical = 1,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_i865g_info = {
749N/A .gen = 2, .num_pipes = 1,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_i915g_info = {
749N/A .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A};
749N/Astatic const struct intel_device_info intel_i915gm_info = {
749N/A .gen = 3, .is_mobile = 1, .num_pipes = 2,
749N/A .cursor_needs_physical = 1,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A .supports_tv = 1,
749N/A};
749N/Astatic const struct intel_device_info intel_i945g_info = {
749N/A .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A};
749N/Astatic const struct intel_device_info intel_i945gm_info = {
749N/A .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
749N/A .has_hotplug = 1, .cursor_needs_physical = 1,
749N/A .has_overlay = 1, .overlay_needs_physical = 1,
749N/A .supports_tv = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_i965g_info = {
749N/A .gen = 4, .is_broadwater = 1, .num_pipes = 2,
749N/A .has_hotplug = 1,
749N/A .has_overlay = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_i965gm_info = {
749N/A .gen = 4, .is_crestline = 1, .num_pipes = 2,
749N/A .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
749N/A .has_overlay = 1,
749N/A .supports_tv = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_g33_info = {
749N/A .gen = 3, .is_g33 = 1, .num_pipes = 2,
749N/A .need_gfx_hws = 1, .has_hotplug = 1,
749N/A .has_overlay = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_g45_info = {
749N/A .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
749N/A .has_pipe_cxsr = 1, .has_hotplug = 1,
749N/A .has_bsd_ring = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_gm45_info = {
749N/A .gen = 4, .is_g4x = 1, .num_pipes = 2,
749N/A .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
749N/A .has_pipe_cxsr = 1, .has_hotplug = 1,
749N/A .supports_tv = 1,
749N/A .has_bsd_ring = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_pineview_info = {
749N/A .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
749N/A .need_gfx_hws = 1, .has_hotplug = 1,
749N/A .has_overlay = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_ironlake_d_info = {
749N/A .gen = 5, .num_pipes = 2,
749N/A .need_gfx_hws = 1, .has_hotplug = 1,
749N/A .has_bsd_ring = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_ironlake_m_info = {
749N/A .gen = 5, .is_mobile = 1, .num_pipes = 2,
749N/A .need_gfx_hws = 1, .has_hotplug = 1,
749N/A .has_fbc = 1,
749N/A .has_bsd_ring = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_sandybridge_d_info = {
749N/A .gen = 6, .num_pipes = 2,
749N/A .need_gfx_hws = 1, .has_hotplug = 1,
749N/A .has_bsd_ring = 1,
749N/A .has_blt_ring = 1,
749N/A .has_llc = 1,
749N/A .has_force_wake = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_sandybridge_m_info = {
749N/A .gen = 6, .is_mobile = 1, .num_pipes = 2,
749N/A .need_gfx_hws = 1, .has_hotplug = 1,
749N/A .has_fbc = 1,
749N/A .has_bsd_ring = 1,
749N/A .has_blt_ring = 1,
749N/A .has_llc = 1,
749N/A .has_force_wake = 1,
749N/A};
749N/A
749N/A#define GEN7_FEATURES \
749N/A .gen = 7, .num_pipes = 3, \
749N/A .need_gfx_hws = 1, .has_hotplug = 1, \
749N/A .has_bsd_ring = 1, \
749N/A .has_blt_ring = 1, \
749N/A .has_llc = 1, \
749N/A .has_force_wake = 1
749N/A
749N/Astatic const struct intel_device_info intel_ivybridge_d_info = {
749N/A GEN7_FEATURES,
749N/A .is_ivybridge = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_ivybridge_m_info = {
749N/A GEN7_FEATURES,
749N/A .is_ivybridge = 1,
749N/A .is_mobile = 1,
749N/A .has_fbc = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_ivybridge_q_info = {
749N/A GEN7_FEATURES,
749N/A .is_ivybridge = 1,
749N/A .num_pipes = 0, /* legal, last one wins */
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_valleyview_m_info = {
749N/A GEN7_FEATURES,
749N/A .is_mobile = 1,
749N/A .num_pipes = 2,
749N/A .is_valleyview = 1,
749N/A .display_mmio_offset = VLV_DISPLAY_BASE,
749N/A .has_llc = 0, /* legal, last one wins */
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_valleyview_d_info = {
749N/A GEN7_FEATURES,
749N/A .num_pipes = 2,
749N/A .is_valleyview = 1,
749N/A .display_mmio_offset = VLV_DISPLAY_BASE,
749N/A .has_llc = 0, /* legal, last one wins */
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_haswell_d_info = {
749N/A GEN7_FEATURES,
749N/A .is_haswell = 1,
749N/A .has_ddi = 1,
749N/A .has_fpga_dbg = 1,
749N/A .has_vebox_ring = 1,
749N/A};
749N/A
749N/Astatic const struct intel_device_info intel_haswell_m_info = {
749N/A GEN7_FEATURES,
749N/A .is_haswell = 1,
749N/A .is_mobile = 1,
749N/A .has_ddi = 1,
749N/A .has_fpga_dbg = 1,
749N/A .has_fbc = 1,
749N/A .has_vebox_ring = 1,
749N/A};
749N/Astatic struct drm_pci_id_list pciidlist[] = {
749N/A INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
749N/A INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
749N/A INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
749N/A INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
749N/A INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
749N/A INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
749N/A INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
749N/A INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
749N/A INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
749N/A INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
749N/A INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
749N/A INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
749N/A INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
749N/A INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
749N/A INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
749N/A INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
749N/A INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
749N/A INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
749N/A INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
749N/A INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
749N/A INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
749N/A INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
749N/A INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
749N/A INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
749N/A INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
749N/A INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
749N/A INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
749N/A INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
749N/A INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
749N/A INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
749N/A INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
749N/A INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
749N/A INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
749N/A INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
749N/A INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
749N/A INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
749N/A INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
749N/A INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
749N/A INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
749N/A INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
749N/A INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
749N/A INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
749N/A INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
749N/A INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
749N/A INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
749N/A INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
749N/A INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
749N/A INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
749N/A INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
749N/A INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
749N/A INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
749N/A INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
749N/A INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT3 mobile */
749N/A INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
749N/A INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
749N/A INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
749N/A INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
749N/A INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
749N/A INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
749N/A INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
749N/A INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
749N/A INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
749N/A INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
749N/A INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
749N/A INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
749N/A INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
749N/A INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
749N/A INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
749N/A INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
749N/A INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
749N/A INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
749N/A INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
749N/A INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
749N/A INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
749N/A INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
749N/A INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
749N/A INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
749N/A INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
749N/A INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
749N/A INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
749N/A INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
749N/A INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
749N/A INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
749N/A INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
749N/A INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
749N/A INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
749N/A INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
749N/A INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
749N/A INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
749N/A {0, 0, 0}
749N/A};
749N/A
749N/A#define PCI_VENDOR_ID_INTEL 0x8086
749N/A
749N/Avoid intel_detect_pch (struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A dev_info_t *isa_dip;
749N/A int vendor_id, device_id;
749N/A /* LINTED */
749N/A int error;
749N/A /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
749N/A * (which really amounts to a PCH but no South Display).
749N/A */
749N/A if (INTEL_INFO(dev)->num_pipes == 0) {
749N/A dev_priv->pch_type = PCH_NOP;
749N/A return;
749N/A }
749N/A
749N/A /*
749N/A * The reason to probe ISA bridge instead of Dev31:Fun0 is to
749N/A * make graphics device passthrough work easy for VMM, that only
749N/A * need to expose ISA bridge to let driver know the real hardware
749N/A * underneath. This is a requirement from virtualization team.
749N/A */
749N/A isa_dip = ddi_find_devinfo("isa", -1, 0);
749N/A
749N/A if (isa_dip) {
749N/A vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, isa_dip, DDI_PROP_DONTPASS,
749N/A "vendor-id", -1);
749N/A DRM_DEBUG("vendor_id 0x%x", vendor_id);
749N/A
749N/A if (vendor_id == PCI_VENDOR_ID_INTEL) {
749N/A device_id = ddi_prop_get_int(DDI_DEV_T_ANY, isa_dip, DDI_PROP_DONTPASS,
749N/A "device-id", -1);
749N/A DRM_DEBUG("device_id 0x%x", device_id);
749N/A device_id &= INTEL_PCH_DEVICE_ID_MASK;
749N/A dev_priv->pch_id = (unsigned short) device_id;
749N/A if (device_id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
749N/A dev_priv->pch_type = PCH_IBX;
749N/A DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
749N/A WARN_ON(!IS_GEN5(dev));
749N/A } else if (device_id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
749N/A dev_priv->pch_type = PCH_CPT;
749N/A DRM_DEBUG_KMS("Found CougarPoint PCH\n");
749N/A WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
749N/A } else if (device_id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
749N/A /* PantherPoint is CPT compatible */
749N/A dev_priv->pch_type = PCH_CPT;
749N/A DRM_DEBUG_KMS("Found PatherPoint PCH\n");
749N/A WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
749N/A } else if (device_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
749N/A dev_priv->pch_type = PCH_LPT;
749N/A DRM_DEBUG_KMS("Found LynxPoint PCH\n");
749N/A WARN_ON(!IS_HASWELL(dev));
749N/A WARN_ON(IS_ULT(dev));
749N/A } else if (device_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
749N/A dev_priv->pch_type = PCH_LPT;
749N/A DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
749N/A WARN_ON(!IS_HASWELL(dev));
749N/A WARN_ON(!IS_ULT(dev));
749N/A }
749N/A }
749N/A }
749N/A}
749N/A
749N/Abool i915_semaphore_is_enabled(struct drm_device *dev)
749N/A{
749N/A if (INTEL_INFO(dev)->gen < 6)
749N/A return 0;
749N/A
749N/A if (i915_semaphores >= 0)
749N/A return i915_semaphores;
749N/A
749N/A#ifdef CONFIG_INTEL_IOMMU
749N/A /* Enable semaphores on SNB when IO remapping is off */
749N/A if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
749N/A return false;
749N/A#endif
749N/A
749N/A return 1;
749N/A}
749N/A
749N/Astatic int i915_drm_freeze(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A struct drm_crtc *crtc;
749N/A
749N/A /* ignore lid events during suspend */
749N/A mutex_lock(&dev_priv->modeset_restore_lock);
749N/A dev_priv->modeset_restore = MODESET_SUSPENDED;
749N/A mutex_unlock(&dev_priv->modeset_restore_lock);
749N/A
749N/A intel_set_power_well(dev, true);
749N/A
749N/A drm_kms_helper_poll_disable(dev);
749N/A
749N/A /* XXX FIXME: pci_save_state(dev->pdev); */
749N/A
749N/A /* If KMS is active, we do the leavevt stuff here */
749N/A if (drm_core_check_feature(dev, DRIVER_MODESET) && dev_priv->gtt.total !=0) {
749N/A
749N/A if (i915_gem_idle(dev, 0))
749N/A DRM_ERROR("GEM idle failed, resume may fail\n");
749N/A
749N/A del_timer_sync(&dev_priv->rps.delayed_resume_timer);
749N/A
749N/A
749N/A (void) drm_irq_uninstall(dev);
749N/A dev_priv->enable_hotplug_processing = false;
749N/A /*
749N/A * Disable CRTCs directly since we want to preserve sw state
749N/A * for _thaw.
749N/A */
749N/A list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head)
749N/A dev_priv->display.crtc_disable(crtc);
749N/A
749N/A intel_modeset_suspend_hw(dev);
749N/A }
749N/A
749N/A if (dev_priv->gtt.total !=0)
749N/A (void) i915_save_state(dev);
749N/A
749N/A return 0;
749N/A}
749N/A
749N/Aint
749N/Ai915_suspend(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A int error;
749N/A
749N/A /*
749N/A * First, try to restore the "console".
749N/A */
749N/A (void) drm_fb_helper_force_kernel_mode();
749N/A
749N/A if (!dev || !dev_priv) {
749N/A DRM_ERROR("dev: %p, dev_priv: %p\n", dev, dev_priv);
749N/A DRM_ERROR("DRM not initialized, aborting suspend.\n");
749N/A return -ENODEV;
749N/A }
749N/A
749N/A error = i915_drm_freeze(dev);
749N/A if (error)
749N/A return error;
749N/A
749N/A return 0;
749N/A}
749N/A
749N/Astatic int
749N/A__i915_drm_thaw(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A int error = 0;
749N/A
749N/A if (dev_priv->gtt.total !=0)
749N/A (void) i915_restore_state(dev);
749N/A
749N/A /* KMS EnterVT equivalent */
749N/A if (drm_core_check_feature(dev, DRIVER_MODESET) && dev_priv->gtt.total !=0) {
749N/A intel_init_pch_refclk(dev);
749N/A
749N/A mutex_lock(&dev->struct_mutex);
749N/A dev_priv->mm.suspended = 0;
749N/A
749N/A error = i915_gem_init_hw(dev);
749N/A mutex_unlock(&dev->struct_mutex);
749N/A
749N/A /* We need working interrupts for modeset enabling ... */
749N/A (void) drm_irq_install(dev);
749N/A
749N/A intel_modeset_init_hw(dev);
749N/A drm_modeset_lock_all(dev);
749N/A intel_modeset_setup_hw_state(dev, true);
749N/A drm_modeset_unlock_all(dev);
749N/A
749N/A /*
749N/A * ... but also need to make sure that hotplug processing
749N/A * doesn't cause havoc. Like in the driver load code we don't
749N/A * bother with the tiny race here where we might loose hotplug
749N/A * notifications.
749N/A * */
749N/A intel_hpd_init(dev);
749N/A dev_priv->enable_hotplug_processing = true;
749N/A }
749N/A
749N/A mutex_lock(&dev_priv->modeset_restore_lock);
749N/A dev_priv->modeset_restore = MODESET_DONE;
749N/A mutex_unlock(&dev_priv->modeset_restore_lock);
749N/A
749N/A return error;
749N/A}
749N/A
749N/Astatic int
749N/Ai915_drm_thaw(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A int error = 0;
749N/A
749N/A if (dev_priv->gtt.total !=0)
749N/A intel_gt_sanitize(dev);
749N/A if (drm_core_check_feature(dev, DRIVER_MODESET) &&
749N/A dev_priv->gtt.total !=0) {
749N/A mutex_lock(&dev->struct_mutex);
749N/A i915_gem_restore_gtt_mappings(dev);
749N/A mutex_unlock(&dev->struct_mutex);
749N/A }
749N/A __i915_drm_thaw(dev);
749N/A
749N/A return error;
749N/A}
749N/A
749N/Aint
749N/Ai915_resume(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A int ret;
749N/A if (dev_priv->gtt.total !=0)
749N/A intel_gt_sanitize(dev);
749N/A if (drm_core_check_feature(dev, DRIVER_MODESET) &&
749N/A dev_priv->gtt.total !=0) {
749N/A mutex_lock(&dev->struct_mutex);
749N/A i915_gem_restore_gtt_mappings(dev);
749N/A mutex_unlock(&dev->struct_mutex);
749N/A }
749N/A
749N/A ret = __i915_drm_thaw(dev);
749N/A if (ret)
749N/A return ret;
749N/A
749N/A drm_kms_helper_poll_enable(dev);
749N/A return 0;
749N/A}
749N/A
749N/Astatic int i8xx_do_reset(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A
749N/A if (IS_I85X(dev))
749N/A return -ENODEV;
749N/A
749N/A I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
749N/A POSTING_READ(D_STATE);
749N/A
749N/A if (IS_I830(dev) || IS_845G(dev)) {
749N/A I915_WRITE(DEBUG_RESET_I830,
749N/A DEBUG_RESET_DISPLAY |
749N/A DEBUG_RESET_RENDER |
749N/A DEBUG_RESET_FULL);
749N/A POSTING_READ(DEBUG_RESET_I830);
749N/A msleep(1);
749N/A
749N/A I915_WRITE(DEBUG_RESET_I830, 0);
749N/A POSTING_READ(DEBUG_RESET_I830);
749N/A }
749N/A
749N/A msleep(1);
749N/A
749N/A I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
749N/A POSTING_READ(D_STATE);
749N/A
749N/A return 0;
749N/A}
749N/A
749N/Astatic int i965_reset_complete(struct drm_device *dev)
749N/A{
749N/A u8 gdrst;
749N/A (void) pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
749N/A return (gdrst & GRDOM_RESET_ENABLE) == 0;
749N/A}
749N/A
749N/Astatic int i965_do_reset(struct drm_device *dev)
749N/A{
749N/A int ret;
749N/A u8 gdrst;
749N/A
749N/A /*
749N/A * Set the domains we want to reset (GRDOM/bits 2 and 3) as
749N/A * well as the reset bit (GR/bit 0). Setting the GR bit
749N/A * triggers the reset; when done, the hardware will clear it.
749N/A */
749N/A pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
749N/A pci_write_config_byte(dev->pdev, I965_GDRST,
749N/A gdrst | GRDOM_RENDER |
749N/A GRDOM_RESET_ENABLE);
749N/A ret = wait_for(i965_reset_complete(dev), 500);
749N/A if (ret)
749N/A return ret;
749N/A
749N/A /* We can't reset render&media without also resetting display ... */
749N/A pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
749N/A pci_write_config_byte(dev->pdev, I965_GDRST,
749N/A gdrst | GRDOM_MEDIA |
749N/A GRDOM_RESET_ENABLE);
749N/A
749N/A return wait_for(i965_reset_complete(dev), 500);
749N/A}
749N/A
749N/Astatic int ironlake_do_reset(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A u32 gdrst;
749N/A int ret;
749N/A
749N/A gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
749N/A gdrst &= ~GRDOM_MASK;
749N/A I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
749N/A gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
749N/A ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
749N/A if (ret)
749N/A return ret;
749N/A
749N/A /* We can't reset render&media without also resetting display ... */
749N/A gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
749N/A gdrst &= ~GRDOM_MASK;
749N/A I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
749N/A gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
749N/A return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
749N/A}
749N/A
749N/Astatic int gen6_do_reset(struct drm_device *dev)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A int ret;
749N/A unsigned long irqflags;
749N/A
749N/A /* Hold gt_lock across reset to prevent any register access
749N/A * with forcewake not set correctly
749N/A */
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A
749N/A /* Reset the chip */
749N/A
749N/A /* GEN6_GDRST is not in the gt power well, no need to check
749N/A * for fifo space for the write or forcewake the chip for
749N/A * the read
749N/A */
749N/A I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
749N/A
749N/A /* Spin waiting for the device to ack the reset request */
749N/A ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
749N/A
749N/A /* If reset with a user forcewake, try to restore, otherwise turn it off */
749N/A if (dev_priv->forcewake_count)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A else
749N/A dev_priv->gt.force_wake_put(dev_priv);
749N/A
749N/A /* Restore fifo count */
749N/A dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
749N/A
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A return ret;
749N/A}
749N/A
749N/Aint intel_gpu_reset(struct drm_device *dev)
749N/A{
749N/A switch (INTEL_INFO(dev)->gen) {
749N/A case 7:
749N/A case 6: return gen6_do_reset(dev);
749N/A case 5: return ironlake_do_reset(dev);
749N/A case 4: return i965_do_reset(dev);
749N/A case 2: return i8xx_do_reset(dev);
749N/A default: return -ENODEV;
749N/A }
749N/A}
749N/A
749N/A/**
749N/A * i915_reset - reset chip after a hang
749N/A * @dev: drm device to reset
749N/A *
749N/A * Reset the chip. Useful if a hang is detected. Returns zero on successful
749N/A * reset or otherwise an error code.
749N/A *
749N/A * Procedure is fairly simple:
749N/A * - reset the chip using the reset reg
749N/A * - re-init context state
749N/A * - re-init hardware status page
749N/A * - re-init ring buffer
749N/A * - re-init interrupt state
749N/A * - re-init display
749N/A */
749N/Aint i915_reset(struct drm_device *dev)
749N/A{
749N/A drm_i915_private_t *dev_priv = dev->dev_private;
749N/A struct timeval cur_time;
749N/A bool simulated;
749N/A int ret;
749N/A
749N/A if (!i915_try_reset)
749N/A return 0;
749N/A
749N/A mutex_lock(&dev->struct_mutex);
749N/A
749N/A i915_gem_reset(dev);
749N/A
749N/A simulated = dev_priv->gpu_error.stop_rings != 0;
749N/A
749N/A do_gettimeofday(&cur_time);
749N/A if (!simulated && cur_time.tv_sec - dev_priv->gpu_error.last_reset < 5) {
749N/A ret = -ENODEV;
749N/A DRM_ERROR("GPU hanging too fast, wait 5 secons for another reset");
749N/A mutex_unlock(&dev->struct_mutex);
749N/A return ret;
749N/A } else {
749N/A ret = intel_gpu_reset(dev);
749N/A
749N/A /* Also reset the gpu hangman. */
749N/A if (simulated) {
749N/A DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
749N/A dev_priv->gpu_error.stop_rings = 0;
749N/A if (ret == -ENODEV) {
749N/A DRM_ERROR("Reset not implemented, but ignoring "
749N/A "error for simulated gpu hangs\n");
749N/A ret = 0;
749N/A }
749N/A } else {
749N/A do_gettimeofday(&cur_time);
749N/A dev_priv->gpu_error.last_reset = cur_time.tv_sec;
749N/A }
749N/A }
749N/A if (ret) {
749N/A DRM_ERROR("Failed to reset chip.\n");
749N/A mutex_unlock(&dev->struct_mutex);
749N/A return ret;
749N/A }
749N/A
749N/A /* Ok, now get things going again... */
749N/A
749N/A /*
749N/A * Everything depends on having the GTT running, so we need to start
749N/A * there. Fortunately we don't need to do this unless we reset the
749N/A * chip at a PCI level.
749N/A *
749N/A * Next we need to restore the context, but we don't use those
749N/A * yet either...
749N/A *
749N/A * Ring buffer needs to be re-initialized in the KMS case, or if X
749N/A * was running at the time of the reset (i.e. we weren't VT
749N/A * switched away).
749N/A */
749N/A if (drm_core_check_feature(dev, DRIVER_MODESET) ||
749N/A !dev_priv->mm.suspended) {
749N/A struct intel_ring_buffer *ring;
749N/A int i;
749N/A
749N/A dev_priv->mm.suspended = 0;
749N/A
749N/A i915_gem_init_swizzling(dev);
749N/A
749N/A for_each_ring(ring, dev_priv, i)
749N/A ring->init(ring);
749N/A
749N/A i915_gem_context_init(dev);
749N/A if (dev_priv->mm.aliasing_ppgtt) {
749N/A ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
749N/A if (ret)
749N/A i915_gem_cleanup_aliasing_ppgtt(dev);
749N/A }
749N/A
749N/A /*
749N/A * It would make sense to re-init all the other hw state, at
749N/A * least the rps/rc6/emon init done within modeset_init_hw. For
749N/A * some unknown reason, this blows up my ilk, so don't.
749N/A */
749N/A
749N/A mutex_unlock(&dev->struct_mutex);
749N/A
749N/A (void) drm_irq_uninstall(dev);
749N/A if (drm_irq_install(dev)) {
749N/A DRM_ERROR("Could not install irq for driver.\n");
749N/A return -EIO;
749N/A }
749N/A intel_hpd_init(dev);
749N/A } else {
749N/A mutex_unlock(&dev->struct_mutex);
749N/A }
749N/A
749N/A return 0;
749N/A}
749N/A
749N/Astatic struct drm_driver driver = {
749N/A /* don't use mtrr's here, the Xserver or user space app should
749N/A * deal with them for intel hardware.
749N/A */
749N/A .driver_features =
749N/A DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
749N/A DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
749N/A .load = i915_driver_load,
749N/A .unload = i915_driver_unload,
749N/A .firstopen = i915_driver_firstopen,
749N/A .open = i915_driver_open,
749N/A .lastclose = i915_driver_lastclose,
749N/A .preclose = i915_driver_preclose,
749N/A .postclose = i915_driver_postclose,
749N/A
749N/A /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
749N/A .device_is_agp = i915_driver_device_is_agp,
749N/A .master_create = i915_master_create,
749N/A .master_destroy = i915_master_destroy,
749N/A /* OSOL begin */
749N/A .entervt = i915_driver_entervt,
749N/A .leavevt = i915_driver_leavevt,
749N/A .agp_support_detect = i915_driver_agp_support_detect,
749N/A /* OSOL end */
749N/A#if defined(CONFIG_DEBUG_FS)
749N/A .debugfs_init = i915_debugfs_init,
749N/A .debugfs_cleanup = i915_debugfs_cleanup,
749N/A#endif
749N/A .gem_init_object = i915_gem_init_object,
749N/A .gem_free_object = i915_gem_free_object,
749N/A /*.gem_vm_ops = &i915_gem_vm_ops,*/
749N/A .gem_fault = i915_gem_fault,
749N/A .ioctls = i915_ioctls,
749N/A
749N/A .id_table = pciidlist,
749N/A
749N/A .name = DRIVER_NAME,
749N/A .desc = DRIVER_DESC,
749N/A .date = DRIVER_DATE,
749N/A .major = DRIVER_MAJOR,
749N/A .minor = DRIVER_MINOR,
749N/A .patchlevel = DRIVER_PATCHLEVEL,
749N/A};
749N/A
749N/Astatic int
749N/Ai915_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
749N/A{
749N/A struct drm_device *dev;
749N/A int ret, item;
749N/A
749N/A item = ddi_get_instance(dip);
749N/A
749N/A switch (cmd) {
749N/A case DDI_ATTACH:
749N/A if (ddi_soft_state_zalloc(i915_statep, item) != DDI_SUCCESS) {
749N/A DRM_ERROR("failed to alloc softstate, item = %d", item);
749N/A return (DDI_FAILURE);
749N/A }
749N/A
749N/A dev = ddi_get_soft_state(i915_statep, item);
749N/A if (!dev) {
749N/A DRM_ERROR("cannot get soft state");
749N/A return (DDI_FAILURE);
749N/A }
749N/A
749N/A dev->devinfo = dip;
749N/A
749N/A if (!(driver.driver_features & DRIVER_MODESET))
749N/A driver.get_vblank_timestamp = NULL;
749N/A
749N/A ret = drm_init(dev, &driver);
749N/A if (ret != DDI_SUCCESS)
749N/A (void) ddi_soft_state_free(i915_statep, item);
749N/A
749N/A return (ret);
749N/A
749N/A case DDI_RESUME:
749N/A dev = ddi_get_soft_state(i915_statep, item);
749N/A if (!dev) {
749N/A DRM_ERROR("cannot get soft state");
749N/A return (DDI_FAILURE);
749N/A }
749N/A
749N/A return (i915_resume(dev));
749N/A }
749N/A
749N/A DRM_ERROR("only supports attach or resume");
749N/A return (DDI_FAILURE);
749N/A}
749N/A
749N/Astatic int
749N/Ai915_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
749N/A{
749N/A struct drm_device *dev;
749N/A int item;
749N/A
749N/A item = ddi_get_instance(dip);
749N/A dev = ddi_get_soft_state(i915_statep, item);
749N/A if (!dev) {
749N/A DRM_ERROR("cannot get soft state");
749N/A return (DDI_FAILURE);
749N/A }
749N/A
749N/A switch (cmd) {
749N/A case DDI_DETACH:
749N/A drm_exit(dev);
749N/A (void) ddi_soft_state_free(i915_statep, item);
749N/A return (DDI_SUCCESS);
749N/A
749N/A case DDI_SUSPEND:
749N/A return (i915_suspend(dev));
749N/A }
749N/A
749N/A DRM_ERROR("only supports detach or suspend");
749N/A return (DDI_FAILURE);
749N/A}
749N/A
749N/Astatic int
749N/A/* LINTED */
749N/Ai915_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
749N/A{
749N/A struct drm_minor *minor;
749N/A
749N/A minor = idr_find(&drm_minors_idr, DRM_DEV2MINOR((dev_t)arg));
749N/A if (!minor)
749N/A return (DDI_FAILURE);
749N/A if (!minor->dev || !minor->dev->devinfo)
749N/A return (DDI_FAILURE);
749N/A
749N/A switch (infocmd) {
749N/A case DDI_INFO_DEVT2DEVINFO:
749N/A *result = (void *)minor->dev->devinfo;
749N/A return (DDI_SUCCESS);
749N/A
749N/A case DDI_INFO_DEVT2INSTANCE:
749N/A *result = (void *)(uintptr_t)ddi_get_instance(minor->dev->devinfo);
749N/A return (DDI_SUCCESS);
749N/A }
749N/A
749N/A return (DDI_FAILURE);
749N/A}
749N/A
749N/Astatic int
749N/Ai915_quiesce(dev_info_t *dip)
749N/A{
749N/A struct drm_device *dev;
749N/A struct drm_i915_private *dev_priv;
749N/A struct drm_crtc *crtc;
749N/A int ret = 0;
749N/A
749N/A dev = ddi_get_soft_state(i915_statep, ddi_get_instance(dip));
749N/A
749N/A if (!dev)
749N/A return (DDI_FAILURE);
749N/A
749N/A dev_priv = dev->dev_private;
749N/A
749N/A if (dev_priv && dev_priv->gtt.total !=0) {
749N/A
749N/A
749N/A
749N/A (void) drm_fb_helper_force_kernel_mode();
749N/A
749N/A mutex_lock(&dev->struct_mutex);
749N/A ret = i915_gpu_idle(dev);
749N/A if (ret)
749N/A DRM_ERROR("failed to idle hardware: %d\n", ret);
749N/A i915_gem_retire_requests(dev);
749N/A mutex_unlock(&dev->struct_mutex);
749N/A
749N/A if (dev_priv->fbcon_obj != NULL)
749N/A intel_fbdev_fini(dev);
749N/A
749N/A drm_kms_helper_poll_fini(dev);
749N/A mutex_lock(&dev->struct_mutex);
749N/A
749N/A list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
749N/A /* Skip inactive CRTCs */
749N/A if (!crtc->fb)
749N/A continue;
749N/A
749N/A intel_increase_pllclock(crtc);
749N/A }
749N/A
749N/A intel_disable_fbc(dev);
749N/A
749N/A intel_disable_gt_powersave(dev);
749N/A
749N/A ironlake_teardown_rc6(dev);
749N/A
749N/A mutex_unlock(&dev->struct_mutex);
749N/A drm_mode_config_cleanup(dev);
749N/A
749N/A mutex_lock(&dev->struct_mutex);
749N/A i915_gem_free_all_phys_object(dev);
749N/A i915_gem_cleanup_ringbuffer(dev);
749N/A i915_gem_context_fini(dev);
749N/A mutex_unlock(&dev->struct_mutex);
749N/A
749N/A i915_gem_cleanup_aliasing_ppgtt(dev);
749N/A i915_gem_cleanup_stolen(dev);
749N/A drm_mm_takedown(&dev_priv->mm.stolen);
749N/A intel_cleanup_overlay(dev);
749N/A
749N/A i915_gem_lastclose(dev);
749N/A
749N/A if (dev_priv->gtt.scratch_page)
749N/A teardown_scratch_page(dev);
749N/A
749N/A if (MDB_TRACK_ENABLE) {
749N/A struct batch_info_list *r_list, *list_temp;
749N/A list_for_each_entry_safe(r_list, list_temp, struct batch_info_list, &dev_priv->batch_list, head) {
749N/A list_del(&r_list->head);
749N/A drm_free(r_list->obj_list, r_list->num * sizeof(caddr_t), DRM_MEM_MAPS);
749N/A drm_free(r_list, sizeof (struct batch_info_list), DRM_MEM_MAPS);
749N/A }
749N/A list_del(&dev_priv->batch_list);
749N/A }
749N/A
749N/A if (dev->old_gtt) {
749N/A intel_rw_gtt(dev, dev->old_gtt_size,
749N/A 0, (void *) dev->old_gtt, 1);
749N/A kmem_free(dev->old_gtt, dev->old_gtt_size);
749N/A }
749N/A }
749N/A
749N/A return (DDI_SUCCESS);
749N/A}
749N/A
749N/Astatic int __init i915_init(void)
749N/A{
749N/A driver.num_ioctls = i915_max_ioctl;
749N/A
749N/A driver.driver_features |= DRIVER_MODESET;
749N/A
749N/A return 0;
749N/A}
749N/A
749N/Astatic void __exit i915_exit(void)
749N/A{
749N/A
749N/A}
749N/A
749N/Aint
749N/A_init(void)
749N/A{
749N/A int ret;
749N/A
749N/A ret = ddi_soft_state_init(&i915_statep,
749N/A sizeof (struct drm_device), DRM_MAX_INSTANCES);
749N/A if (ret)
749N/A return (ret);
749N/A
749N/A ret = i915_init();
749N/A if (ret) {
749N/A ddi_soft_state_fini(&i915_statep);
749N/A return (ret);
749N/A }
749N/A
749N/A ret = mod_install(&modlinkage);
749N/A if (ret) {
749N/A i915_exit();
749N/A ddi_soft_state_fini(&i915_statep);
749N/A return (ret);
749N/A }
749N/A
749N/A return (ret);
749N/A}
749N/A
749N/Aint
749N/A_fini(void)
749N/A{
749N/A int ret;
749N/A
749N/A ret = mod_remove(&modlinkage);
749N/A if (ret)
749N/A return (ret);
749N/A
749N/A i915_exit();
749N/A
749N/A ddi_soft_state_fini(&i915_statep);
749N/A
749N/A return (ret);
749N/A}
749N/A
749N/Aint
749N/A_info(struct modinfo *modinfop)
749N/A{
749N/A return (mod_info(&modlinkage, modinfop));
749N/A}
749N/A
749N/A/* We give fast paths for the really cool registers */
749N/A#define NEEDS_FORCE_WAKE(dev_priv, reg) \
749N/A ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
749N/A ((reg) < 0x40000) && \
749N/A ((reg) != FORCEWAKE))
749N/A
749N/Astatic void
749N/Ailk_dummy_write(struct drm_i915_private *dev_priv)
749N/A{
749N/A /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
749N/A * chip from rc6 before touching it for real. MI_MODE is masked, hence
749N/A * harmless to write 0 into. */
749N/A I915_WRITE_NOTRACE(MI_MODE, 0);
749N/A}
749N/A
749N/Astatic void
749N/Ahsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
749N/A{
749N/A if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
749N/A (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
749N/A DRM_INFO("Unknown unclaimed register before writing to %x\n",
749N/A reg);
749N/A I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
749N/A }
749N/A}
749N/A
749N/Astatic void
749N/Ahsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
749N/A{
749N/A if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
749N/A (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
749N/A DRM_INFO("Unclaimed write to %x\n", reg);
749N/A I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
749N/A }
749N/A}
749N/A
749N/Au8 i915_read8(struct drm_i915_private *dev_priv, u32 reg)
749N/A{
749N/A u8 val;
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg)) {
749N/A unsigned long irqflags;
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A val = DRM_READ8(dev_priv->regs, reg);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_put(dev_priv);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A } else
749N/A val = DRM_READ8(dev_priv->regs, (reg));
749N/A return val;
749N/A}
749N/A
749N/Au16 i915_read16(struct drm_i915_private *dev_priv, u32 reg)
749N/A{
749N/A u16 val;
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg)) {
749N/A unsigned long irqflags;
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A val = DRM_READ16(dev_priv->regs, reg);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A } else
749N/A val = DRM_READ16(dev_priv->regs, (reg));
749N/A return val;
749N/A}
749N/A
749N/Au32 i915_read32(struct drm_i915_private *dev_priv, u32 reg)
749N/A{
749N/A u32 val;
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg)) {
749N/A unsigned long irqflags;
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A val = DRM_READ32(dev_priv->regs, reg);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A } else
749N/A val = DRM_READ32(dev_priv->regs, (reg));
749N/A return val;
749N/A}
749N/A
749N/Au64 i915_read64(struct drm_i915_private *dev_priv, u32 reg)
749N/A{
749N/A u64 val;
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg)) {
749N/A unsigned long irqflags;
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A val = DRM_READ64(dev_priv->regs, reg);
749N/A if (dev_priv->forcewake_count == 0)
749N/A dev_priv->gt.force_wake_get(dev_priv);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A } else
749N/A val = DRM_READ64(dev_priv->regs, (reg));
749N/A return val;
749N/A}
749N/A
749N/Avoid i915_write8(struct drm_i915_private *dev_priv, u32 reg,
749N/A u8 val)
749N/A{
749N/A unsigned long irqflags;
749N/A u32 __fifo_ret = 0;
749N/A
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg))
749N/A __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv);
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A hsw_unclaimed_reg_clear(dev_priv, reg);
749N/A
749N/A DRM_WRITE8(dev_priv->regs, (reg), (val));
749N/A if (__fifo_ret)
749N/A gen6_gt_check_fifodbg(dev_priv);
749N/A hsw_unclaimed_reg_check(dev_priv, reg);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A}
749N/A
749N/Avoid i915_write16(struct drm_i915_private *dev_priv, u32 reg,
749N/A u16 val)
749N/A{
749N/A unsigned long irqflags;
749N/A u32 __fifo_ret = 0;
749N/A
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg))
749N/A __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv);
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A hsw_unclaimed_reg_clear(dev_priv, reg);
749N/A
749N/A DRM_WRITE16(dev_priv->regs, (reg), (val));
749N/A if (__fifo_ret)
749N/A gen6_gt_check_fifodbg(dev_priv);
749N/A hsw_unclaimed_reg_check(dev_priv, reg);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A}
749N/A
749N/Avoid i915_write32(struct drm_i915_private *dev_priv, u32 reg,
749N/A u32 val)
749N/A{
749N/A unsigned long irqflags;
749N/A u32 __fifo_ret = 0;
749N/A
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg))
749N/A __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv);
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A hsw_unclaimed_reg_clear(dev_priv, reg);
749N/A
749N/A DRM_WRITE32(dev_priv->regs, (reg), (val));
749N/A if (__fifo_ret)
749N/A gen6_gt_check_fifodbg(dev_priv);
749N/A hsw_unclaimed_reg_check(dev_priv, reg);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A}
749N/A
749N/Avoid i915_write64(struct drm_i915_private *dev_priv, u32 reg,
749N/A u64 val)
749N/A{
749N/A unsigned long irqflags;
749N/A u32 __fifo_ret = 0;
749N/A
749N/A spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
749N/A if (NEEDS_FORCE_WAKE(dev_priv, reg))
749N/A __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv);
749N/A
749N/A if (IS_GEN5(dev_priv->dev))
749N/A ilk_dummy_write(dev_priv);
749N/A
749N/A hsw_unclaimed_reg_clear(dev_priv, reg);
749N/A
749N/A DRM_WRITE64(dev_priv->regs, (reg), (val));
749N/A if (__fifo_ret)
749N/A gen6_gt_check_fifodbg(dev_priv);
749N/A hsw_unclaimed_reg_check(dev_priv, reg);
749N/A spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
749N/A}
749N/A
749N/A#define __i915_read(x) \
749N/Au ## x i915_read ## x(struct drm_i915_private *dev_priv, u32 reg);
749N/A
749N/A__i915_read(8)
749N/A__i915_read(16)
749N/A__i915_read(32)
749N/A__i915_read(64)
749N/A#undef __i915_read
749N/A
749N/A#define __i915_write(x) \
749N/Avoid i915_write ## x(struct drm_i915_private *dev_priv, u32 reg, \
749N/A u ## x val);
749N/A
749N/A__i915_write(8)
749N/A__i915_write(16)
749N/A__i915_write(32)
749N/A__i915_write(64)
749N/A#undef __i915_write
749N/A
749N/Astatic const struct register_whitelist {
749N/A uint64_t offset;
749N/A uint32_t size;
749N/A uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
749N/A} whitelist[] = {
749N/A { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
749N/A};
749N/A
749N/Aint i915_reg_read_ioctl(DRM_IOCTL_ARGS)
749N/A{
749N/A struct drm_i915_private *dev_priv = dev->dev_private;
749N/A struct drm_i915_reg_read *reg = data;
749N/A struct register_whitelist const *entry = whitelist;
749N/A int i;
749N/A
749N/A for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
749N/A if (entry->offset == reg->offset &&
749N/A (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
749N/A break;
749N/A }
749N/A
749N/A if (i == ARRAY_SIZE(whitelist))
749N/A return -EINVAL;
749N/A
749N/A switch (entry->size) {
749N/A case 8:
749N/A reg->val = I915_READ64(reg->offset);
749N/A break;
749N/A case 4:
749N/A reg->val = I915_READ(reg->offset);
749N/A break;
749N/A case 2:
749N/A reg->val = I915_READ16(reg->offset);
749N/A break;
749N/A case 1:
749N/A reg->val = I915_READ8(reg->offset);
749N/A break;
749N/A default:
749N/A WARN_ON(1);
749N/A return -EINVAL;
749N/A }
749N/A
749N/A return 0;
749N/A}
749N/A
749N/Avoid i915_gem_chipset_flush(struct drm_device *dev)
749N/A{
749N/A if (INTEL_INFO(dev)->gen < 6)
749N/A drm_agp_chipset_flush(dev);
749N/A}
749N/A
749N/Avoid i915_driver_agp_support_detect(struct drm_device *dev, unsigned long flags)
749N/A{
749N/A struct intel_device_info *info;
749N/A info = (struct intel_device_info *) flags;
749N/A
749N/A /* Remove AGP support for GEN6+ platform */
749N/A if (info->gen >= 6)
749N/A driver.driver_features &= ~DRIVER_USE_AGP;
749N/A}
749N/A