Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/i915

Lines Matching refs:I915_READ
78 	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
79 	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
80 	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
81 	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
204 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
215 		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
216 		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
217 		dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
218 		dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
219 		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
221 			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
223 		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
224 		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
225 		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
226 		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
228 			dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
230 			dev_priv->regfile.saveLVDS = I915_READ(LVDS);
236 		dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
239 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
240 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
241 		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
243 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
244 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
245 		dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
251 			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
253 			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
255 			dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
256 			dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
257 			dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
258 			dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
357 			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
358 			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
359 			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
360 			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
361 			dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
362 			dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
364 				I915_READ(RSTDBYCTL);
365 			dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
367 			dev_priv->regfile.saveIER = I915_READ(IER);
368 			dev_priv->regfile.saveIMR = I915_READ(IMR);
375 	dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
378 	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
382 		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
383 		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
386 		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));