Searched refs:I915_WRITE (Results 1 - 25 of 30) sorted by relevance

12

/solaris-x11-s11/open-src/kernel/i915/src/
H A Di915_ums.c92 I915_WRITE(reg + (i << 2), array[i]);
285 I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
286 I915_WRITE(_PIPEB_DATA_M_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
287 I915_WRITE(_PIPEA_DATA_N_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
288 I915_WRITE(_PIPEB_DATA_N_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
289 I915_WRITE(_PIPEA_LINK_M_G4X, dev_priv->regfile.savePIPEA_DP_LINK_M);
290 I915_WRITE(_PIPEB_LINK_M_G4X, dev_priv->regfile.savePIPEB_DP_LINK_M);
291 I915_WRITE(_PIPEA_LINK_N_G4X, dev_priv->regfile.savePIPEA_DP_LINK_N);
292 I915_WRITE(_PIPEB_LINK_N_G4X, dev_priv->regfile.savePIPEB_DP_LINK_N);
311 I915_WRITE(FENCE_REG_945_
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H A Dintel_pm.c69 I915_WRITE(FBC_CONTROL, fbc_ctl);
102 I915_WRITE(FBC_TAG + (i * 4), 0);
107 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
108 I915_WRITE(FBC_FENCE_OFF, crtc->y);
117 I915_WRITE(FBC_CONTROL, fbc_ctl);
144 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
146 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
149 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
152 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
166 I915_WRITE(DPFC_CONTRO
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H A Di915_suspend.c142 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
144 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
145 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
146 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
274 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
283 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
289 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
291 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
294 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
297 I915_WRITE(BLC_PWM_PCH_CTL
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H A Dintel_sideband.c48 I915_WRITE(VLV_IOSF_ADDR, addr);
50 I915_WRITE(VLV_IOSF_DATA, *val);
51 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
61 I915_WRITE(VLV_IOSF_DATA, 0);
133 I915_WRITE(SBI_ADDR, (reg << 16));
139 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
163 I915_WRITE(SBI_ADDR, (reg << 16));
164 I915_WRITE(SBI_DATA, value);
170 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
H A Di915_irq.c91 I915_WRITE(DEIMR, dev_priv->irq_mask);
103 I915_WRITE(DEIMR, dev_priv->irq_mask);
164 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
183 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
185 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
200 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
204 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
206 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
328 I915_WRITE(reg, pipestat);
342 I915_WRITE(re
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H A Dintel_i2c.c69 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
85 I915_WRITE(DSPCLK_GATE_D, val);
249 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
254 I915_WRITE(GMBUS4 + reg_offset, 0);
279 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
283 I915_WRITE(GMBUS4 + reg_offset, 0);
300 I915_WRITE(GMBUS1 + reg_offset,
339 I915_WRITE(GMBUS3 + reg_offset, val);
340 I915_WRITE(GMBUS1 + reg_offset,
353 I915_WRITE(GMBUS
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H A Dintel_sprite.c119 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
120 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
130 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
132 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
134 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
135 I915_WRITE(SPCNTR(pipe, plane), sprctl);
150 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
171 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
172 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
173 I915_WRITE(SPKEYMS
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H A Dintel_ddi.c109 I915_WRITE(reg, ddi_translations[i]);
183 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
191 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
197 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
200 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
206 I915_WRITE(DP_TP_CTL(PORT_E),
216 I915_WRITE(DDI_BUF_CTL(PORT_E),
225 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
229 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
238 I915_WRITE(_FDI_RXA_MIS
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H A Dintel_hdmi.c158 I915_WRITE(VIDEO_DIP_CTL, val);
162 I915_WRITE(VIDEO_DIP_DATA, *data);
167 I915_WRITE(VIDEO_DIP_DATA, 0);
174 I915_WRITE(VIDEO_DIP_CTL, val);
198 I915_WRITE(reg, val);
202 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
207 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
214 I915_WRITE(reg, val);
241 I915_WRITE(reg, val);
245 I915_WRITE(TVIDEO_DIP_DAT
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H A Dintel_crt.c140 I915_WRITE(crt->adpa_reg, temp);
280 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
282 I915_WRITE(crt->adpa_reg, adpa);
307 I915_WRITE(crt->adpa_reg, adpa);
314 I915_WRITE(crt->adpa_reg, save_adpa);
344 I915_WRITE(crt->adpa_reg, adpa);
349 I915_WRITE(crt->adpa_reg, save_adpa);
403 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
416 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
419 I915_WRITE(PORT_HOTPLUG_E
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H A Dintel_tv.c865 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
874 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
1055 I915_WRITE(TV_H_CTL_1, hctl1);
1056 I915_WRITE(TV_H_CTL_2, hctl2);
1057 I915_WRITE(TV_H_CTL_3, hctl3);
1058 I915_WRITE(TV_V_CTL_1, vctl1);
1059 I915_WRITE(TV_V_CTL_2, vctl2);
1060 I915_WRITE(TV_V_CTL_3, vctl3);
1061 I915_WRITE(TV_V_CTL_4, vctl4);
1062 I915_WRITE(TV_V_CTL_
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H A Dintel_display.c779 I915_WRITE(pipestat_reg,
1336 I915_WRITE(reg, val);
1339 I915_WRITE(reg, val);
1342 I915_WRITE(reg, val);
1371 I915_WRITE(reg, val);
1490 I915_WRITE(reg, val);
1516 I915_WRITE(reg, val | TRANS_ENABLE);
1536 I915_WRITE(_TRANSA_CHICKEN2, val);
1547 I915_WRITE(LPT_TRANSCONF, val);
1568 I915_WRITE(re
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H A Dintel_ringbuffer.h55 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
58 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
61 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
64 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
67 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
H A Dintel_panel.c344 I915_WRITE(BLC_PWM_PCH_CTL2, val);
355 I915_WRITE(BLC_PWM_CTL, val);
357 I915_WRITE(BLC_PWM_CTL2,
440 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
473 I915_WRITE(BLC_PWM_CTL, tmp | level);
533 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
538 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
587 I915_WRITE(reg, tmp);
589 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
596 I915_WRITE(BLC_PWM_PCH_CTL
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H A Ddvo_ns2501.c114 I915_WRITE(DVOC, 0x10004084);
115 I915_WRITE(_DPLL_A, 0xd0820000);
116 I915_WRITE(DVOC_SRCDIM, 0x400300); // 1024x768
117 I915_WRITE(FW_BLC, 0x1080304);
119 I915_WRITE(DVOC, 0x90004084);
135 I915_WRITE(DVOC, ns->dvoc);
136 I915_WRITE(_DPLL_A, ns->pll_a);
137 I915_WRITE(DVOC_SRCDIM, ns->srcdim);
138 I915_WRITE(FW_BLC, ns->fw_blc);
H A Di915_gem_stolen.c114 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
116 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
128 I915_WRITE(FBC_CFB_BASE,
130 I915_WRITE(FBC_LL_BASE,
H A Di915_gem_gtt.c247 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
251 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
254 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
256 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
261 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
270 I915_WRITE(GAM_ECOCHK, ecochk);
276 I915_WRITE(RING_MODE_GEN7(ring),
279 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
280 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
526 I915_WRITE(GFX_FLSH_CNTL_GEN
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H A Dintel_ringbuffer.c394 I915_WRITE(HWS_PGA, addr);
554 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
563 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
567 I915_WRITE(GFX_MODE,
571 I915_WRITE(GFX_MODE_GEN7,
587 I915_WRITE(CACHE_MODE_0,
599 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
842 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
860 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
879 I915_WRITE(IM
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H A Dintel_dvo.c171 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
182 I915_WRITE(dvo_reg, temp | DVO_ENABLE);
321 I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED);
323 /*I915_WRITE(DVOB_SRCDIM,
326 I915_WRITE(dvo_srcdim_reg,
329 /*I915_WRITE(DVOB, dvo_val);*/
330 I915_WRITE(dvo_reg, dvo_val);
H A Dintel_dp.c357 I915_WRITE(ch_data + i,
361 I915_WRITE(ch_ctl,
383 I915_WRITE(ch_ctl,
819 I915_WRITE(DP_A, dpa_ctl);
1007 I915_WRITE(pp_ctrl_reg, pp);
1037 I915_WRITE(pp_ctrl_reg, pp);
1104 I915_WRITE(PCH_PP_CONTROL, pp);
1114 I915_WRITE(pp_ctrl_reg, pp);
1121 I915_WRITE(PCH_PP_CONTROL, pp);
1146 I915_WRITE(pp_ctrl_re
[all...]
H A Dintel_lvds.c184 I915_WRITE(lvds_encoder->reg, temp);
206 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
208 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
233 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
237 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
1085 I915_WRITE(PCH_PP_CONTROL,
1088 I915_WRITE(PP_CONTROL,
H A Di915_drv.c648 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
652 I915_WRITE(DEBUG_RESET_I830,
659 I915_WRITE(DEBUG_RESET_I830, 0);
665 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
713 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
722 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
H A Dintel_overlay.c1295 I915_WRITE(OGAMC0, attrs->gamma0);
1296 I915_WRITE(OGAMC1, attrs->gamma1);
1297 I915_WRITE(OGAMC2, attrs->gamma2);
1298 I915_WRITE(OGAMC3, attrs->gamma3);
1299 I915_WRITE(OGAMC4, attrs->gamma4);
1300 I915_WRITE(OGAMC5, attrs->gamma5);
H A Di915_gem.c2188 I915_WRITE(fence_reg, 0);
2203 I915_WRITE(fence_reg + 4, val >> 32);
2206 I915_WRITE(fence_reg + 0, val);
2209 I915_WRITE(fence_reg + 4, 0);
2254 I915_WRITE(reg, val);
2286 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3452 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3462 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3468 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3479 I915_WRITE(DISP_ARB_CT
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H A Dintel_bios.c754 I915_WRITE(PP_ON_DELAYS, 0x019007d0);
757 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);

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