1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright (c) 2006, 2013, Intel Corporation 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 1450N/A * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1450N/A * Eric Anholt <eric@anholt.net> 1450N/A /* skip to first section */ 1450N/A /* walk the sections looking for section_id */ 1450N/A * the size of fp_timing varies on the different platform. 1450N/A * So calculate the DVO timing relative offset in LVDS data 1450N/A * entry to get the DVO timing entry 1450N/A * this function may return NULL if the corresponding entry is invalid 1450N/A/* Try to find integrated panel data */ 1450N/A * enumerate the LVDS panel timing info entry in VBT to check whether 1450N/A * the LVDS downclock is found. 1450N/A "Normal Clock %dKHz, downclock %dKHz\n",
1450N/A /* check the resolution, just to be sure */ 1450N/A/* Try to find sdvo panel data */ 1450N/A " %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode" 1450N/A " %d fdi_rx_polarity_inverted %d\n",
1450N/A /* judge whether the size of child device meets the requirements. 1450N/A * If the child device size obtained from general definition block 1450N/A * is different with sizeof(struct child_device_config), skip the 1450N/A * parsing of sdvo device info 1450N/A /* different child dev size . Ignore it */ 1450N/A /* get the block size of general definitions */ 1450N/A /* get the number of child device */ 1450N/A /* skip the device block if device type is invalid */ 1450N/A * If the slave address is neither 0x70 nor 0x72, 1450N/A * it is not a SDVO device. Skip it. 1450N/A /* skip the incorrect SDVO port */ 1450N/A /* Maybe this is a SDVO device with multiple inputs */ 1450N/A /* And the mapping info is not added */ 1450N/A " is a SDVO device with multiple inputs.\n");
1450N/A /* No SDVO device info is found */ 1450N/A /* Get the eDP sequencing and link info */ 1450N/A /* judge whether the size of child device meets the requirements. 1450N/A * If the child device size obtained from general definition block 1450N/A * is different with sizeof(struct child_device_config), skip the 1450N/A * parsing of sdvo device info 1450N/A /* different child dev size . Ignore it */ 1450N/A /* get the block size of general definitions */ 1450N/A /* get the number of child device */ 1450N/A /* get the number of child device that is present */ 1450N/A /* skip the device block if device type is invalid */ 1450N/A /* skip the device block if device type is invalid */ 1450N/A * intel_init_bios - initialize VBIOS settings & find VBT 1450N/A * Loads the Video BIOS and checks that the VBT exists. Sets scratch registers 1450N/A * Returns 0 on success, nonzero on failure. 1450N/A /* Scour memory looking for the VBT signature */ 1450N/A /* Grab useful general definitions */ 1450N/A/* Ensure that vital registers have been initialised, even if the BIOS 1450N/A * is absent or just failing to do its job. 1450N/A /* Set the Panel Power On/Off timings if uninitialized. */ 1450N/A /* Set T2 to 40ms and T5 to 200ms */ 1450N/A /* Set T3 to 35ms and Tx to 200ms */