Lines Matching refs:I915_WRITE
779 I915_WRITE(pipestat_reg,
1336 I915_WRITE(reg, val);
1339 I915_WRITE(reg, val);
1342 I915_WRITE(reg, val);
1371 I915_WRITE(reg, val);
1490 I915_WRITE(reg, val);
1516 I915_WRITE(reg, val | TRANS_ENABLE);
1536 I915_WRITE(_TRANSA_CHICKEN2, val);
1547 I915_WRITE(LPT_TRANSCONF, val);
1568 I915_WRITE(reg, val);
1578 I915_WRITE(reg, val);
1588 I915_WRITE(LPT_TRANSCONF, val);
1596 I915_WRITE(_TRANSA_CHICKEN2, val);
1652 I915_WRITE(reg, val | PIPECONF_ENABLE);
1692 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1704 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1706 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1731 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1755 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1940 I915_WRITE(reg, dspcntr);
1956 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1960 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1961 I915_WRITE(DSPLINOFF(plane), linear_offset);
1963 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2035 I915_WRITE(reg, dspcntr);
2046 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2050 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2052 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2053 I915_WRITE(DSPLINOFF(plane), linear_offset);
2241 I915_WRITE(reg, temp);
2252 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2260 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2291 I915_WRITE(SOUTH_CHICKEN1, temp);
2315 I915_WRITE(reg, temp);
2326 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2332 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2338 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2339 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2349 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2361 I915_WRITE(reg, temp);
2367 I915_WRITE(reg, temp);
2378 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2412 I915_WRITE(reg, temp);
2427 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2429 I915_WRITE(FDI_RX_MISC(pipe),
2441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2451 I915_WRITE(reg, temp);
2461 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2483 I915_WRITE(reg, temp);
2494 I915_WRITE(reg, temp);
2504 I915_WRITE(reg, temp);
2514 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2544 I915_WRITE(reg, temp);
2562 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2564 I915_WRITE(FDI_RX_MISC(pipe),
2573 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2583 I915_WRITE(reg, temp);
2594 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2609 I915_WRITE(reg, temp);
2615 I915_WRITE(reg, temp);
2625 I915_WRITE(reg, temp);
2635 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2660 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2667 I915_WRITE(reg, temp | FDI_PCDCLK);
2676 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2693 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2698 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2705 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2723 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2730 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2737 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2745 I915_WRITE(reg, temp);
2759 I915_WRITE(reg, temp);
2818 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2888 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2900 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2902 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2904 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2907 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2909 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2911 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2913 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2937 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2962 I915_WRITE(PCH_DPLL_SEL, temp);
3004 I915_WRITE(reg, temp);
3115 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3119 I915_WRITE(PCH_FP0(pll->id), fp);
3120 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3153 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3156 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3157 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3158 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3209 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3283 I915_WRITE(IPS_CTL, IPS_ENABLE);
3295 I915_WRITE(IPS_CTL, 0);
3381 I915_WRITE(PF_CTL(pipe), 0);
3382 I915_WRITE(PF_WIN_POS(pipe), 0);
3383 I915_WRITE(PF_WIN_SZ(pipe), 0);
3438 I915_WRITE(reg, temp);
3443 I915_WRITE(PCH_DPLL_SEL, temp);
3561 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3562 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3564 I915_WRITE(CURCNTR(pipe), cntl);
3565 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3566 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3586 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3587 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3591 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3697 I915_WRITE(PFIT_CONTROL, 0);
4323 I915_WRITE(FP0(pipe), fp);
4328 I915_WRITE(FP1(pipe), fp2);
4331 I915_WRITE(FP1(pipe), fp);
4370 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4371 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4372 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4373 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4385 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4386 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4387 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4388 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4390 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4391 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4392 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4393 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4506 I915_WRITE(DPLL(pipe), dpll);
4515 I915_WRITE(DPLL_MD(pipe), dpll_md);
4593 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4604 I915_WRITE(DPLL(pipe), dpll);
4613 I915_WRITE(DPLL_MD(pipe), dpll_md);
4620 I915_WRITE(DPLL(pipe), dpll);
4657 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4665 I915_WRITE(DPLL(pipe), dpll);
4676 I915_WRITE(DPLL(pipe), dpll);
4706 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4708 I915_WRITE(HTOTAL(cpu_transcoder),
4711 I915_WRITE(HBLANK(cpu_transcoder),
4714 I915_WRITE(HSYNC(cpu_transcoder),
4718 I915_WRITE(VTOTAL(cpu_transcoder),
4721 I915_WRITE(VBLANK(cpu_transcoder),
4724 I915_WRITE(VSYNC(cpu_transcoder),
4734 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4739 I915_WRITE(PIPESRC(pipe),
4843 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4943 I915_WRITE(DSPSIZE(plane),
4946 I915_WRITE(DSPPOS(plane), 0);
4950 I915_WRITE(DSPCNTR(plane), dspcntr);
5127 I915_WRITE(PCH_DREF_CONTROL, val);
5144 I915_WRITE(PCH_DREF_CONTROL, val);
5155 I915_WRITE(PCH_DREF_CONTROL, val);
5166 I915_WRITE(PCH_DREF_CONTROL, val);
5215 I915_WRITE(SOUTH_CHICKEN2, tmp);
5223 I915_WRITE(SOUTH_CHICKEN2, tmp);
5411 I915_WRITE(PIPECONF(pipe), val);
5445 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5446 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5448 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5449 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5451 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5452 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5454 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5455 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5456 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5464 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5465 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5466 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5468 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5475 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5496 I915_WRITE(PIPECONF(cpu_transcoder), val);
5499 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5568 I915_WRITE(SOUTH_CHICKEN1, temp);
5793 I915_WRITE(PCH_DPLL(pll->id), dpll);
5804 I915_WRITE(PCH_DPLL(pll->id), dpll);
5807 I915_WRITE(PCH_FP1(pll->id), fp2);
5809 I915_WRITE(PCH_FP1(pll->id), fp);
5825 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5980 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6122 I915_WRITE(reg_elda, i);
6156 I915_WRITE(G4X_AUD_CNTL_ST, i);
6164 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)(uintptr_t)eld + i));
6168 I915_WRITE(G4X_AUD_CNTL_ST, i);
6196 I915_WRITE(aud_cntrl_st2, tmp);
6205 I915_WRITE(aud_cntrl_st2, tmp);
6214 I915_WRITE(aud_config, tmp);
6224 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6226 I915_WRITE(aud_config, 0);
6236 I915_WRITE(aud_cntrl_st2, i);
6243 I915_WRITE(aud_cntl_st, i);
6250 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)(uintptr_t)(eld + i)));
6254 I915_WRITE(aud_cntrl_st2, i);
6302 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6304 I915_WRITE(aud_config, 0);
6314 I915_WRITE(aud_cntrl_st2, i);
6321 I915_WRITE(aud_cntl_st, i);
6326 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)(uintptr_t)eld + i));
6330 I915_WRITE(aud_cntrl_st2, i);
6390 I915_WRITE(palreg + 4 * i,
6416 I915_WRITE(_CURABASE, base);
6425 I915_WRITE(_CURACNTR, cntl);
6448 I915_WRITE(CURCNTR(pipe), cntl);
6453 I915_WRITE(CURBASE(pipe), base);
6475 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6480 I915_WRITE(CURBASE_IVB(pipe), base);
6531 I915_WRITE(CURPOS_IVB(pipe), pos);
6534 I915_WRITE(CURPOS(pipe), pos);
6626 I915_WRITE(CURSIZE, (height << 12) | width);
7084 I915_WRITE(dpll_reg, dpll);
7120 I915_WRITE(dpll_reg, dpll);
8879 I915_WRITE(reg, val);
8900 I915_WRITE(reg, val);
9587 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9734 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10212 * prevent the next I915_WRITE from detecting it and printing an error