Lines Matching refs:I915_WRITE
394 I915_WRITE(HWS_PGA, addr);
554 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
563 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
567 I915_WRITE(GFX_MODE,
571 I915_WRITE(GFX_MODE_GEN7,
587 I915_WRITE(CACHE_MODE_0,
599 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
842 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
860 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
879 I915_WRITE(IMR, dev_priv->irq_mask);
897 I915_WRITE(IMR, dev_priv->irq_mask);
970 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
976 I915_WRITE(reg,
1046 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1069 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1091 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
1113 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
1615 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1616 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1643 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1662 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,