Lines Matching refs:I915_WRITE
142 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
144 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
145 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
146 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
274 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
283 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
289 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
291 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
294 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
297 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
298 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
302 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
303 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
304 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
305 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
306 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
307 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
308 I915_WRITE(RSTDBYCTL,
311 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
312 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
313 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
314 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
315 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
316 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
317 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
326 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
328 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
330 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
331 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
332 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
333 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
408 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
409 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
410 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
411 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
412 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
413 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
414 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
416 I915_WRITE(IER, dev_priv->regfile.saveIER);
417 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
422 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
425 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
428 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
429 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
432 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);