Disassembler: added AMD-V vmmcall.
DIS: #6249: Cleaned up the code, added some usefull comments.
DIS: #6249: Complex instructions support (like gather) and some fixes. VSIB fix.
DIS: #6249: Added missing 660F38h instructions. Small bug fixes. Unit test updated.
DIS: #6249: Some bug fixes and new testcases. Enabled 0F3A instructions which were accidentally disabled. Added support for 0F3A instruction without prefix.
DIS: #6249: Added missing instructions (starting with 660F3Ah)
DIS: 6251: Added AVX/VEX 3-byte instructions support.
DIS: #6251: AVX / VEX instructions support (two byte instructions only) and some fixes to the other tables.
DIS: #6249: Added missing commands: getsec, movsldup, movddup, movshdup, rcpss
DIS: #6249: Added crc32 Gy, Ew support (with word as operand 2)
DIS: Fixed VMREAD/VMWRITE disassembling, added support for MOVBE, POPCNT, TZCNT, LZCNT, ADCX, ADOX and CRC32 (only CRC32 Gd, Eb & CRC32 Gd, Ey forms).
comment typo
PMOVSKB -> PMOVMSKB; DISOPTYPE_SSE/MMX/FPU.
DIS: *fence todo.
pmulhrwa -> pmulhrw (yasm bug).
Disasm: Fixed operand order of BSF and BSR - dst=reg, src=rm.
DisasmTables.cpp: Fixing the mnemonic for two 3DNow! instruction so yasm groks them.
Fixed g_aTwoByteMapX86_3DNow bug and relaxed assertion in Parse3DNow.
DIS: Dropped most of the little hacks in the groups for dealing with instructions that doesn't actually parse modrm bytes. Only group 7 and the FPU instructions are left with this hack.
-empty lines.
const two pointer tables.
DIS: Reducing the DISCPUMODE even more (200 bytes now) and making it have the same layout in all contexts. This is useful since it's used several places in the VM structure. Also a bunch of other cleanups.
DIS: More cleanups.
DIS: More scoping work.
DIS,DIS-users: Drop the operand/parameter formatting during instruction parsing. The desired formatter can do this afterwards if desired. Should save time + size. (DISCPUSTATE is now 256 bytes here on 64-bit linux, was ~406 yesterday.)
Fixed far call/jmp imm disassembly.
%S -> %s and some other minor cleanups.
DisasmTables.cpp: Added todos for some new instructions.
Automated rebranding to Oracle copyright/license strings via filemuncher
lots under src/VBox: whitespace cleanup.
Nop %Ev disassembly fix
Disassembly tables: missing invalid opcode entry (caused movqdu->movq disassembly errors)
Deal with operand size and mod default values for certain instructions (mov crx, mov drx)
Typo for rdpmc
Added support for three byte opcodes (not complete; just to test invept & invvpid)
Added todo
Swapgs & vmcall added to the tables.
Many fixes for operand sizes (Iv -> Iz)
warnings
For all parameters
Missing IDX_ParseFixedReg
Corrected fstsw to fnstsw. The fstsw mnemonic is assembled into fwait+fnstsw, see the intel manuals (3-432 in Vol. 2A), so the correct name for DF /7 and DF E0 is fnstsw. The disassembler did turn a 9B DF E0 sequence into two instructions like it should, so it's just the mnemonics.
Disassembler updates for 64 bits code
Even more disassembler updates
More disassmbler updates
Updates for disassembling 64 bits instructions
The Big Sun Rebranding Header Change
Disassemble vmread/vmwrite
Fix for ARPL
Started with changes for disassembling 64 bits instructions
disassembler: fix les/lds/lss/lgs/lfs
The Giant CDDL Dual-License Header Change.
Biggest check-in ever. New source code headers for all (C) innotek files.
Marked io instructions as read or write
InnoTek -> innotek: all the headers and comments.
Corrected parameter parsing for LDS, LES, LFS, LGS and LSS instructions
import