DisasmCore.cpp revision 997c47dc1532875eb8e995bf9993dff13071c16f
/* $Id$ */
/** @file
* VBox Disassembler - Core Components.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DIS
#include <VBox/disopcode.h>
#include "DisasmInternal.h"
#include "DisasmTables.h"
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
static int disCoreParseInstr(PDISCPUSTATE pCpu, RTUINTPTR uInstrAddr, const OPCODE *paOneByteMap, uint32_t *pcbInstr);
static unsigned QueryModRM(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc = NULL);
static unsigned QueryModRM_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc = NULL);
static unsigned ParseSIB_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
static void disasmModRMReg(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam, int fRegAddr);
/** @name Parsers
* @{ */
static FNDISPARSE ParseIllegal;
static FNDISPARSE ParseModRM;
static FNDISPARSE ParseModRM_SizeOnly;
static FNDISPARSE UseModRM;
static FNDISPARSE ParseImmByte;
static FNDISPARSE ParseImmByte_SizeOnly;
static FNDISPARSE ParseImmByteSX;
static FNDISPARSE ParseImmByteSX_SizeOnly;
static FNDISPARSE ParseImmBRel;
static FNDISPARSE ParseImmBRel_SizeOnly;
static FNDISPARSE ParseImmUshort;
static FNDISPARSE ParseImmUshort_SizeOnly;
static FNDISPARSE ParseImmV;
static FNDISPARSE ParseImmV_SizeOnly;
static FNDISPARSE ParseImmVRel;
static FNDISPARSE ParseImmVRel_SizeOnly;
static FNDISPARSE ParseImmZ;
static FNDISPARSE ParseImmZ_SizeOnly;
static FNDISPARSE ParseImmAddr;
static FNDISPARSE ParseImmAddr_SizeOnly;
static FNDISPARSE ParseImmAddrF;
static FNDISPARSE ParseImmAddrF_SizeOnly;
static FNDISPARSE ParseFixedReg;
static FNDISPARSE ParseImmUlong;
static FNDISPARSE ParseImmUlong_SizeOnly;
static FNDISPARSE ParseImmQword;
static FNDISPARSE ParseImmQword_SizeOnly;
static FNDISPARSE ParseTwoByteEsc;
static FNDISPARSE ParseThreeByteEsc4;
static FNDISPARSE ParseThreeByteEsc5;
static FNDISPARSE ParseImmGrpl;
static FNDISPARSE ParseShiftGrp2;
static FNDISPARSE ParseGrp3;
static FNDISPARSE ParseGrp4;
static FNDISPARSE ParseGrp5;
static FNDISPARSE Parse3DNow;
static FNDISPARSE ParseGrp6;
static FNDISPARSE ParseGrp7;
static FNDISPARSE ParseGrp8;
static FNDISPARSE ParseGrp9;
static FNDISPARSE ParseGrp10;
static FNDISPARSE ParseGrp12;
static FNDISPARSE ParseGrp13;
static FNDISPARSE ParseGrp14;
static FNDISPARSE ParseGrp15;
static FNDISPARSE ParseGrp16;
static FNDISPARSE ParseModFence;
static FNDISPARSE ParseNopPause;
static FNDISPARSE ParseYv;
static FNDISPARSE ParseYb;
static FNDISPARSE ParseXv;
static FNDISPARSE ParseXb;
/* Floating point parsing */
static FNDISPARSE ParseEscFP;
/** @} */
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/** Parser opcode table for full disassembly. */
{
};
/** Parser opcode table for only calculating instruction size. */
{
};
/**
* Parses one guest instruction.
*
* The result is found in pCpu and pcbInstr.
*
* @returns VBox status code.
* @param pvInstr Address of the instruction to decode. This is a
* real address in the current context that can be
* accessed without faulting. (Consider
* DISInstrWithReader if this isn't the case.)
* @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
* @param pCpu Pointer to cpu structure. Will be initialized.
* @param pcbInstr Where to store the size of the instruction.
* NULL is allowed. This is also stored in
* PDISCPUSTATE::opsize.
*/
DISDECL(int) DISInstr(const void *pvInstr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr)
{
return DISInstEx((uintptr_t)pvInstr, enmCpuMode, DISOPTYPE_ALL, NULL /*pfnReadBytes*/, NULL /*pvUser*/, pCpu, pcbInstr);
}
/**
* Parses one guest instruction.
*
* The result is found in pCpu and pcbInstr.
*
* @returns VBox status code.
* @param uInstrAddr Address of the instruction to decode. What this means
* is left to the pfnReadBytes function.
* @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
* @param pCpu Pointer to cpu structure. Will be initialized.
* @param pcbInstr Where to store the size of the instruction.
* NULL is allowed. This is also stored in
* PDISCPUSTATE::opsize.
*/
DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
{
}
/**
* Disassembles on instruction, details in @a pCpu and length in @a pcbInstr.
*
* @returns VBox status code.
* @param uInstrAddr Address of the instruction to decode. What this means
* is left to the pfnReadBytes function.
* @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param fFilter Instruction type filter.
* @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
* @param pCpu Pointer to CPU structure. With the exception of
* DISCPUSTATE::apvUserData[1] and
* DISCPUSTATE::apvUserData[2], the structure will be
* completely initialized by this API, i.e. no input is
* taken from it.
* @param pcbInstr Where to store the size of the instruction. (This
* is also stored in PDISCPUSTATE::opsize.) Optional.
*/
{
const OPCODE *paOneByteMap;
/*
* Initialize the CPU state.
* Note! The RT_BZERO make ASSUMPTIONS about the placement of apvUserData.
*/
if (enmCpuMode == DISCPUMODE_64BIT)
{
}
else
{
}
}
/**
* Internal worker for DISCoreOne and DISCoreOneEx.
*
* @returns VBox status code.
* @param pCpu Initialized cpu state.
* @param paOneByteMap The one byte opcode map to use.
* @param uInstrAddr Instruction address.
* @param pcbInstr Where to store the instruction size. Can be NULL.
*/
static int disCoreParseInstr(PDISCPUSTATE pCpu, RTUINTPTR uInstrAddr, const OPCODE *paOneByteMap, uint32_t *pcbInstr)
{
/*
* Parse byte by byte.
*/
unsigned iByte = 0;
unsigned cbInc;
for (;;)
{
/* Hardcoded assumption about OP_* values!! */
if (opcode <= OP_LAST_PREFIX)
{
/* The REX prefix must precede the opcode byte(s). Any other placement is ignored. */
{
/** Last prefix byte (for SSE2 extension tables); don't include the REX prefix */
}
switch (opcode)
{
case OP_INVALID:
if (pcbInstr)
// segment override prefix byte
case OP_SEG:
/* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */
{
}
continue; //fetch the next byte
// lock prefix byte
case OP_LOCK:
continue; //fetch the next byte
// address size override prefix byte
case OP_ADDRSIZE:
else
else
continue; //fetch the next byte
// operand size override prefix byte
case OP_OPSIZE:
else
pCpu->opmode = DISCPUMODE_16BIT; /* for 32 and 64 bits mode (there is no 32 bits operand size override prefix) */
continue; //fetch the next byte
// rep and repne are not really prefixes, but we'll treat them as such
case OP_REPE:
continue; //fetch the next byte
case OP_REPNE:
continue; //fetch the next byte
case OP_REX:
/* REX prefix byte */
continue; //fetch the next byte
}
}
break;
}
if (pcbInstr)
}
//*****************************************************************************
//*****************************************************************************
{
int size = 0;
bool fFiltered = false;
// Store the opcode format string for disasmPrintf
#ifndef DIS_CORE_ONLY
#endif
/*
* Apply filter to instruction type to determine if a full disassembly is required.
* Note! Multibyte opcodes are always marked harmless until the final byte.
*/
{
fFiltered = true;
}
else
{
/* Not filtered out -> full disassembly */
}
// Should contain the parameter type on input
/* Correct the operand size if the instruction is marked as forced or default 64 bits */
{
else
}
else
{
/* Forced 32 bits operand size for certain instructions (mov crx, mov drx). */
}
{
}
{
}
{
}
// else simple one byte instruction
return size;
}
//*****************************************************************************
/* Floating point opcode parsing */
//*****************************************************************************
{
int index;
unsigned size = 0;
unsigned ModRM;
if (ModRM <= 0xBF)
{
// Should contain the parameter type on input
}
else
{
}
/*
* Apply filter to instruction type to determine if a full disassembly is required.
* @note Multibyte opcodes are always marked harmless until the final byte.
*/
else
/* Not filtered out -> full disassembly */
/* Correct the operand size if the instruction is marked as forced or default 64 bits */
{
/* Note: redundant, but just in case this ever changes */
else
}
// Little hack to make sure the ModRM byte is included in the returned size
// Store the opcode format string for disasmPrintf
#ifndef DIS_CORE_ONLY
#endif
return size;
}
//*****************************************************************************
// SIB byte: (32 bits mode only)
// 7 - 6 5 - 3 2-0
// Scale Index Base
//*****************************************************************************
static const char *szSIBBaseReg64[16] = {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
static const char *szSIBIndexReg64[16]= {"RAX", "RCX", "RDX", "RBX", NULL, "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
#endif
//*****************************************************************************
{
const char **ppszSIBIndexReg;
const char **ppszSIBBaseReg;
{
}
else
{
}
if (ppszSIBIndexReg[index])
{
if (scale != 0)
{
}
}
{
// [scaled index] + disp32
{
}
else
{ /* sign-extend to 64 bits */
}
}
else
{
}
return; /* Already fetched everything in ParseSIB; no size returned */
}
//*****************************************************************************
//*****************************************************************************
{
unsigned SIB;
{
/* REX.B extends the Base field if not scaled index + disp32 */
}
{
/* Additional 32 bits displacement. No change in long mode. */
}
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseSIB_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
unsigned SIB;
{
/* REX.B extends the Base field. */
/* REX.X extends the Index field. */
}
{
/* Additional 32 bits displacement. No change in long mode. */
}
return size;
}
//*****************************************************************************
// ModR/M byte:
// 7 - 6 5 - 3 2-0
//*****************************************************************************
{
switch (vtype)
{
case OP_PARM_G: //general purpose register
return 0;
default:
if (IS_OP_PARM_RARE(vtype))
{
switch (vtype)
{
case OP_PARM_C: //control register
{
}
else
return 0;
case OP_PARM_D: //debug register
return 0;
case OP_PARM_P: //MMX register
return 0;
case OP_PARM_S: //segment register
return 0;
case OP_PARM_T: //test register
return 0;
case OP_PARM_W: //XMM register or memory operand
if (mod != 3)
break; /* memory operand */
/* else no break */
case OP_PARM_V: //XMM register
return 0;
}
}
}
/* @todo bound */
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
switch (mod)
{
case 0: //effective address
if (rm == 4)
{ /* SIB byte follows ModRM */
}
else
if (rm == 5)
{
/* 32 bits displacement */
{
}
else
{
}
}
else
{ //register address
}
break;
case 1: //effective address + 8 bits displacement
}
else
{
}
break;
case 2: //effective address + 32 bits displacement
}
else
{
}
break;
case 3: //registers
break;
}
}
else
{//16 bits addressing mode
switch (mod)
{
case 0: //effective address
if (rm == 6)
{//16 bits displacement
}
else
{
}
break;
case 1: //effective address + 8 bits displacement
break;
case 2: //effective address + 16 bits displacement
break;
case 3: //registers
break;
}
}
return 0; //everything was already fetched in ParseModRM
}
//*****************************************************************************
// Query the size of the ModRM parameters and fetch the immediate data (if any)
//*****************************************************************************
unsigned QueryModRM(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc)
{
unsigned sibinc;
unsigned size = 0;
// unsigned reg = pCpu->ModRM.Bits.Reg;
if (!pSibInc)
*pSibInc = 0;
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
{ /* SIB byte follows ModRM */
}
switch (mod)
{
case 0: /* Effective address */
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
else
{
/* 16 bits mode */
switch (mod)
{
case 0: /* Effective address */
if (rm == 6) {
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
return size;
}
//*****************************************************************************
// Query the size of the ModRM parameters and fetch the immediate data (if any)
//*****************************************************************************
unsigned QueryModRM_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc)
{
unsigned sibinc;
unsigned size = 0;
// unsigned reg = pCpu->ModRM.Bits.Reg;
if (!pSibInc)
*pSibInc = 0;
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
{ /* SIB byte follows ModRM */
}
switch (mod)
{
case 0: //effective address
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
else
{
/* 16 bits mode */
switch (mod)
{
case 0: //effective address
if (rm == 6) {
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
return size;
}
//*****************************************************************************
//*****************************************************************************
{
AssertFailed();
return 0;
}
//*****************************************************************************
//*****************************************************************************
{
/* Disregard the mod bits for certain instructions (mov crx, mov drx).
*
* From the AMD manual:
* This instruction is always treated as a register-to-register (MOD = 11) instruction, regardless of the
* encoding of the MOD field in the MODR/M byte.
*/
{
/* REX.R extends the Reg field. */
/* REX.B extends the Rm field if there is no SIB byte nor a 32 bits displacement */
&&
{
}
}
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseModRM_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
/* Disregard the mod bits for certain instructions (mov crx, mov drx).
*
* From the AMD manual:
* This instruction is always treated as a register-to-register (MOD = 11) instruction, regardless of the
* encoding of the MOD field in the MODR/M byte.
*/
{
/* REX.R extends the Reg field. */
/* REX.B extends the Rm field if there is no SIB byte nor a 32 bits displacement */
&&
{
}
}
/* UseModRM is not necessary here; we're only interested in the opcode size */
return size;
}
//*****************************************************************************
//*****************************************************************************
{
////AssertMsgFailed(("??\n"));
//nothing to do apparently
return 0;
}
//*****************************************************************************
//*****************************************************************************
{
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmByte_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmByteSX_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
{
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmUshort_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
{
return sizeof(uint32_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmUlong_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint32_t);
}
//*****************************************************************************
//*****************************************************************************
{
return sizeof(uint64_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmQword_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint64_t);
}
//*****************************************************************************
//*****************************************************************************
{
{
return sizeof(uint32_t);
}
{
return sizeof(uint64_t);
}
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmV_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint32_t);
return sizeof(uint64_t);
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
{
/* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */
{
return sizeof(uint16_t);
}
/* 64 bits op mode means *sign* extend to 64 bits. */
{
}
else
{
}
return sizeof(uint32_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmZ_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
/* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */
return sizeof(uint16_t);
return sizeof(uint32_t);
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
{
return sizeof(char);
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
unsigned ParseImmBRel_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(char);
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
{
{
return sizeof(int32_t);
}
{
/* 32 bits relative immediate sign extended to 64 bits. */
return sizeof(int32_t);
}
return sizeof(int16_t);
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
unsigned ParseImmVRel_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(int16_t);
/* Both 32 & 64 bits mode use 32 bits relative immediates. */
return sizeof(int32_t);
}
//*****************************************************************************
//*****************************************************************************
{
{
{
/* far 16:32 pointer */
}
/*
* near 32 bits pointer
*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return sizeof(uint32_t);
}
{
/*
* near 64 bits pointer
*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return sizeof(uint64_t);
}
{
/* far 16:16 pointer */
return sizeof(uint32_t);
}
/*
* near 16 bits pointer
*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmAddr_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
{
{// far 16:32 pointer
}
else
{// near 32 bits pointer
return sizeof(uint32_t);
}
}
{
return sizeof(uint64_t);
}
else
{
{// far 16:16 pointer
return sizeof(uint32_t);
}
else
{// near 16 bits pointer
return sizeof(uint16_t);
}
}
}
//*****************************************************************************
//*****************************************************************************
{
// immediate far pointers - only 16:16 or 16:32; determined by operand, *not* address size!
{
// far 16:32 pointer
}
// far 16:16 pointer
return sizeof(uint32_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmAddrF_SizeOnly(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
// immediate far pointers - only 16:16 or 16:32
{
// far 16:32 pointer
}
else
{
// far 16:16 pointer
return sizeof(uint32_t);
}
}
//*****************************************************************************
//*****************************************************************************
{
/*
* Sets up flags for stored in OPC fixed registers.
*/
{
/* No parameter at all. */
return 0;
}
{
/* 32-bit EAX..EDI registers. */
{
/* Use 32-bit registers. */
}
else
{
/* Use 64-bit registers. */
}
else
{
/* Use 16-bit registers. */
}
}
else
{
/* Segment ES..GS registers. */
}
else
{
/* 16-bit AX..DI registers. */
}
else
{
/* 8-bit AL..DL, AH..DH registers. */
{
}
}
else
{
/* FPU registers. */
}
/* else - not supported for now registers. */
return 0;
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
{
/* 2nd byte */
/* default to the non-prefixed table. */
/* Handle opcode table extensions that rely on the address, repe or repne prefix byte. */
/** @todo Should we take the first or last prefix byte in case of multiple prefix bytes??? */
if (pCpu->lastprefix)
{
switch (pCpu->lastprefix)
{
case OP_OPSIZE: /* 0x66 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
case OP_REPNE: /* 0xF2 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
case OP_REPE: /* 0xF3 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
}
}
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseThreeByteEsc4(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
/* 3rd byte */
/* default to the non-prefixed table. */
{
}
else
pOpcode = &g_InvalidOpcode[0];
/* Handle opcode table extensions that rely on the address, repne prefix byte. */
/** @todo Should we take the first or last prefix byte in case of multiple prefix bytes??? */
switch (pCpu->lastprefix)
{
case OP_OPSIZE: /* 0x66 */
{
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
}
break;
case OP_REPNE: /* 0xF2 */
{
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
}
break;
}
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseThreeByteEsc5(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
/* 3rd byte */
/** @todo Should we take the first or last prefix byte in case of multiple prefix bytes??? */
/* default to the non-prefixed table. */
{
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
}
else
pOpcode = &g_InvalidOpcode[0];
return size;
}
//*****************************************************************************
//*****************************************************************************
{
unsigned size = 0;
{
}
else
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
int idx;
{
case 0xC0:
case 0xC1:
break;
case 0xD0:
case 0xD1:
case 0xD2:
case 0xD3:
break;
default:
AssertMsgFailed(("Oops\n"));
return sizeof(uint8_t);
}
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
// 0xF 0xF [ModRM] [SIB] [displacement] imm8_opcode
// It would appear the ModRM byte must always be present. How else can you
// determine the offset of the imm8_opcode byte otherwise?
//
//*****************************************************************************
{
#ifdef DEBUG_Sander
//needs testing
AssertMsgFailed(("Test me\n"));
#endif
//little hack to make sure the ModRM byte is included in the returned size
{
#ifdef DEBUG_Sander /* bird, 2005-06-28: Alex is getting this during full installation of win2ksp4. */
#endif
}
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
else
else
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
else
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
static const char *szModRMReg8[] = {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "SPL", "BPL", "SIL", "DIL"};
static const char *szModRMReg16[] = {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W"};
static const char *szModRMReg32[] = {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D"};
static const char *szModRMReg64[] = {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
static const char *szModRMReg1616[8] = {"BX+SI", "BX+DI", "BP+SI", "BP+DI", "SI", "DI", "BP", "BX"};
#endif
static const int BaseModRMReg16[8] = { USE_REG_BX, USE_REG_BX, USE_REG_BP, USE_REG_BP, USE_REG_SI, USE_REG_DI, USE_REG_BP, USE_REG_BX};
//*****************************************************************************
static void disasmModRMReg(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam, int fRegAddr)
{
if (fRegAddr)
else
{
{
case DISCPUMODE_32BIT:
break;
case DISCPUMODE_64BIT:
break;
case DISCPUMODE_16BIT:
break;
default:
/* make gcc happy */
break;
}
}
switch (subtype)
{
case OP_PARM_b:
/* AH, BH, CH & DH map to DIL, SIL, EBL & SPL when a rex prefix is present. */
/* Intel� 64 and IA-32 Architectures Software Developer�s Manual: 3.4.1.1 */
&& idx >= USE_REG_AH
&& idx <= USE_REG_BH)
{
}
break;
case OP_PARM_w:
break;
case OP_PARM_d:
break;
case OP_PARM_q:
break;
default:
break;
}
}
//*****************************************************************************
//*****************************************************************************
{
if (idx < 4)
{
}
}
//*****************************************************************************
//*****************************************************************************
{
{
return;
}
}
/**
* Slow path for storing instruction bytes.
*
* @param pCpu The disassembler state.
* @param uAddress The address.
* @param pbSrc The bytes.
* @param cbSrc The number of bytes.
*/
DECL_NO_INLINE(static, void)
{
/*
* Figure out which case it is.
*/
{
{
return; /* fully re-reading old stuff. */
}
/* Only partially re-reading stuff, skip ahead and add the rest. */
pbSrc += cbAlreadyRead;
cbSrc -= cbAlreadyRead;
}
{
/* The instruction is too long! This shouldn't happen. */
AssertMsgFailed(("%RTptr LB %zx off=%RTptr (%.*Rhxs)", uAddress, cbSrc, off, cbInstr, pCpu->abInstr));
return;
}
{
/* Mind the gap - this shouldn't happen, but read the gap bytes if it does. */
AssertMsgFailed(("%RTptr LB %zx off=%RTptr (%.16Rhxs)", uAddress, cbSrc, off, cbInstr, pCpu->abInstr));
if (RT_FAILURE(rc))
{
}
}
/*
* Copy the bytes.
*/
{
}
else
{
AssertMsgFailed(("%RTptr LB %zx off=%RTptr (%.*Rhxs)", uAddress, cbSrc, off, sizeof(pCpu->abInstr), pCpu->abInstr));
}
}
DECLCALLBACK(int) disReadBytesDefault(PDISCPUSTATE pCpu, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead)
{
#ifdef IN_RING0
AssertMsgFailed(("DISReadWord with no read callback in ring 0!!\n"));
return VERR_DIS_NO_READ_CALLBACK;
#else
return VINF_SUCCESS;
#endif
}
//*****************************************************************************
/* Read functions for getting the opcode bytes */
//*****************************************************************************
{
if (RT_FAILURE(rc))
{
Log(("DISReadByte failed!!\n"));
}
/** @todo change this into reading directly into abInstr and use it as a
* cache. */
else
return bTemp;
}
//*****************************************************************************
//*****************************************************************************
{
uTemp.u = 0;
if (RT_FAILURE(rc))
{
Log(("DISReadWord failed!!\n"));
}
{
}
else
return uTemp.u;
}
//*****************************************************************************
//*****************************************************************************
{
uTemp.u = 0;
if (RT_FAILURE(rc))
{
Log(("DISReadDWord failed!!\n"));
}
{
}
else
return uTemp.u;
}
//*****************************************************************************
//*****************************************************************************
{
uTemp.u = 0;
if (RT_FAILURE(rc))
{
}
{
}
else
return uTemp.u;
}
/**
* Validates the lock sequence.
*
* The AMD manual lists the following instructions:
* ADC
* ADD
* AND
* BTC
* BTR
* BTS
* CMPXCHG
* CMPXCHG8B
* CMPXCHG16B
* DEC
* INC
* NEG
* NOT
* OR
* SBB
* SUB
* XADD
* XCHG
* XOR
*
* @param pCpu Fully disassembled instruction.
*/
{
/*
* Filter out the valid lock sequences.
*/
{
/* simple: no variations */
case OP_CMPXCHG8B: /* == OP_CMPXCHG16B? */
return;
/* simple: /r - reject register destination. */
case OP_BTC:
case OP_BTR:
case OP_BTS:
case OP_CMPXCHG:
case OP_XADD:
break;
return;
/*
* Lots of variants but its sufficient to check that param 1
* is a memory operand.
*/
case OP_ADC:
case OP_ADD:
case OP_AND:
case OP_DEC:
case OP_INC:
case OP_NEG:
case OP_NOT:
case OP_OR:
case OP_SBB:
case OP_SUB:
case OP_XCHG:
case OP_XOR:
if (pCpu->param1.flags & (DISUSE_BASE | DISUSE_INDEX | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT8 | DISUSE_RIPDISPLACEMENT32))
return;
break;
default:
break;
}
/*
* Invalid lock sequence, make it a OP_ILLUD2.
*/
}