DisasmCore.cpp revision 9fddb5277c67fe4db6da1c96c4cb2605c1fcb828
/* $Id$ */
/** @file
* VBox Disassembler - Core Components.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DIS
#include <VBox/disopcode.h>
#include "DisasmInternal.h"
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** This must be less or equal to DISSTATE::abInstr.
* See Vol3A/Table 6-2 and Vol3B/Section22.25 for instance. */
#define DIS_MAX_INSTR_LENGTH 15
/** Whether we can do unaligned access. */
#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
# define DIS_HOST_UNALIGNED_ACCESS_OK
#endif
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/** @name Parsers
* @{ */
static FNDISPARSE ParseIllegal;
static FNDISPARSE ParseModRM;
static FNDISPARSE ParseModRM_SizeOnly;
static FNDISPARSE UseModRM;
static FNDISPARSE ParseImmByte;
static FNDISPARSE ParseImmByte_SizeOnly;
static FNDISPARSE ParseImmByteSX;
static FNDISPARSE ParseImmByteSX_SizeOnly;
static FNDISPARSE ParseImmBRel;
static FNDISPARSE ParseImmBRel_SizeOnly;
static FNDISPARSE ParseImmUshort;
static FNDISPARSE ParseImmUshort_SizeOnly;
static FNDISPARSE ParseImmV;
static FNDISPARSE ParseImmV_SizeOnly;
static FNDISPARSE ParseImmVRel;
static FNDISPARSE ParseImmVRel_SizeOnly;
static FNDISPARSE ParseImmZ;
static FNDISPARSE ParseImmZ_SizeOnly;
static FNDISPARSE ParseImmAddr;
static FNDISPARSE ParseImmAddr_SizeOnly;
static FNDISPARSE ParseImmAddrF;
static FNDISPARSE ParseImmAddrF_SizeOnly;
static FNDISPARSE ParseFixedReg;
static FNDISPARSE ParseImmUlong;
static FNDISPARSE ParseImmUlong_SizeOnly;
static FNDISPARSE ParseImmQword;
static FNDISPARSE ParseImmQword_SizeOnly;
static FNDISPARSE ParseInvOpModRm;
static FNDISPARSE ParseTwoByteEsc;
static FNDISPARSE ParseThreeByteEsc4;
static FNDISPARSE ParseThreeByteEsc5;
static FNDISPARSE ParseImmGrpl;
static FNDISPARSE ParseShiftGrp2;
static FNDISPARSE ParseGrp3;
static FNDISPARSE ParseGrp4;
static FNDISPARSE ParseGrp5;
static FNDISPARSE Parse3DNow;
static FNDISPARSE ParseGrp6;
static FNDISPARSE ParseGrp7;
static FNDISPARSE ParseGrp8;
static FNDISPARSE ParseGrp9;
static FNDISPARSE ParseGrp10;
static FNDISPARSE ParseGrp12;
static FNDISPARSE ParseGrp13;
static FNDISPARSE ParseGrp14;
static FNDISPARSE ParseGrp15;
static FNDISPARSE ParseGrp16;
static FNDISPARSE ParseModFence;
static FNDISPARSE ParseNopPause;
static FNDISPARSE ParseYv;
static FNDISPARSE ParseYb;
static FNDISPARSE ParseXv;
static FNDISPARSE ParseXb;
/** Floating point parsing */
static FNDISPARSE ParseEscFP;
/** @} */
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/** Parser opcode table for full disassembly. */
{
};
/** Parser opcode table for only calculating instruction size. */
{
};
/********************************************************************************************************************************
*
*
* Read functions for getting the opcode bytes
*
*
********************************************************************************************************************************/
/**
* @interface_method_impl{FNDISREADBYTES, The default byte reader callber.}
*/
static DECLCALLBACK(int) disReadBytesDefault(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
{
#ifdef IN_RING0
AssertMsgFailed(("disReadWord with no read callback in ring 0!!\n"));
return VERR_DIS_NO_READ_CALLBACK;
#else
: cbLeftOnPage <= cbMinRead
: (uint8_t)cbLeftOnPage;
return VINF_SUCCESS;
#endif
}
/**
* Read more bytes into the DISSTATE::abInstr buffer, advance
* DISSTATE::cbCachedInstr.
*
* Will set DISSTATE::rc on failure, but still advance cbCachedInstr.
*
* The caller shall fend off reads beyond the DISSTATE::abInstr buffer.
*
* @param pDis The disassembler state.
* @param offInstr The offset of the read request.
* @param cbMin The size of the read request that needs to be
* satisfied.
*/
{
/*
* Adjust the incoming request to not overlap with bytes that has already
* been read and to make sure we don't leave unread gaps.
*/
{
}
{
}
/*
* Do the read.
* (No need to zero anything on failure as abInstr is already zeroed by the
* DISInstrEx API.)
*/
if (RT_SUCCESS(rc))
{
}
else
{
}
}
/**
* Function for handling a 8-bit cache miss.
*
* @returns The requested byte.
* @param pDis The disassembler state.
* @param offInstr The offset of the byte relative to the
* instruction.
*/
{
{
Log(("disReadByte: too long instruction...\n"));
if (cbLeft > 0)
return 0;
}
}
/**
* Read a byte (8-bit) instruction.
*
* @returns The requested byte.
* @param pDis The disassembler state.
* @param uAddress The address.
*/
{
}
/**
* Function for handling a 16-bit cache miss.
*
* @returns The requested word.
* @param pDis The disassembler state.
* @param offInstr The offset of the word relative to the
* instruction.
*/
{
{
Log(("disReadWord: too long instruction...\n"));
switch (cbLeft)
{
case 1:
default:
if (cbLeft >= 2)
return 0;
}
}
#ifdef DIS_HOST_UNALIGNED_ACCESS_OK
#else
#endif
}
/**
* Read a word (16-bit) instruction.
*
* @returns The requested word.
* @param pDis The disassembler state.
* @param offInstr The offset of the qword relative to the
* instruction.
*/
{
#ifdef DIS_HOST_UNALIGNED_ACCESS_OK
#else
#endif
}
/**
* Function for handling a 32-bit cache miss.
*
* @returns The requested dword.
* @param pDis The disassembler state.
* @param offInstr The offset of the dword relative to the
* instruction.
*/
{
{
Log(("disReadDWord: too long instruction...\n"));
switch (cbLeft)
{
case 1:
case 2:
case 3:
return RT_MAKE_U32_FROM_U8(pDis->abInstr[offInstr], pDis->abInstr[offInstr + 1], pDis->abInstr[offInstr + 2], 0);
default:
if (cbLeft >= 4)
return 0;
}
}
#ifdef DIS_HOST_UNALIGNED_ACCESS_OK
#else
#endif
}
/**
* Read a dword (32-bit) instruction.
*
* @returns The requested dword.
* @param pDis The disassembler state.
* @param offInstr The offset of the qword relative to the
* instruction.
*/
{
#ifdef DIS_HOST_UNALIGNED_ACCESS_OK
#else
#endif
}
/**
* Function for handling a 64-bit cache miss.
*
* @returns The requested qword.
* @param pDis The disassembler state.
* @param offInstr The offset of the qword relative to the
* instruction.
*/
{
{
Log(("disReadQWord: too long instruction...\n"));
switch (cbLeft)
{
case 1:
case 2:
case 3:
case 4:
0, 0, 0, 0);
case 5:
case 6:
0, 0);
case 7:
default:
if (cbLeft >= 8)
return 0;
}
}
#ifdef DIS_HOST_UNALIGNED_ACCESS_OK
#else
#endif
}
/**
* Read a qword (64-bit) instruction.
*
* @returns The requested qword.
* @param pDis The disassembler state.
* @param uAddress The address.
*/
{
#ifdef DIS_HOST_UNALIGNED_ACCESS_OK
#else
#endif
}
//*****************************************************************************
//*****************************************************************************
{
// Store the opcode format string for disasmPrintf
/*
* Apply filter to instruction type to determine if a full disassembly is required.
* Note! Multibyte opcodes are always marked harmless until the final byte.
*/
bool fFiltered;
{
fFiltered = true;
}
else
{
/* Not filtered out -> full disassembly */
fFiltered = false;
}
// Should contain the parameter type on input
/* Correct the operand size if the instruction is marked as forced or default 64 bits */
{
else
}
else
{
/* Forced 32 bits operand size for certain instructions (mov crx, mov drx). */
}
{
}
{
}
{
}
// else simple one byte instruction
return offInstr;
}
//*****************************************************************************
/* Floating point opcode parsing */
//*****************************************************************************
{
if (ModRM <= 0xBF)
{
// Should contain the parameter type on input
}
else
{
}
/*
* Apply filter to instruction type to determine if a full disassembly is required.
* @note Multibyte opcodes are always marked harmless until the final byte.
*/
else
/* Not filtered out -> full disassembly */
/* Correct the operand size if the instruction is marked as forced or default 64 bits */
{
/* Note: redundant, but just in case this ever changes */
else
}
// Little hack to make sure the ModRM byte is included in the returned size
offInstr++; //ModRM byte
return offInstr;
}
/********************************************************************************************************************************
*
*
* SIB byte: (not 16-bit mode)
* 7 - 6 5 - 3 2-0
* Scale Index Base
*
*
********************************************************************************************************************************/
{
unsigned regtype;
else
if (index != 4)
{
if (scale != 0)
{
}
}
{
// [scaled index] + disp32
{
}
else
{ /* sign-extend to 64 bits */
}
}
else
{
}
return; /* Already fetched everything in ParseSIB; no size returned */
}
{
offInstr++;
{
/* REX.B extends the Base field if not scaled index + disp32 */
}
{
/* Additional 32 bits displacement. No change in long mode. */
offInstr += 4;
}
return offInstr;
}
static size_t ParseSIB_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
offInstr++;
{
/* REX.B extends the Base field. */
/* REX.X extends the Index field. */
}
{
/* Additional 32 bits displacement. No change in long mode. */
offInstr += 4;
}
return offInstr;
}
/********************************************************************************************************************************
*
*
* ModR/M byte:
* 7 - 6 5 - 3 2-0
*
*
********************************************************************************************************************************/
static void disasmModRMReg(unsigned idx, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam, int fRegAddr)
{
if (fRegAddr)
else
{
{
case DISCPUMODE_32BIT:
break;
case DISCPUMODE_64BIT:
break;
case DISCPUMODE_16BIT:
break;
default:
/* make gcc happy */
break;
}
}
switch (subtype)
{
case OP_PARM_b:
/* AH, BH, CH & DH map to DIL, SIL, EBL & SPL when a rex prefix is present. */
/* Intel� 64 and IA-32 Architectures Software Developer�s Manual: 3.4.1.1 */
&& idx >= DISGREG_AH
&& idx <= DISGREG_BH)
{
}
break;
case OP_PARM_w:
break;
case OP_PARM_d:
break;
case OP_PARM_q:
break;
default:
break;
}
}
{
if (idx < 4)
{
}
}
{
if (idx >= DISSELREG_END)
{
return;
}
}
{
switch (vtype)
{
case OP_PARM_G: //general purpose register
return offInstr;
default:
if (IS_OP_PARM_RARE(vtype))
{
switch (vtype)
{
case OP_PARM_C: //control register
{
}
else
return offInstr;
case OP_PARM_D: //debug register
return offInstr;
case OP_PARM_Q: //MMX or memory operand
if (mod != 3)
break; /* memory operand */
/* else no break */
case OP_PARM_P: //MMX register
return offInstr;
case OP_PARM_S: //segment register
return offInstr;
case OP_PARM_T: //test register
return offInstr;
case OP_PARM_W: //XMM register or memory operand
if (mod != 3)
break; /* memory operand */
/* else no break */
case OP_PARM_V: //XMM register
return offInstr;
}
}
}
/** @todo bound */
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
switch (mod)
{
case 0: //effective address
else
if (rm == 5)
{
/* 32 bits displacement */
{
}
else
{
}
}
else
{ //register address
}
break;
case 1: //effective address + 8 bits displacement
else
{
}
break;
case 2: //effective address + 32 bits displacement
else
{
}
break;
case 3: //registers
break;
}
}
else
{//16 bits addressing mode
switch (mod)
{
case 0: //effective address
if (rm == 6)
{//16 bits displacement
}
else
{
}
break;
case 1: //effective address + 8 bits displacement
break;
case 2: //effective address + 16 bits displacement
break;
case 3: //registers
break;
}
}
return offInstr;
}
//*****************************************************************************
// Query the size of the ModRM parameters and fetch the immediate data (if any)
//*****************************************************************************
{
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
switch (mod)
{
case 0: /* Effective address */
{
offInstr += 4;
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
offInstr++;
break;
case 2: /* Effective address + 32 bits displacement */
offInstr += 4;
break;
case 3: /* registers */
break;
}
}
else
{
/* 16 bits mode */
switch (mod)
{
case 0: /* Effective address */
if (rm == 6)
{
offInstr += 2;
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
offInstr++;
break;
case 2: /* Effective address + 32 bits displacement */
offInstr += 2;
break;
case 3: /* registers */
break;
}
}
return offInstr;
}
//*****************************************************************************
// Parse the ModRM parameters and fetch the immediate data (if any)
//*****************************************************************************
static size_t QueryModRM_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
{ /* SIB byte follows ModRM */
}
switch (mod)
{
case 0: //effective address
offInstr += 4;
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
offInstr += 1;
break;
case 2: /* Effective address + 32 bits displacement */
offInstr += 4;
break;
case 3: /* registers */
break;
}
}
else
{
/* 16 bits mode */
switch (mod)
{
case 0: //effective address
if (rm == 6)
offInstr += 2;
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
offInstr++;
break;
case 2: /* Effective address + 32 bits displacement */
offInstr += 2;
break;
case 3: /* registers */
break;
}
}
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
AssertFailed();
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
offInstr++;
/* Disregard the mod bits for certain instructions (mov crx, mov drx).
*
* From the AMD manual:
* This instruction is always treated as a register-to-register (MOD = 11) instruction, regardless of the
* encoding of the MOD field in the MODR/M byte.
*/
{
/* REX.R extends the Reg field. */
/* REX.B extends the Rm field if there is no SIB byte nor a 32 bits displacement */
&&
{
}
}
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseModRM_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
offInstr++;
/* Disregard the mod bits for certain instructions (mov crx, mov drx).
*
* From the AMD manual:
* This instruction is always treated as a register-to-register (MOD = 11) instruction, regardless of the
* encoding of the MOD field in the MODR/M byte.
*/
{
/* REX.R extends the Reg field. */
/* REX.B extends the Rm field if there is no SIB byte nor a 32 bits displacement */
&&
{
}
}
/* UseModRM is not necessary here; we're only interested in the opcode size */
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
return offInstr + 1;
}
//*****************************************************************************
//*****************************************************************************
{
return offInstr + 1;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmByte_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 1;
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return offInstr + 1;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmByteSX_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 1;
}
//*****************************************************************************
//*****************************************************************************
{
return offInstr + 2;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmUshort_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 2;
}
//*****************************************************************************
//*****************************************************************************
{
return offInstr + 4;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmUlong_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 4;
}
//*****************************************************************************
//*****************************************************************************
{
return offInstr + 8;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmQword_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 8;
}
//*****************************************************************************
//*****************************************************************************
{
{
return offInstr + 4;
}
{
return offInstr + 8;
}
return offInstr + 2;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmV_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 4;
return offInstr + 8;
return offInstr + 2;
}
//*****************************************************************************
//*****************************************************************************
{
/* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */
{
return offInstr + 2;
}
/* 64 bits op mode means *sign* extend to 64 bits. */
{
}
else
{
}
return offInstr + 4;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmZ_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
/* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */
return offInstr + 2;
return offInstr + 4;
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
{
return offInstr + 1;
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
static size_t ParseImmBRel_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 1;
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
{
{
return offInstr + 4;
}
{
/* 32 bits relative immediate sign extended to 64 bits. */
return offInstr + 4;
}
return offInstr + 2;
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
static size_t ParseImmVRel_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
return offInstr + 2;
/* Both 32 & 64 bits mode use 32 bits relative immediates. */
return offInstr + 4;
}
//*****************************************************************************
//*****************************************************************************
{
{
{
/* far 16:32 pointer */
}
/*
* near 32 bits pointer
*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return offInstr + 4;
}
{
/*
* near 64 bits pointer
*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return offInstr + 8;
}
{
/* far 16:16 pointer */
return offInstr + 4;
}
/*
* near 16 bits pointer
*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return offInstr + 2;
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmAddr_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
{
}
{
return offInstr + 8;
}
}
//*****************************************************************************
//*****************************************************************************
{
// immediate far pointers - only 16:16 or 16:32; determined by operand, *not* address size!
{
// far 16:32 pointer
}
// far 16:16 pointer
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseImmAddrF_SizeOnly(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
// immediate far pointers - only 16:16 or 16:32
}
//*****************************************************************************
//*****************************************************************************
{
/*
* Sets up flags for stored in OPC fixed registers.
*/
{
/* No parameter at all. */
return offInstr;
}
{
/* 32-bit EAX..EDI registers. */
{
/* Use 32-bit registers. */
}
{
/* Use 64-bit registers. */
}
else
{
/* Use 16-bit registers. */
}
{
}
}
{
/* Segment ES..GS registers. */
}
{
/* 16-bit AX..DI registers. */
}
{
/* 8-bit AL..DL, AH..DH registers. */
{
}
}
{
/* FPU registers. */
}
/* else - not supported for now registers. */
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
{
}
else
{
}
return offInstr;
}
//*****************************************************************************
//*****************************************************************************
{
/* This is used to avoid a bunch of special hacks to get the ModRM byte
included when encountering invalid opcodes in groups. */
return offInstr + 1;
}
//*****************************************************************************
//*****************************************************************************
{
/* 2nd byte */
offInstr++;
/* default to the non-prefixed table. */
/* Handle opcode table extensions that rely on the address, repe or repne prefix byte. */
/** @todo Should we take the first or last prefix byte in case of multiple prefix bytes??? */
if (pDis->bLastPrefix)
{
switch (pDis->bLastPrefix)
{
case OP_OPSIZE: /* 0x66 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
{
}
else
}
break;
case OP_REPNE: /* 0xF2 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
case OP_REPE: /* 0xF3 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
}
}
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseThreeByteEsc4(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
/* 3rd byte */
offInstr++;
/* default to the non-prefixed table. */
{
}
else
pOpcode = &g_InvalidOpcode[0];
/* Handle opcode table extensions that rely on the address, repne prefix byte. */
/** @todo Should we take the first or last prefix byte in case of multiple prefix bytes??? */
switch (pDis->bLastPrefix)
{
case OP_OPSIZE: /* 0x66 */
{
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
{
}
else
}
}
break;
case OP_REPNE: /* 0xF2 */
{
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
}
break;
case OP_REPE: /* 0xF3 */
{
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
}
}
}
//*****************************************************************************
//*****************************************************************************
static size_t ParseThreeByteEsc5(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam)
{
/* 3rd byte */
offInstr++;
/** @todo Should we take the first or last prefix byte in case of multiple prefix bytes??? */
/* default to the non-prefixed table. */
{
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
{
}
else
}
}
else
pOpcode = &g_InvalidOpcode[0];
}
//*****************************************************************************
//*****************************************************************************
{
{
}
else
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
unsigned idx;
{
case 0xC0:
case 0xC1:
break;
case 0xD0:
case 0xD1:
case 0xD2:
case 0xD3:
break;
default:
return offInstr;
}
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
// 0xF 0xF [ModRM] [SIB] [displacement] imm8_opcode
// It would appear the ModRM byte must always be present. How else can you
// determine the offset of the imm8_opcode byte otherwise?
//
//*****************************************************************************
{
/** @todo This code needs testing! Esp. wrt invalid opcodes. */
offRet++;
return offRet;
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
else
else
/* Cannot easily skip this hack because of monitor and vmcall! */
//little hack to make sure the ModRM byte is included in the returned size
offInstr++;
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
else
}
//*****************************************************************************
//*****************************************************************************
{
}
/**
* Validates the lock sequence.
*
* The AMD manual lists the following instructions:
* ADC
* ADD
* AND
* BTC
* BTR
* BTS
* CMPXCHG
* CMPXCHG8B
* CMPXCHG16B
* DEC
* INC
* NEG
* NOT
* OR
* SBB
* SUB
* XADD
* XCHG
* XOR
*
* @param pDis Fully disassembled instruction.
*/
{
/*
* Filter out the valid lock sequences.
*/
{
/* simple: no variations */
case OP_CMPXCHG8B: /* == OP_CMPXCHG16B? */
return;
/* simple: /r - reject register destination. */
case OP_BTC:
case OP_BTR:
case OP_BTS:
case OP_CMPXCHG:
case OP_XADD:
break;
return;
/*
* Lots of variants but its sufficient to check that param 1
* is a memory operand.
*/
case OP_ADC:
case OP_ADD:
case OP_AND:
case OP_DEC:
case OP_INC:
case OP_NEG:
case OP_NOT:
case OP_OR:
case OP_SBB:
case OP_SUB:
case OP_XCHG:
case OP_XOR:
return;
break;
default:
break;
}
/*
* Invalid lock sequence, make it a OP_ILLUD2.
*/
}
/**
* Internal worker for DISInstrEx and DISInstrWithPrefetchedBytes.
*
* @returns VBox status code.
* @param pDis Initialized disassembler state.
* @param paOneByteMap The one byte opcode map to use.
* @param pcbInstr Where to store the instruction size. Can be NULL.
*/
{
/*
* Parse byte by byte.
*/
for (;;)
{
/* Hardcoded assumption about OP_* values!! */
if (opcode <= OP_LAST_PREFIX)
{
/* The REX prefix must precede the opcode byte(s). Any other placement is ignored. */
{
/* Last prefix byte (for SSE2 extension tables); don't include the REX prefix */
}
switch (opcode)
{
case OP_INVALID:
if (pcbInstr)
// segment override prefix byte
case OP_SEG:
#if 0 /* Try be accurate in our reporting, shouldn't break anything... :-) */
/* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */
#else
#endif
continue; //fetch the next byte
// lock prefix byte
case OP_LOCK:
continue; //fetch the next byte
// address size override prefix byte
case OP_ADDRSIZE:
else
else
continue; //fetch the next byte
// operand size override prefix byte
case OP_OPSIZE:
else
pDis->uOpMode = DISCPUMODE_16BIT; /* for 32 and 64 bits mode (there is no 32 bits operand size override prefix) */
continue; //fetch the next byte
// rep and repne are not really prefixes, but we'll treat them as such
case OP_REPE:
continue; //fetch the next byte
case OP_REPNE:
continue; //fetch the next byte
case OP_REX:
/* REX prefix byte */
continue; //fetch the next byte
}
}
/* first opcode byte. */
break;
}
if (pcbInstr)
}
/**
* Inlined worker that initializes the disassembler state.
*
* @returns The primary opcode map to use.
* @param pDis The disassembler state.
* @param uInstrAddr The instruction address.
* @param enmCpuMode The CPU mode.
* @param fFilter The instruction filter settings.
* @param pfnReadBytes The byte reader, can be NULL.
* @param pvUser The the user data for the reader.
*/
{
#ifdef VBOX_STRICT /* poison */
#endif
if (enmCpuMode == DISCPUMODE_64BIT)
{
}
else
{
}
return paOneByteMap;
}
/**
* Reads some bytes into the cache.
*
* While this will set DISSTATE::rc on failure, the caller should disregard
* this since that is what would happen if we didn't prefetch bytes prior to the
* instruction parsing.
*
* @param pDis The disassembler state.
*/
{
/*
* Read some bytes into the cache. (If this fail we continue as nothing
* has gone wrong since this is what would happen if we didn't precharge
* the cache here.)
*/
if (RT_SUCCESS(rc))
{
}
else
{
}
}
/**
* Disassembles on instruction, details in @a pDis and length in @a pcbInstr.
*
* @returns VBox status code.
* @param uInstrAddr Address of the instruction to decode. What this means
* is left to the pfnReadBytes function.
* @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param fFilter Instruction type filter.
* @param pvUser User argument for the instruction reader. (Ends up in pvUser.)
* @param pDis Pointer to disassembler state (output).
* @param pcbInstr Where to store the size of the instruction. (This
* is also stored in PDISSTATE::cbInstr.) Optional.
*/
{
PCDISOPCODE paOneByteMap = disInitializeState(pDis, uInstrAddr, enmCpuMode, fFilter, pfnReadBytes, pvUser);
}
/**
* Disassembles on instruction partially or fully from prefetched bytes, details
* in @a pDis and length in @a pcbInstr.
*
* @returns VBox status code.
* @param uInstrAddr Address of the instruction to decode. What this means
* is left to the pfnReadBytes function.
* @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT.
* @param pvPrefetched Pointer to the prefetched bytes.
* @param cbPrefetched The number of valid bytes pointed to by @a
* pbPrefetched.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param fFilter Instruction type filter.
* @param pvUser User argument for the instruction reader. (Ends up in pvUser.)
* @param pDis Pointer to disassembler state (output).
* @param pcbInstr Where to store the size of the instruction. (This
* is also stored in PDISSTATE::cbInstr.) Optional.
*/
DISDECL(int) DISInstrWithPrefetchedBytes(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t fFilter,
{
PCDISOPCODE paOneByteMap = disInitializeState(pDis, uInstrAddr, enmCpuMode, fFilter, pfnReadBytes, pvUser);
if (!cbPretched)
else
{
{
}
else
{
}
}
}
/**
* Parses one guest instruction.
*
* The result is found in pDis and pcbInstr.
*
* @returns VBox status code.
* @param uInstrAddr Address of the instruction to decode. What this means
* is left to the pfnReadBytes function.
* @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param pvUser User argument for the instruction reader. (Ends up in pvUser.)
* @param pDis Pointer to disassembler state (output).
* @param pcbInstr Where to store the size of the instruction.
* NULL is allowed. This is also stored in
* PDISSTATE::cbInstr.
*/
DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
{
}
/**
* Parses one guest instruction.
*
* The result is found in pDis and pcbInstr.
*
* @returns VBox status code.
* @param pvInstr Address of the instruction to decode. This is a
* real address in the current context that can be
* accessed without faulting. (Consider
* DISInstrWithReader if this isn't the case.)
* @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param pvUser User argument for the instruction reader. (Ends up in pvUser.)
* @param pDis Pointer to disassembler state (output).
* @param pcbInstr Where to store the size of the instruction.
* NULL is allowed. This is also stored in
* PDISSTATE::cbInstr.
*/
DISDECL(int) DISInstr(const void *pvInstr, DISCPUMODE enmCpuMode, PDISSTATE pDis, uint32_t *pcbInstr)
{
return DISInstrEx((uintptr_t)pvInstr, enmCpuMode, DISOPTYPE_ALL, NULL /*pfnReadBytes*/, NULL /*pvUser*/, pDis, pcbInstr);
}