HWSVMR0.cpp revision e64031e20c39650a7bc902a3e1aba613b9415dee
/* $Id$ */
/** @file
* HWACCM SVM - Host Context Ring 0.
*/
/*
* Copyright (C) 2006-2007 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HWACCM
#include "HWACCMInternal.h"
#include <VBox/hwacc_svm.h>
#include <VBox/disopcode.h>
#endif
#include "HWSVMR0.h"
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/**
* Sets up and activates AMD-V on the current CPU
*
* @returns VBox status code.
* @param pCpu CPU info struct
* @param pVM The VM to operate on. (can be NULL after a resume!!)
* @param pvPageCpu Pointer to the global cpu page
* @param pPageCpuPhys Physical address of the global cpu page
*/
VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
{
/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
if (val & MSR_K6_EFER_SVME)
{
/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
if ( pVM
{
pCpu->fIgnoreAMDVInUseError = true;
}
if (!pCpu->fIgnoreAMDVInUseError)
return VERR_SVM_IN_USE;
}
/* Turn on AMD-V in the EFER MSR. */
/* Write the physical page address where the CPU will store the host state while executing the VM. */
return VINF_SUCCESS;
}
/**
* Deactivates AMD-V on the current CPU
*
* @returns VBox status code.
* @param pCpu CPU info struct
* @param pvPageCpu Pointer to the global cpu page
* @param pPageCpuPhys Physical address of the global cpu page
*/
{
/* Turn off AMD-V in the EFER MSR. */
/* Invalidate host state physical address. */
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM AMD-V init.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
/* Set all bits to intercept all IO accesses. */
/* Erratum 170 which requires a forced TLB flush for each world switch:
*
* All BH-G1/2 and DH-G1/2 models include a fix:
* Athlon X2: 0x6b 1/2
* 0x68 1/2
* Athlon 64: 0x7f 1
* 0x6f 2
* Sempron: 0x7f 1/2
* 0x6f 2
* 0x6c 2
* 0x7c 2
* Turion 64: 0x68 2
*
*/
if ( u32Family == 0xf
{
Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
}
/* Allocate VMCBs for all guest CPUs. */
{
/* Allocate one page for the host context */
rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
/* Allocate one page for the VM control block (VMCB). */
rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
/* Set all bits to intercept all MSR accesses. */
}
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM AMD-V termination.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
{
{
}
{
}
{
}
}
{
}
return VINF_SUCCESS;
}
/**
* Sets up AMD-V for the specified VM
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc = VINF_SUCCESS;
{
/* Program the control fields. Most of them never have to be changed again. */
/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
else
/*
* CR0/3/4 writes must be intercepted for obvious reasons.
*/
else
/* Intercept all DRx reads and writes by default. Changed later on. */
/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
* All breakpoints are automatically cleared when the VM exits.
*/
#ifndef DEBUG
#endif
| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
;
/* With nested paging we don't care about invlpg anymore. */
| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
;
/* Ignore the priority in the TPR; just deliver it when we tell it to. */
/* Set IO and MSR bitmap addresses. */
/* No LBR virtualization. */
/** The ASID must start at 1; the host uses 0. */
/** Setup the PAT msr (nested paging only) */
* to modify them directly.
*/
}
return rc;
}
/**
* Sets the permission bits for the specified MSR
*
* @param pVCpu The VMCPU to operate on.
* @param ulMSR MSR value
* @param fRead Reading allowed/disallowed
* @param fWrite Writing allowed/disallowed
*/
{
unsigned ulBit;
if (ulMSR <= 0x00001FFF)
{
/* Pentium-compatible MSRs */
}
else
if ( ulMSR >= 0xC0000000
&& ulMSR <= 0xC0001FFF)
{
/* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
pMSRBitmap += 0x800;
}
else
if ( ulMSR >= 0xC0010000
&& ulMSR <= 0xC0011FFF)
{
/* AMD Seventh and Eighth Generation Processor MSRs */
pMSRBitmap += 0x1000;
}
else
{
AssertFailed();
return;
}
if (fRead)
else
if (fWrite)
else
}
/**
* Injects an event (trap or external interrupt)
*
* @param pVCpu The VMCPU to operate on.
* @param pVMCB SVM control block
* @param pCtx CPU Context
* @param pIntInfo SVM interrupt info
*/
{
#ifdef VBOX_WITH_STATISTICS
#endif
#ifdef VBOX_STRICT
Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
else
Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
else
{
}
#endif
/* Set event injection state. */
}
/**
* Checks for pending guest interrupts and injects them
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param pVMCB SVM control block
* @param pCtx CPU Context
*/
{
int rc;
/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
{
Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
return VINF_SUCCESS;
}
/* If an active trap is already pending, then we must forward it first! */
if (!TRPMHasTrap(pVCpu))
{
{
Event.n.u32ErrorCode = 0;
return VINF_SUCCESS;
}
/* @todo SMI interrupts. */
/* When external interrupts are pending, we should exit the VM when IF is set. */
{
{
{
LogFlow(("Enable irq window exit!\n"));
else
Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
}
}
else
{
if (RT_SUCCESS(rc))
{
}
else
{
/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
/* Just continue */
}
}
}
}
#ifdef VBOX_STRICT
if (TRPMHasTrap(pVCpu))
{
}
#endif
&& TRPMHasTrap(pVCpu)
)
{
/* If a new event is pending, then dispatch it now. */
/* Clear the pending trap. */
{
switch (u8Vector) {
case 8:
case 10:
case 11:
case 12:
case 13:
case 14:
case 17:
/* Valid error codes. */
break;
default:
break;
}
if (u8Vector == X86_XCPT_NMI)
else
}
else
} /* if (interrupts can be dispatched) */
return VINF_SUCCESS;
}
/**
* Save the host state
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
*/
{
/* Nothing to do here. */
return VINF_SUCCESS;
}
/**
* Loads the guest state
*
* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param pCtx Guest context
*/
{
return VERR_INVALID_PARAMETER;
/* Setup AMD SVM. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
{
}
/* Guest CPU context: LDTR. */
{
}
/* Guest CPU context: TR. */
{
}
/* Guest CPU context: GDTR. */
{
}
/* Guest CPU context: IDTR. */
{
}
/*
* Sysenter MSRs (unconditional)
*/
/* Control registers */
{
if (!CPUMIsGuestFPUStateActive(pVCpu))
{
}
else
{
/** @todo check if we support the old style mess correctly. */
if (!(val & X86_CR0_NE))
{
Log(("Forcing X86_CR0_NE!!!\n"));
/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
{
}
}
val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
}
/* Always enable caching. */
/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
{
val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
val |= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
}
}
/* CR2 as well */
{
/* Save our shadow CR3 register. */
{
#if HC_ARCH_BITS == 32
if (CPUMIsGuestInLongModeEx(pCtx))
else
#endif
}
else
{
Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
}
}
{
{
{
case PGMMODE_REAL:
case PGMMODE_PROTECTED: /* Protected mode, no paging. */
AssertFailed();
case PGMMODE_32_BIT: /* 32-bit paging. */
val &= ~X86_CR4_PAE;
break;
case PGMMODE_PAE: /* PAE paging. */
case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
/** @todo use normal 32 bits paging */
val |= X86_CR4_PAE;
break;
case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
#ifdef VBOX_ENABLE_64_BITS_GUESTS
break;
#else
AssertFailed();
#endif
default: /* shut up gcc */
AssertFailed();
}
}
}
/* Debug registers. */
{
#ifdef DEBUG
/* Sync the hypervisor debug state now if any breakpoint is armed. */
&& !DBGFIsStepping(pVCpu))
{
/* Save the host and load the hypervisor debug state. */
/* DRx intercepts remain enabled. */
/* Override dr6 & dr7 with the hypervisor values. */
}
else
#endif
/* Sync the debug state now if any breakpoint is armed. */
&& !DBGFIsStepping(pVCpu))
{
/* Disable drx move intercepts. */
/* Save the host and load the guest debug state. */
}
}
/* EIP, ESP and EFLAGS */
/* Set CPL */
/* vmrun will fail without MSR_K6_EFER_SVME. */
/* 64 bits guest mode? */
if (CPUMIsGuestInLongModeEx(pCtx))
{
#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
#else
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# endif
#endif
/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
}
else
{
/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
}
/* TSC offset. */
{
{
}
else
{
/* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
}
}
else
{
}
/* Sync the various msrs for 64 bits mode. */
#ifdef DEBUG
/* Intercept X86_XCPT_DB if stepping is enabled */
if ( DBGFIsStepping(pVCpu)
else
#endif
/* Done. */
return VINF_SUCCESS;
}
/**
* Runs guest code in an AMD-V VM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param pCtx Guest context
*/
{
int rc = VINF_SUCCESS;
bool fSyncTPR = false;
unsigned cResume = 0;
PHWACCM_CPUINFO pCpu = 0;
#ifdef VBOX_STRICT
#endif
#endif
/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
*/
/* Safety precaution; looping for too long here can have a very bad effect on the host */
{
goto end;
}
/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
{
Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
{
/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
*/
/* Irq inhibition is no longer active; clear the corresponding SVM state. */
}
}
else
{
/* Irq inhibition is no longer active; clear the corresponding SVM state. */
}
{
{
}
}
#endif
/* Check for pending actions that force us to go back to ring 3. */
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
{
/* Check if a sync operation is pending. */
{
rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (rc != VINF_SUCCESS)
{
goto end;
}
}
#ifdef DEBUG
/* Intercept X86_XCPT_DB if stepping is enabled */
if (!DBGFIsStepping(pVCpu))
#endif
{
{
rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
goto end;
}
}
/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
{
goto end;
}
/* Check if a pgm pool flush is in progress. */
{
goto end;
}
}
/*
* Exit to ring-3 preemption/work is pending.
*
* Interrupts are disabled before the call to make sure we don't miss any interrupt
* that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
* further down, but SVMR0CheckPendingInterrupt makes that impossible.)
*
* Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
* shootdowns rely on this.
*/
{
goto end;
}
#endif
/* When external interrupts are pending, we should exit the VM when IF is set. */
/* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
if (RT_FAILURE(rc))
{
goto end;
}
/* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
* @todo query and update the TPR only when it could have been changed (mmio access)
*/
{
bool fPending;
/* TPR caching in CR8 */
{
/* Our patch code uses LSTAR for TPR caching. */
if (fPending)
{
/* A TPR change could activate a pending interrupt, so catch lstar writes. */
}
else
/* No interrupts are pending, so we don't need to be explicitely notified.
* There are enough world switches for detecting pending interrupts.
*/
}
else
{
pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
if (fPending)
{
/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
}
else
/* No interrupts are pending, so we don't need to be explicitely notified.
* There are enough world switches for detecting pending interrupts.
*/
}
}
/* All done! Let's start VM execution. */
/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
#ifdef LOG_ENABLED
{
LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
else
LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
}
#endif
/*
* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
* (until the actual world switch)
*/
#ifdef VBOX_STRICT
idCpuCheck = RTMpCpuId();
#endif
/* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
{
goto end;
}
/* Disable interrupts to make sure a poke will interrupt execution.
* This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
*/
#endif
/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
{
/* Force a TLB flush on VM entry. */
}
else
/** Set TLB flush state as checked until we return from the world switch. */
/* Check for tlb shootdown flushes. */
/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
{
{
pCpu->cTLBFlushes++;
}
else
}
else
{
/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
{
/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
}
}
AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
#ifdef VBOX_WITH_STATISTICS
else
#endif
/* In case we execute a goto ResumeExecution later on. */
#ifdef VBOX_STRICT
#endif
#ifdef VBOX_WITH_KERNEL_USING_XMM
hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
#else
pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
#endif
/* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
uOldEFlags = ~(RTCCUINTREG)0;
#endif
/*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*/
/* Reason for the VM exit */
{
#ifdef DEBUG
#endif
goto end;
}
/* Let's first sync back eip, esp, and eflags. */
/* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
/* Can be updated behind our back in the nested paging case. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
/* Correct the hidden CS granularity flag. Haven't seen it being wrong in
any other register (yet). */
{
}
#define SVM_ASSERT_SEL_GRANULARITY(reg) \
/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
{
}
/* Note! NOW IT'S SAFE FOR LOGGING! */
/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
{
}
else
/* Sync back DR6 as it could have been changed by hitting breakpoints. */
/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
/* Check if an injected event was interrupted prematurely. */
&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
{
Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
#ifdef LOG_ENABLED
if ( exitCode == SVM_EXIT_EXCEPTION_E
{
Log(("Double fault!\n"));
}
#endif
/* Error code present? (redundant) */
else
}
#ifdef VBOX_WITH_STATISTICS
if (exitCode == SVM_EXIT_NPF)
else
#endif
/* Sync back the TPR if it was changed. */
if (fSyncTPR)
{
{
{
/* Our patch code uses LSTAR for TPR caching. */
}
}
else
{
{
rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
}
}
}
/* Deal with the reason of the VM-exit. */
switch (exitCode)
{
case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
{
/* Pending trap. */
switch (vector)
{
case X86_XCPT_DB:
{
/* Note that we don't support guest and host-initiated debugging at the same time. */
if (rc == VINF_EM_RAW_GUEST_TRAP)
{
/* Reinject the exception. */
goto ResumeExecution;
}
/* Return to ring 3 to deal with the debug exit code. */
break;
}
case X86_XCPT_NM:
{
/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
if (rc == VINF_SUCCESS)
{
/* Continue execution. */
goto ResumeExecution;
}
Log(("Forward #NM fault to the guest\n"));
goto ResumeExecution;
}
case X86_XCPT_PF: /* Page fault */
{
#ifdef DEBUG
{ /* A genuine pagefault.
* Forward the trap to the guest by injecting the exception and resuming execution.
*/
Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
/* Now we must update CR2. */
goto ResumeExecution;
}
#endif
/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
{
if ( rc == VINF_SUCCESS
&& GCPhys == GCPhysApicBase)
{
/* Only attempt to patch the instruction once. */
PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
if (!pPatch)
{
break;
}
}
}
#endif
/* Exit qualification contains the linear address of the page fault. */
/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
if (rc == VINF_SUCCESS)
{ /* We've successfully synced our shadow pages, so let's just continue execution. */
Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
goto ResumeExecution;
}
else
if (rc == VINF_EM_RAW_GUEST_TRAP)
{ /* A genuine pagefault.
* Forward the trap to the guest by injecting the exception and resuming execution.
*/
Log2(("Forward page fault to the guest\n"));
/* The error code might have been changed. */
/* Now we must update CR2. */
goto ResumeExecution;
}
#ifdef VBOX_STRICT
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case X86_XCPT_MF: /* Floating point exception. */
{
{
/* old style FPU error reporting needs some extra work. */
/** @todo don't fall back to the recompiler, but do it manually. */
break;
}
goto ResumeExecution;
}
#ifdef VBOX_STRICT
case X86_XCPT_BP: /* Breakpoint. */
case X86_XCPT_GP: /* General protection failure exception.*/
case X86_XCPT_UD: /* Unknown opcode exception. */
case X86_XCPT_DE: /* Divide error. */
case X86_XCPT_SS: /* Stack segment exception. */
case X86_XCPT_NP: /* Segment not present exception. */
{
switch(vector)
{
case X86_XCPT_GP:
break;
case X86_XCPT_BP:
break;
case X86_XCPT_DE:
break;
case X86_XCPT_UD:
break;
case X86_XCPT_SS:
break;
case X86_XCPT_NP:
break;
}
goto ResumeExecution;
}
#endif
default:
break;
} /* switch (vector) */
break;
}
case SVM_EXIT_NPF:
{
/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
{
{
/* Only attempt to patch the instruction once. */
PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
if (!pPatch)
{
break;
}
}
}
#endif
/* Exit qualification contains the linear address of the page fault. */
/* Handle the pagefault trap for the nested shadow table. */
#if HC_ARCH_BITS == 32
if (CPUMIsGuestInLongModeEx(pCtx))
else
#endif
rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
if (rc == VINF_SUCCESS)
{ /* We've successfully synced our shadow pages, so let's just continue execution. */
Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
goto ResumeExecution;
}
#ifdef VBOX_STRICT
if (rc != VINF_EM_RAW_EMULATE_INSTR)
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case SVM_EXIT_VINTR:
/* A virtual interrupt is about to be delivered, which means IF=1. */
goto ResumeExecution;
case SVM_EXIT_FERR_FREEZE:
case SVM_EXIT_INTR:
case SVM_EXIT_NMI:
case SVM_EXIT_SMI:
case SVM_EXIT_INIT:
/* External interrupt; leave to allow it to be dispatched again. */
break;
case SVM_EXIT_WBINVD:
case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
/* Skip instruction and continue directly. */
/* Continue execution.*/
goto ResumeExecution;
case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
{
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
{
Log2(("SVM: Rdtsc\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
{
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
{
Log2(("SVM: Rdtscp\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
{
Log2(("SVM: invlpg\n"));
/* Truly a pita. Why can't SVM give the same information as VT-x? */
if (rc == VINF_SUCCESS)
{
goto ResumeExecution; /* eip already updated */
}
break;
}
case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
{
switch (exitCode - SVM_EXIT_WRITE_CR0)
{
case 0:
break;
case 2:
break;
case 3:
break;
case 4:
break;
case 8:
break;
default:
AssertFailed();
}
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
{
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
{
if ( !DBGFIsStepping(pVCpu)
{
/* Disable drx move intercepts. */
/* Save the host and load the guest debug state. */
goto ResumeExecution;
}
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
{
if (!DBGFIsStepping(pVCpu))
{
/* Disable drx move intercepts. */
/* Save the host and load the guest debug state. */
goto ResumeExecution;
}
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
case SVM_EXIT_IOIO: /* I/O instruction. */
{
/** @todo could use a lookup table here */
if (IoExitInfo.n.u1OP8)
{
uIOSize = 1;
uAndVal = 0xff;
}
else
if (IoExitInfo.n.u1OP16)
{
uIOSize = 2;
uAndVal = 0xffff;
}
else
if (IoExitInfo.n.u1OP32)
{
uIOSize = 4;
uAndVal = 0xffffffff;
}
else
{
AssertFailed(); /* should be fatal. */
break;
}
if (IoExitInfo.n.u1STR)
{
/* Disassemble manually to deal with segment prefixes. */
if (rc == VINF_SUCCESS)
{
if (IoExitInfo.n.u1Type == 0)
{
rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
}
else
{
rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
}
}
else
}
else
{
if (IoExitInfo.n.u1Type == 0)
{
Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
if (rc == VINF_IOM_HC_IOPORT_WRITE)
HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
}
else
{
if (IOM_SUCCESS(rc))
{
/* Write back to the EAX register. */
Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
}
else
if (rc == VINF_IOM_HC_IOPORT_READ)
HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
}
}
/*
* Handled the I/O return codes.
* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
*/
if (IOM_SUCCESS(rc))
{
/* Update EIP and continue execution. */
{
/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
{
/* IO operation lookup arrays. */
for (unsigned i=0;i<4;i++)
{
{
/* Clear all breakpoint status flags and set the one we just hit. */
/* Note: AMD64 Architecture Programmer's Manual 13.1:
* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
* the contents have been read.
*/
/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
/* Paranoia. */
/* Inject the exception. */
goto ResumeExecution;
}
}
}
goto ResumeExecution;
}
Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
break;
}
#ifdef VBOX_STRICT
if (rc == VINF_IOM_HC_IOPORT_READ)
else if (rc == VINF_IOM_HC_IOPORT_WRITE)
else
AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
#endif
break;
}
case SVM_EXIT_HLT:
/** Check if external interrupts are pending; if so, don't switch back. */
goto ResumeExecution;
rc = VINF_EM_HALT;
break;
case SVM_EXIT_MWAIT_UNCOND:
Log2(("SVM: mwait\n"));
if ( rc == VINF_EM_HALT
|| rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
/** Check if external interrupts are pending; if so, don't switch back. */
if ( rc == VINF_SUCCESS
|| ( rc == VINF_EM_HALT
)
goto ResumeExecution;
}
break;
case SVM_EXIT_MONITOR:
{
Log2(("SVM: monitor\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_VMMCALL:
if (rc == VINF_SUCCESS)
{
goto ResumeExecution; /* rip already updated. */
}
/* no break */
case SVM_EXIT_RSM:
case SVM_EXIT_INVLPGA:
case SVM_EXIT_VMRUN:
case SVM_EXIT_VMLOAD:
case SVM_EXIT_VMSAVE:
case SVM_EXIT_STGI:
case SVM_EXIT_CLGI:
case SVM_EXIT_SKINIT:
{
/* Unsupported instructions. */
goto ResumeExecution;
}
/* Emulate in ring 3. */
case SVM_EXIT_MSR:
{
/* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
{
{
/* Our patch code uses LSTAR for TPR caching. */
}
/* Skip the instruction and continue. */
/* Only resume if successful. */
goto ResumeExecution;
}
/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
break;
}
case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
{
/* Caused by an injected interrupt. */
{
case SVM_EVENT_EXTERNAL_IRQ:
case SVM_EVENT_NMI:
break;
default:
/* Exceptions and software interrupts can just be restarted. */
break;
}
}
break;
case SVM_EXIT_PAUSE:
case SVM_EXIT_MWAIT_ARMED:
break;
case SVM_EXIT_SHUTDOWN:
break;
case SVM_EXIT_IDTR_READ:
case SVM_EXIT_GDTR_READ:
case SVM_EXIT_LDTR_READ:
case SVM_EXIT_TR_READ:
case SVM_EXIT_IDTR_WRITE:
case SVM_EXIT_GDTR_WRITE:
case SVM_EXIT_LDTR_WRITE:
case SVM_EXIT_TR_WRITE:
case SVM_EXIT_CR0_SEL_WRITE:
default:
/* Unexpected exit codes. */
break;
}
end:
/* Signal changes for the recompiler. */
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
if (exitCode == SVM_EXIT_INTR)
{
/* On the next entry we'll only sync the host context. */
}
else
{
/* On the next entry we'll sync everything. */
/** @todo we can do better than this */
/* Not in the VINF_PGM_CHANGE_MODE though! */
}
/* translate into a less severe return code */
if (rc == VERR_EM_INTERPRETER)
/* Just set the correct state here instead of trying to catch every goto above. */
/* Restore interrupts if we exitted after disabling them. */
if (uOldEFlags != ~(RTCCUINTREG)0)
#endif
return rc;
}
/**
* Emulate simple mov tpr instruction
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param pCtx CPU context
*/
{
int rc;
while (true)
{
bool fPending;
PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
if (!pPatch)
break;
{
case HWACCMTPRINSTR_READ:
/* TPR caching in CR8 */
LogFlow(("Emulated read successfully\n"));
break;
case HWACCMTPRINSTR_WRITE_REG:
case HWACCMTPRINSTR_WRITE_IMM:
/* Fetch the new TPR value */
{
}
else
LogFlow(("Emulated write successfully\n"));
break;
default:
}
}
return VINF_SUCCESS;
}
/**
* Enters the AMD-V session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param pCpu CPU info struct
*/
{
LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
return VINF_SUCCESS;
}
/**
* Leaves the AMD-V session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param pCtx CPU context
*/
{
#ifdef DEBUG
{
}
else
#endif
/* Save the guest debug state if necessary. */
{
/* Intercept all DRx reads and writes again. Changed later on. */
/* Resync the debug registers the next time. */
}
else
return VINF_SUCCESS;
}
static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case PARMTYPE_IMMEDIATE:
case PARMTYPE_ADDRESS:
return VERR_EM_INTERPRETER;
break;
default:
return VERR_EM_INTERPRETER;
}
/** @todo is addr always a flat linear address or ds based
* (in absence of segment override prefixes)????
*/
if (RT_SUCCESS(rc))
return VINF_SUCCESS;
return rc;
}
/**
* Interprets INVLPG
*
* @returns VBox status code.
* @retval VINF_* Scheduling instructions.
* @retval VERR_EM_INTERPRETER Something we can't cope with.
* @retval VERR_* Fatal errors.
*
* @param pVM The VM handle.
* @param pRegFrame The register frame.
* @param ASID Tagged TLB id for the guest
*
* Updates the EIP if an instruction was executed successfully.
*/
{
/*
* Only allow 32 & 64 bits code.
*/
DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
if (enmMode != CPUMODE_16BIT)
{
int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
if (RT_SUCCESS(rc))
{
{
if (RT_SUCCESS(rc))
return rc;
}
}
}
return VERR_EM_INTERPRETER;
}
/**
* Invalidates a guest page
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param GCVirt Page to invalidate
*/
{
/* Skip it if a TLB flush is already pending. */
if (!fFlushPending)
{
#if HC_ARCH_BITS == 32
/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
if (CPUMIsGuestInLongMode(pVCpu))
else
#endif
}
return VINF_SUCCESS;
}
#if 0 /* obsolete, but left here for clarification. */
/**
* Invalidates a guest page by physical address
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param GCPhys Page to invalidate
*/
{
/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
return VINF_SUCCESS;
}
#endif
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
/**
* Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
*
* @returns VBox status code.
* @param pVMCBHostPhys Physical address of host VMCB.
* @param pVMCBPhys Physical address of the VMCB.
* @param pCtx Guest context.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
*/
DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
{
}
/**
* Executes the specified handler in 64 mode
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx Guest context
* @param pfnHandler RC handler
* @param cbParam Number of parameters
* @param paParam Array of 32 bits parameters
*/
VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
{
int rc;
/* @todo This code is not guest SMP safe (hyper stack and switchers) */
/* Disable interrupts. */
for (int i=(int)cbParam-1;i>=0;i--)
/* Call switcher. */
return rc;
}
#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */