pci.h revision 677833bc953b6cb418c701facbdcf4aa18d6c44e
#ifndef PCI_H
#define PCI_H
/*
** Support for NE2000 PCI clones added David Monro June 1997
** Generalised for other PCI NICs by Ken Yap July 1997
**
** Most of this is taken from:
**
*/
/*
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
#include "pci_ids.h"
#define PCIBIOS_PCI_BIOS_PRESENT 0xb101
#define PCIBIOS_FIND_PCI_DEVICE 0xb102
#define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
#define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
#define PCIBIOS_READ_CONFIG_BYTE 0xb108
#define PCIBIOS_READ_CONFIG_WORD 0xb109
#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
#define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
#define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
#define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#ifndef PCI_BASE_ADDRESS_IO_MASK
#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
#endif
#ifndef PCI_BASE_ADDRESS_MEM_MASK
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
#endif
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
bits 31..11 are address,
10..2 are reserved */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK ~0x0f
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
#define PCI_MEMORY_RANGE_MASK ~0x0f
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0f
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK ~0x0f
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_CB_CAPABILITY_LIST 0x14
/* Capability lists */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_SIZEOF 4
/* Power Management Registers */
#define PCI_PM_SIZEOF 8
/* AGP registers */
#define PCI_AGP_SIZEOF 12
/* Slot Identification */
/* Message Signalled Interrupts registers */
/* PCI signature: "PCI " */
/* PCI service signature: "$PCI" */
union bios32 {
struct {
unsigned long signature; /* _32_ */
unsigned long entry; /* 32 bit physical address */
unsigned char revision; /* Revision level, 0 */
unsigned char length; /* Length in paragraphs should be 01 */
unsigned char checksum; /* All bytes must add up to zero */
} fields;
char chars[16];
};
struct pci_device;
struct dev;
struct pci_device {
const char *name;
/* membase and ioaddr are silly and depricated */
unsigned int membase;
unsigned int ioaddr;
unsigned int romaddr;
unsigned char irq;
unsigned char devfn;
unsigned char bus;
unsigned char use_specified;
const struct pci_driver *driver;
};
extern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t *value);
extern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t value);
extern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t *value);
extern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t value);
extern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t *value);
extern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t value);
extern unsigned long pcibios_bus_base(unsigned int bus);
extern void adjust_pci_device(struct pci_device *p);
static inline int
{
}
static inline int
{
}
static inline int
{
}
static inline int
{
}
static inline int
{
}
static inline int
{
}
/* Helper functions to find the size of a pci bar */
/* Helper function to find pci capabilities */
struct pci_id {
const char *name;
};
struct dev;
/* Most pci drivers will use this */
struct pci_driver {
int type;
const char *name;
int id_count;
/* On a few occasions the hardware is standardized enough that
* we only need to know the class of the device and not the exact
* type to drive the device correctly. If this is the case
* set a class value other than 0.
*/
unsigned short class;
};
/* Defined by the linker... */
extern const struct pci_driver pci_drivers[];
extern const struct pci_driver pci_drivers_end[];
#endif /* PCI_H */