HWACCMR0.cpp revision c98fb3e16fcd571a790eab772c0c66173d225205
/* $Id$ */
/** @file
* HWACCM - Host Context Ring 0.
*/
/*
* Copyright (C) 2006-2007 innotek GmbH
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License as published by the Free Software Foundation,
* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
* distribution. VirtualBox OSE is distributed in the hope that it will
* be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HWACCM
#include "HWACCMInternal.h"
#include <VBox/hwacc_vmx.h>
#include <VBox/hwacc_svm.h>
#include "HWVMXR0.h"
#include "HWSVMR0.h"
/**
* Does Ring-0 HWACCM initialization.
*
* This is mainly to check that the Host CPU mode is compatible
* with VMX.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
/*
* Check for VMX capabilities
*/
if (ASMHasCpuId())
{
/* Query AMD features. */
ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &pVM->hwaccm.s.cpuid.u32AMDFeatureECX, &pVM->hwaccm.s.cpuid.u32AMDFeatureEDX);
)
{
/*
*/
if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
)
{
/*
* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
* Once the lock bit is set, this MSR can no longer be modified.
*/
if (!(pVM->hwaccm.s.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK)))
{
/* MSR is not yet locked; we can change it ourselves here */
pVM->hwaccm.s.vmx.msr.feature_ctrl |= (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK);
}
if ( (pVM->hwaccm.s.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK))
{
/*
* Check CR4.VMXE
*/
{
/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
* try to execute the VMX instructions...
*/
}
}
else
}
else
}
else
if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
)
{
/*
*/
)
{
/* Check if SVM is disabled */
if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
{
/* Turn on SVM in the EFER MSR. */
if (!(val & MSR_K6_EFER_SVME))
{
}
/* Paranoia. */
if (val & MSR_K6_EFER_SVME)
{
/* Query AMD features. */
ASMCpuId(0x8000000A, &pVM->hwaccm.s.svm.u32Rev, &pVM->hwaccm.s.svm.u32MaxASID, &u32Dummy, &u32Dummy);
}
else
{
AssertFailed();
}
}
else
}
else
}
else
}
else
#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
return VINF_SUCCESS;
}
/**
* Sets up and activates VMX
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc = VINF_SUCCESS;
return VERR_INVALID_PARAMETER;
/* Setup Intel VMX. */
else
return rc;
}
/**
* Enable VMX or SVN
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
if (VBOX_FAILURE(rc))
return rc;
/* Always reload the host context and the guest's CR0 register. (!!!!) */
{
if (rc != VINF_SUCCESS)
return rc;
}
else
{
if (rc != VINF_SUCCESS)
return rc;
}
return VINF_SUCCESS;
}
/**
* Disable VMX or SVN
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
if (VBOX_FAILURE(rc))
return rc;
/** @note It's rather tricky with longjmps done by e.g. Log statements or the page fault handler. */
/* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
* or trash somebody else's FPU state.
*/
/* Restore host FPU and XMM state if necessary. */
if (CPUMIsGuestFPUStateActive(pVM))
{
Log2(("CPUMRestoreHostFPUState\n"));
/** @note CPUMRestoreHostFPUState keeps the current CR0 intact. */
}
{
return VMXR0Disable(pVM);
}
else
{
return SVMR0Disable(pVM);
}
}
/**
* Runs guest code in a hardware accelerated VM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
if (VBOX_FAILURE(rc))
return rc;
{
}
else
{
}
}
#ifdef VBOX_STRICT
/**
* Dumps a descriptor.
*
* @param Desc Descriptor to dump.
* @param Sel Selector number.
* @param pszMsg Message to prepend the log entry with.
*/
{
/*
* Make variable description string.
*/
static struct
{
unsigned cch;
const char *psz;
} const aTypes[32] =
{
/* system */
#if HC_ARCH_BITS == 64
#else
#endif
/* non system */
};
char szMsg[128];
else
#if HC_ARCH_BITS == 64
else
#else
else
#endif
*psz = '\0';
/*
* Limit and Base and format the output.
*/
#if HC_ARCH_BITS == 64
uint64_t u32Base = ((uintptr_t)Desc->Gen.u32BaseHigh3 << 32ULL) | Desc->Gen.u8BaseHigh2 << 24ULL | Desc->Gen.u8BaseHigh1 << 16ULL | Desc->Gen.u16BaseLow;
#else
uint32_t u32Base = Desc->Gen.u8BaseHigh2 << 24 | Desc->Gen.u8BaseHigh1 << 16 | Desc->Gen.u16BaseLow;
#endif
}
/**
* Formats a full register dump.
*
* @param pCtx The context to format.
*/
{
/*
* Format the flags.
*/
static struct
{
} aFlags[] =
{
};
char szEFlags[80];
{
if (pszAdd)
{
*psz++ = ' ';
}
}
/*
* Format the registers.
*/
Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
"cs={%04x base=%08x limit=%08x flags=%08x} dr0=%08x dr1=%08x\n"
"ds={%04x base=%08x limit=%08x flags=%08x} dr2=%08x dr3=%08x\n"
"es={%04x base=%08x limit=%08x flags=%08x} dr4=%08x dr5=%08x\n"
"fs={%04x base=%08x limit=%08x flags=%08x} dr6=%08x dr7=%08x\n"
,
(RTSEL)pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr0, pCtx->dr1,
(RTSEL)pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr2, pCtx->dr3,
(RTSEL)pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr4, pCtx->dr5,
(RTSEL)pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr6, pCtx->dr7));
Log(("gs={%04x base=%08x limit=%08x flags=%08x} cr0=%08x cr2=%08x\n"
"ss={%04x base=%08x limit=%08x flags=%08x} cr3=%08x cr4=%08x\n"
"gdtr=%08x:%04x idtr=%08x:%04x eflags=%08x\n"
"ldtr={%04x base=%08x limit=%08x flags=%08x}\n"
"tr ={%04x base=%08x limit=%08x flags=%08x}\n"
"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
"FCW=%04x FSW=%04x FTW=%04x\n",
(RTSEL)pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
(RTSEL)pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
}
#endif