etherfabric.c revision 677833bc953b6cb418c701facbdcf4aa18d6c44e
/**************************************************************************
*
* Etherboot driver for Level 5 Etherfabric network cards
*
* Written by Michael Brown <mbrown@fensystems.co.uk>
*
* Copyright Fen Systems Ltd. 2005
* Copyright Level 5 Networks Inc. 2005
*
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL), incorporated herein by
* reference. Drivers based on or derived from this code fall under
* the GPL and must retain the authorship, copyright and license
* notice.
*
**************************************************************************
*/
#include "etherboot.h"
#include "nic.h"
#include "pci.h"
#include "timer.h"
#define dma_addr_t unsigned long
#include "etherfabric.h"
/**************************************************************************
*
* Constants and macros
*
**************************************************************************
*/
#define DBG(...)
#define EFAB_ASSERT(x) \
do { \
if ( ! (x) ) { \
DBG ( "ASSERT(%s) failed at %s line %d [%s]\n", #x, \
} \
} while (0)
#define EFAB_TRACE(...)
#define EFAB_REGDUMP(...)
#define FALCON_USE_IO_BAR 1
/*
* EtherFabric constants
*
*/
/* PCI Definitions */
#define EFAB_VENDID_LEVEL5 0x1924
#define EF1002_DEVID 0xC101
/**************************************************************************
*
* Data structures
*
**************************************************************************
*/
/*
* Buffers used for TX, RX and event queue
*
*/
#define EFAB_BUF_ALIGN 4096
#define EFAB_DATA_BUF_SIZE 2048
#define EFAB_RX_BUFS 16
#define EFAB_RXD_SIZE 512
#define EFAB_TXD_SIZE 512
#define EFAB_EVQ_SIZE 512
struct efab_buffers {
};
static struct efab_buffers efab_buffers;
/** An RX buffer */
struct efab_rx_buf {
unsigned int len;
int id;
};
/** A TX buffer */
struct efab_tx_buf {
unsigned int len;
int id;
};
/** Etherfabric event type */
enum efab_event_type {
EFAB_EV_NONE = 0,
};
/** Etherfabric event */
struct efab_event {
/** Event type */
enum efab_event_type type;
/** RX buffer ID */
int rx_id;
/** RX length */
unsigned int rx_len;
};
/*
* Etherfabric abstraction layer
*
*/
struct efab_nic;
struct efab_operations {
struct efab_rx_buf *rx_buf );
struct efab_tx_buf *tx_buf );
struct efab_event *event );
unsigned int mac_reg );
unsigned int mac_reg );
int value );
};
/*
* Driver private data structure
*
*/
struct efab_nic {
/** PCI device */
struct pci_device *pci;
/** Operations table */
struct efab_operations *op;
/** Memory base */
void *membase;
/** I/O base */
unsigned int iobase;
/** Buffers */
struct efab_tx_buf tx_buf;
/** Buffer pointers */
unsigned int eventq_read_ptr; /* Falcon only */
unsigned int tx_write_ptr;
unsigned int rx_write_ptr;
int tx_in_progress;
/** Port 0/1 on the NIC */
int port;
/** MAC address */
/** GMII link options */
unsigned int link_options;
/** Link status */
int link_up;
/** INT_REG_KER for Falcon */
};
/**************************************************************************
*
* i2c EEPROM access
*
**************************************************************************
*/
struct efab_i2c_interface;
/** i2c bus direct control methods */
struct efab_i2c_bit_operations {
/** Set state of SDA line */
/** Set state of SCL line */
/** Get state of SDA line */
/** Get state of SCL line */
/** Delay between each bit operation */
unsigned int udelay;
/** Delay between each byte write */
unsigned int mdelay;
};
/** An i2c interface */
struct efab_i2c_interface {
/** Attached Etherfabric NIC */
/** I2C bus control methods */
struct efab_i2c_bit_operations *op;
/** Current output state of SDA line */
unsigned int sda : 1;
/** Current output state of SCL line */
unsigned int scl : 1;
};
/*
*
*/
}
}
int sda;
return sda;
}
int scl;
return scl;
}
/*
* i2c low-level protocol operations
*
*/
/* Just in case */
}
/* We may be restarting immediately after a {send,recv}_bit,
* so SCL will not necessarily already be high.
*/
}
}
int bit;
return bit;
}
}
/*
* i2c mid-level protocol operations
*
*/
int i;
/* Send byte */
for ( i = 0 ; i < 8 ; i++ ) {
byte <<= 1;
}
/* Check for acknowledgement from slave */
}
int i;
/* Receive byte */
for ( i = 0 ; i < 8 ; i++ ) {
}
return value;
}
}
return ( ( device_id << 1 ) | 0 );
}
unsigned int i;
int rc = 0;
/* Select device and starting offset */
goto out;
goto out;
/* Read data from device */
goto out;
for ( i = 0 ; i < ( len - 1 ); i++ ) {
/* Read and acknowledge all but the last byte */
}
/* Read last byte with no acknowledgement */
rc = 1;
out:
i2c_release ( i2c );
return rc;
}
/**************************************************************************
*
* GMII routines
*
**************************************************************************
*/
/* GMII registers */
/* Basic mode status register. */
/* Link partner ability register. */
/* Pseudo extensions to the link partner ability register */
#define LPA_1000FULL 0x00020000
#define LPA_1000HALF 0x00010000
/* Mask of bits not associated with speed or duplexity. */
/* PHY-specific status register */
/**
* Retrieve GMII autonegotiation advertised abilities
*
*/
unsigned int mii_advertise;
unsigned int gmii_advertise;
/* Extended bits are in bits 8 and 9 of GMII_GTCR */
& 0x03 );
}
/**
* Retrieve GMII autonegotiation link partner abilities
*
*/
unsigned int mii_lpa;
unsigned int gmii_lpa;
/* Extended bits are in bits 10 and 11 of GMII_GTSR */
}
/**
* Calculate GMII autonegotiated link technology
*
*/
static unsigned int gmii_nway_result ( unsigned int negotiated ) {
unsigned int other_bits;
/* Mask out the speed and duplexity bits */
if ( negotiated & LPA_1000FULL )
return ( other_bits | LPA_1000FULL );
else if ( negotiated & LPA_1000HALF )
return ( other_bits | LPA_1000HALF );
else if ( negotiated & LPA_100FULL )
return ( other_bits | LPA_100FULL );
else if ( negotiated & LPA_100BASE4 )
return ( other_bits | LPA_100BASE4 );
else if ( negotiated & LPA_100HALF )
return ( other_bits | LPA_100HALF );
else if ( negotiated & LPA_10FULL )
return ( other_bits | LPA_10FULL );
else return ( other_bits | LPA_10HALF );
}
/**
* Check GMII PHY link status
*
*/
int status;
int phy_status;
/* BMSR is latching - it returns "link down" if the link has
* been down at any point since the last read. To get a
* real-time status, we therefore read the register twice and
* use the result of the second read.
*/
/* Read the PHY-specific Status Register. This is
* non-latching, so we need do only a single read.
*/
}
/**************************************************************************
*
* Alaska PHY
*
**************************************************************************
*/
/**
* Initialise Alaska PHY
*
*/
unsigned int advertised, lpa;
/* Read link up status */
return;
/* Determine link options from PHY. */
printf ( "%dMbps %s-duplex (%04x,%04x)\n",
advertised, lpa );
}
/**************************************************************************
*
* Mentor MAC
*
**************************************************************************
*/
/* GMAC configuration register 1 */
#define GM_CFG1_REG_MAC 0x00
#define GM_SW_RST_LBN 31
#define GM_SW_RST_WIDTH 1
#define GM_RX_FC_EN_LBN 5
#define GM_RX_FC_EN_WIDTH 1
#define GM_TX_FC_EN_LBN 4
#define GM_TX_FC_EN_WIDTH 1
#define GM_RX_EN_LBN 2
#define GM_RX_EN_WIDTH 1
#define GM_TX_EN_LBN 0
#define GM_TX_EN_WIDTH 1
/* GMAC configuration register 2 */
#define GM_CFG2_REG_MAC 0x01
#define GM_PAMBL_LEN_LBN 12
#define GM_PAMBL_LEN_WIDTH 4
#define GM_IF_MODE_LBN 8
#define GM_IF_MODE_WIDTH 2
#define GM_PAD_CRC_EN_LBN 2
#define GM_PAD_CRC_EN_WIDTH 1
#define GM_FD_LBN 0
#define GM_FD_WIDTH 1
/* GMAC maximum frame length register */
#define GM_MAX_FLEN_REG_MAC 0x04
#define GM_MAX_FLEN_LBN 0
#define GM_MAX_FLEN_WIDTH 16
/* GMAC MII management configuration register */
#define GM_MII_MGMT_CFG_REG_MAC 0x08
#define GM_MGMT_CLK_SEL_LBN 0
#define GM_MGMT_CLK_SEL_WIDTH 3
/* GMAC MII management command register */
#define GM_MII_MGMT_CMD_REG_MAC 0x09
#define GM_MGMT_SCAN_CYC_LBN 1
#define GM_MGMT_SCAN_CYC_WIDTH 1
#define GM_MGMT_RD_CYC_LBN 0
#define GM_MGMT_RD_CYC_WIDTH 1
/* GMAC MII management address register */
#define GM_MII_MGMT_ADR_REG_MAC 0x0a
#define GM_MGMT_PHY_ADDR_LBN 8
#define GM_MGMT_PHY_ADDR_WIDTH 5
#define GM_MGMT_REG_ADDR_LBN 0
#define GM_MGMT_REG_ADDR_WIDTH 5
/* GMAC MII management control register */
#define GM_MII_MGMT_CTL_REG_MAC 0x0b
#define GM_MGMT_CTL_LBN 0
#define GM_MGMT_CTL_WIDTH 16
/* GMAC MII management status register */
#define GM_MII_MGMT_STAT_REG_MAC 0x0c
#define GM_MGMT_STAT_LBN 0
#define GM_MGMT_STAT_WIDTH 16
/* GMAC MII management indicators register */
#define GM_MII_MGMT_IND_REG_MAC 0x0d
#define GM_MGMT_BUSY_LBN 0
#define GM_MGMT_BUSY_WIDTH 1
/* GMAC station address register 1 */
#define GM_ADR1_REG_MAC 0x10
#define GM_HWADDR_5_LBN 24
#define GM_HWADDR_5_WIDTH 8
#define GM_HWADDR_4_LBN 16
#define GM_HWADDR_4_WIDTH 8
#define GM_HWADDR_3_LBN 8
#define GM_HWADDR_3_WIDTH 8
#define GM_HWADDR_2_LBN 0
#define GM_HWADDR_2_WIDTH 8
/* GMAC station address register 2 */
#define GM_ADR2_REG_MAC 0x11
#define GM_HWADDR_1_LBN 24
#define GM_HWADDR_1_WIDTH 8
#define GM_HWADDR_0_LBN 16
#define GM_HWADDR_0_WIDTH 8
/* GMAC FIFO configuration register 0 */
#define GMF_CFG0_REG_MAC 0x12
#define GMF_FTFENREQ_LBN 12
#define GMF_FTFENREQ_WIDTH 1
#define GMF_STFENREQ_LBN 11
#define GMF_STFENREQ_WIDTH 1
#define GMF_FRFENREQ_LBN 10
#define GMF_FRFENREQ_WIDTH 1
#define GMF_SRFENREQ_LBN 9
#define GMF_SRFENREQ_WIDTH 1
#define GMF_WTMENREQ_LBN 8
#define GMF_WTMENREQ_WIDTH 1
/* GMAC FIFO configuration register 1 */
#define GMF_CFG1_REG_MAC 0x13
#define GMF_CFGFRTH_LBN 16
#define GMF_CFGFRTH_WIDTH 5
#define GMF_CFGXOFFRTX_LBN 0
#define GMF_CFGXOFFRTX_WIDTH 16
/* GMAC FIFO configuration register 2 */
#define GMF_CFG2_REG_MAC 0x14
#define GMF_CFGHWM_LBN 16
#define GMF_CFGHWM_WIDTH 6
#define GMF_CFGLWM_LBN 0
#define GMF_CFGLWM_WIDTH 6
/* GMAC FIFO configuration register 3 */
#define GMF_CFG3_REG_MAC 0x15
#define GMF_CFGHWMFT_LBN 16
#define GMF_CFGHWMFT_WIDTH 6
#define GMF_CFGFTTH_LBN 0
#define GMF_CFGFTTH_WIDTH 6
/* GMAC FIFO configuration register 4 */
#define GMF_CFG4_REG_MAC 0x16
#define GMF_HSTFLTRFRM_PAUSE_LBN 12
#define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
/* GMAC FIFO configuration register 5 */
#define GMF_CFG5_REG_MAC 0x17
#define GMF_CFGHDPLX_LBN 22
#define GMF_CFGHDPLX_WIDTH 1
#define GMF_CFGBYTMODE_LBN 19
#define GMF_CFGBYTMODE_WIDTH 1
#define GMF_HSTDRPLT64_LBN 18
#define GMF_HSTDRPLT64_WIDTH 1
#define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
#define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
struct efab_mentormac_parameters {
int gmf_cfgfrth;
int gmf_cfgftth;
int gmf_cfghwmft;
int gmf_cfghwm;
int gmf_cfglwm;
};
/**
* Reset Mentor MAC
*
*/
int save_port;
/* Take into reset */
udelay ( 1000 );
/* Take out of reset */
udelay ( 1000 );
/* Mentor MAC connects both PHYs to MAC 0 */
/* Configure GMII interface so PHY is accessible. Note that
* GMII interface is connected only to port 0, and that on
* Falcon this is a no-op.
*/
udelay ( 10 );
}
/**
* Initialise Mentor MAC
*
*/
struct efab_mentormac_parameters *params ) {
/* Configuration register 1 */
/* Half-duplex operation requires TX flow control */
pause = 1;
}
GM_TX_EN, 1,
GM_RX_EN, 1,
GM_RX_FC_EN, 1 );
udelay ( 10 );
/* Configuration register 2 */
GM_PAD_CRC_EN, 1,
udelay ( 10 );
/* Max frame len register */
udelay ( 10 );
/* FIFO configuration register 0 */
GMF_FTFENREQ, 1,
GMF_STFENREQ, 1,
GMF_FRFENREQ, 1,
GMF_SRFENREQ, 1,
GMF_WTMENREQ, 1 );
udelay ( 10 );
/* FIFO configuration register 1 */
GMF_CFGXOFFRTX, 0xffff );
udelay ( 10 );
/* FIFO configuration register 2 */
udelay ( 10 );
/* FIFO configuration register 3 */
udelay ( 10 );
/* FIFO configuration register 4 */
udelay ( 10 );
/* FIFO configuration register 5 */
udelay ( 10 );
/* MAC address */
udelay ( 10 );
udelay ( 10 );
}
/**
* Wait for GMII access to complete
*
*/
int count;
udelay ( 10 );
return 1;
}
printf ( "Timed out waiting for GMII\n" );
return 0;
}
/**
* Write a GMII register
*
*/
int save_port;
/* Mentor MAC connects both PHYs to MAC 0 */
/* Check MII not currently being accessed */
if ( ! mentormac_gmii_wait ( efab ) )
goto out;
/* Write the address register */
udelay ( 10 );
/* Write data */
/* Wait for data to be written */
mentormac_gmii_wait ( efab );
out:
/* Restore efab->port */
}
/**
* Read a GMII register
*
*/
int location ) {
int value = 0xffff;
int save_port;
/* Mentor MAC connects both PHYs to MAC 0 */
/* Check MII not currently being accessed */
if ( ! mentormac_gmii_wait ( efab ) )
goto out;
/* Write the address register */
udelay ( 10 );
/* Request data to be read */
/* Wait for data to be become available */
if ( mentormac_gmii_wait ( efab ) ) {
/* Read data */
EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
}
/* Signal completion */
EFAB_ZERO_DWORD ( reg );
udelay ( 10 );
out:
/* Restore efab->port */
return value;
}
/**************************************************************************
*
* EF1002 routines
*
**************************************************************************
*/
/** Control and General Status */
#define EF1_CTR_GEN_STATUS0_REG 0x0
#define EF1_MASTER_EVENTS_LBN 12
#define EF1_MASTER_EVENTS_WIDTH 1
#define EF1_TX_ENGINE_EN_LBN 19
#define EF1_TX_ENGINE_EN_WIDTH 1
#define EF1_RX_ENGINE_EN_LBN 18
#define EF1_RX_ENGINE_EN_WIDTH 1
#define EF1_TURBO2_LBN 17
#define EF1_TURBO2_WIDTH 1
#define EF1_TURBO1_LBN 16
#define EF1_TURBO1_WIDTH 1
#define EF1_TURBO3_LBN 14
#define EF1_TURBO3_WIDTH 1
#define EF1_LB_RESET_LBN 3
#define EF1_LB_RESET_WIDTH 1
#define EF1_MAC_RESET_LBN 2
#define EF1_MAC_RESET_WIDTH 1
#define EF1_CAM_ENABLE_LBN 1
#define EF1_CAM_ENABLE_WIDTH 1
/** IRQ sources */
#define EF1_IRQ_SRC_REG 0x0008
/** IRQ mask */
#define EF1_IRQ_MASK_REG 0x000c
#define EF1_IRQ_PHY1_LBN 11
#define EF1_IRQ_PHY1_WIDTH 1
#define EF1_IRQ_PHY0_LBN 10
#define EF1_IRQ_PHY0_WIDTH 1
#define EF1_IRQ_SERR_LBN 7
#define EF1_IRQ_SERR_WIDTH 1
#define EF1_IRQ_EVQ_LBN 3
#define EF1_IRQ_EVQ_WIDTH 1
/** Event generation */
#define EF1_EVT3_REG 0x38
/** EEPROM access */
#define EF1_EEPROM_REG 0x40
#define EF1_EEPROM_SDA_LBN 31
#define EF1_EEPROM_SDA_WIDTH 1
#define EF1_EEPROM_SCL_LBN 30
#define EF1_EEPROM_SCL_WIDTH 1
#define EF1_JTAG_DISCONNECT_LBN 17
#define EF1_JTAG_DISCONNECT_WIDTH 1
/** Control register 2 */
#define EF1_CTL2_REG 0x4c
#define EF1_PLL_TRAP_LBN 31
#define EF1_PLL_TRAP_WIDTH 1
#define EF1_MEM_MAP_4MB_LBN 11
#define EF1_MEM_MAP_4MB_WIDTH 1
#define EF1_EV_INTR_CLR_WRITE_LBN 6
#define EF1_EV_INTR_CLR_WRITE_WIDTH 1
#define EF1_BURST_MERGE_LBN 5
#define EF1_BURST_MERGE_WIDTH 1
#define EF1_CLEAR_NULL_PAD_LBN 4
#define EF1_CLEAR_NULL_PAD_WIDTH 1
#define EF1_SW_RESET_LBN 2
#define EF1_SW_RESET_WIDTH 1
#define EF1_INTR_AFTER_EVENT_LBN 1
#define EF1_INTR_AFTER_EVENT_WIDTH 1
/** Event FIFO */
#define EF1_EVENT_FIFO_REG 0x50
/** Event FIFO count */
#define EF1_EVENT_FIFO_COUNT_REG 0x5c
#define EF1_EV_COUNT_LBN 0
#define EF1_EV_COUNT_WIDTH 16
/** TX DMA control and status */
#define EF1_DMA_TX_CSR_REG 0x80
#define EF1_DMA_TX_CSR_CHAIN_EN_LBN 8
#define EF1_DMA_TX_CSR_CHAIN_EN_WIDTH 1
#define EF1_DMA_TX_CSR_ENABLE_LBN 4
#define EF1_DMA_TX_CSR_ENABLE_WIDTH 1
#define EF1_DMA_TX_CSR_INT_EN_LBN 0
#define EF1_DMA_TX_CSR_INT_EN_WIDTH 1
/** RX DMA control and status */
#define EF1_DMA_RX_CSR_REG 0xa0
#define EF1_DMA_RX_ABOVE_1GB_EN_LBN 6
#define EF1_DMA_RX_ABOVE_1GB_EN_WIDTH 1
#define EF1_DMA_RX_BELOW_1MB_EN_LBN 5
#define EF1_DMA_RX_BELOW_1MB_EN_WIDTH 1
#define EF1_DMA_RX_CSR_ENABLE_LBN 0
#define EF1_DMA_RX_CSR_ENABLE_WIDTH 1
/** Level 5 watermark register (in MAC space) */
#define EF1_GMF_L5WM_REG_MAC 0x20
#define EF1_L5WM_LBN 0
#define EF1_L5WM_WIDTH 32
/** MAC clock */
#define EF1_GM_MAC_CLK_REG 0x112000
#define EF1_GM_PORT0_MAC_CLK_LBN 0
#define EF1_GM_PORT0_MAC_CLK_WIDTH 1
#define EF1_GM_PORT1_MAC_CLK_LBN 1
#define EF1_GM_PORT1_MAC_CLK_WIDTH 1
/** TX descriptor FIFO */
#define EF1_TX_DESC_FIFO 0x141000
#define EF1_TX_KER_EVQ_LBN 80
#define EF1_TX_KER_EVQ_WIDTH 12
#define EF1_TX_KER_IDX_LBN 64
#define EF1_TX_KER_IDX_WIDTH 16
#define EF1_TX_KER_MODE_LBN 63
#define EF1_TX_KER_MODE_WIDTH 1
#define EF1_TX_KER_PORT_LBN 60
#define EF1_TX_KER_PORT_WIDTH 1
#define EF1_TX_KER_CONT_LBN 56
#define EF1_TX_KER_CONT_WIDTH 1
#define EF1_TX_KER_BYTE_CNT_LBN 32
#define EF1_TX_KER_BYTE_CNT_WIDTH 24
#define EF1_TX_KER_BUF_ADR_LBN 0
#define EF1_TX_KER_BUF_ADR_WIDTH 32
/** TX descriptor FIFO flush */
#define EF1_TX_DESC_FIFO_FLUSH 0x141ffc
/** RX descriptor FIFO */
#define EF1_RX_DESC_FIFO 0x145000
#define EF1_RX_KER_EVQ_LBN 48
#define EF1_RX_KER_EVQ_WIDTH 12
#define EF1_RX_KER_IDX_LBN 32
#define EF1_RX_KER_IDX_WIDTH 16
#define EF1_RX_KER_BUF_ADR_LBN 0
#define EF1_RX_KER_BUF_ADR_WIDTH 32
/** RX descriptor FIFO flush */
#define EF1_RX_DESC_FIFO_FLUSH 0x145ffc
/** CAM */
#define EF1_CAM_BASE 0x1c0000
#define EF1_CAM_WTF_DOES_THIS_DO_LBN 0
#define EF1_CAM_WTF_DOES_THIS_DO_WIDTH 32
/** Event queue pointers */
#define EF1_EVQ_PTR_BASE 0x260000
#define EF1_EVQ_SIZE_LBN 29
#define EF1_EVQ_SIZE_WIDTH 2
#define EF1_EVQ_SIZE_4K 3
#define EF1_EVQ_SIZE_2K 2
#define EF1_EVQ_SIZE_1K 1
#define EF1_EVQ_SIZE_512 0
#define EF1_EVQ_BUF_BASE_ID_LBN 0
#define EF1_EVQ_BUF_BASE_ID_WIDTH 29
/* MAC registers */
#define EF1002_MAC_REGBANK 0x110000
#define EF1002_MAC_REGBANK_SIZE 0x1000
#define EF1002_MAC_REG_SIZE 0x08
/** Offset of a MAC register within EF1002 */
( EF1002_MAC_REGBANK + \
( (mac_reg) * EF1002_MAC_REG_SIZE ) )
/* Event queue entries */
#define EF1_EV_CODE_LBN 20
#define EF1_EV_CODE_WIDTH 8
#define EF1_RX_EV_DECODE 0x01
#define EF1_TX_EV_DECODE 0x02
#define EF1_TIMER_EV_DECODE 0x0b
#define EF1_DRV_GEN_EV_DECODE 0x0f
/* Receive events */
#define EF1_RX_EV_LEN_LBN 48
#define EF1_RX_EV_LEN_WIDTH 16
#define EF1_RX_EV_PORT_LBN 17
#define EF1_RX_EV_PORT_WIDTH 3
#define EF1_RX_EV_OK_LBN 16
#define EF1_RX_EV_OK_WIDTH 1
#define EF1_RX_EV_IDX_LBN 0
#define EF1_RX_EV_IDX_WIDTH 16
/* Transmit events */
#define EF1_TX_EV_PORT_LBN 17
#define EF1_TX_EV_PORT_WIDTH 3
#define EF1_TX_EV_OK_LBN 16
#define EF1_TX_EV_OK_WIDTH 1
#define EF1_TX_EV_IDX_LBN 0
#define EF1_TX_EV_IDX_WIDTH 16
/**
* Write dword to EF1002 register
*
*/
unsigned int reg ) {
}
/**
* Read dword from an EF1002 register
*
*/
unsigned int reg ) {
}
/**
* Read dword from an EF1002 register, silently
*
*/
unsigned int reg ) {
}
/**
* Get memory base
*
*/
unsigned long membase_phys;
}
static const unsigned int efab_pci_reg_addr[] = {
};
/** Number of registers in efab_pci_reg_addr */
#define EFAB_NUM_PCI_REG \
( sizeof ( efab_pci_reg_addr ) / sizeof ( efab_pci_reg_addr[0] ) )
/** PCI configuration space backup */
struct efab_pci_reg {
};
/**
* Reset device
*
*/
struct efab_pci_reg pci_reg;
unsigned int i;
/* Back up PCI configuration registers */
for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
}
/* Reset the whole device. */
mdelay ( 200 );
/* Restore PCI configuration space */
for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
}
/* Verify PCI configuration space */
for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
printf ( "PCI restore failed on register %02x "
"(is %08x, should be %08x); reboot\n",
return 0;
}
}
/* Verify device reset complete */
if ( EFAB_DWORD_IS_ALL_ONES ( reg ) ) {
printf ( "Reset failed\n" );
return 0;
}
return 1;
}
/**
* Initialise NIC
*
*/
/* No idea what CAM is, but the 'datasheet' says that we have
* to write these values in at start of day
*/
udelay ( 1000 );
udelay ( 1000 );
/* General control register 0 */
udelay ( 1000 );
/* General control register 2 */
udelay ( 1000 );
/* Enable RX DMA */
udelay ( 1000 );
/* Enable TX DMA */
udelay ( 1000 );
/* Disconnect the JTAG chain. Read-modify-write is impossible
* on the I2C control bits, since reading gives the state of
* the line inputs rather than the last written state.
*/
udelay ( 10 );
/* Flush descriptor queues */
EFAB_ZERO_DWORD ( reg );
wmb();
udelay ( 10000 );
/* Reset MAC */
mentormac_reset ( efab );
return 1;
}
/** I2C ID of the EEPROM */
#define EF1002_EEPROM_I2C_ID 0x50
/** Offset of MAC address within EEPROM */
#define EF1002_EEPROM_HWADDR_OFFSET 0x0
/** Set status of i2c outputs */
}
/** Get status of i2c SDA line */
}
/** Get status of i2c SCL line */
}
/** i2c bit-bashing data structure template */
static struct efab_i2c_bit_operations ef1002_i2c_bit_operations = {
.getsda = ef1002_getsda,
.getscl = ef1002_getscl,
.udelay = 20,
.mdelay = 10,
};
/**
* Read MAC address from EEPROM
*
*/
struct efab_i2c_interface i2c = {
.sda = 1,
.scl = 1,
};
return 0;
return 1;
}
/** RX descriptor */
typedef efab_qword_t ef1002_rx_desc_t;
/**
* Build RX descriptor
*
*/
struct efab_rx_buf *rx_buf ) {
EF1_RX_KER_EVQ, 0,
wmb();
udelay ( 10 );
}
/**
* Update RX descriptor write pointer
*
*/
/* Nothing to do */
}
/** TX descriptor */
typedef efab_oword_t ef1002_tx_desc_t;
/**
* Build TX descriptor
*
*/
struct efab_tx_buf *tx_buf ) {
EF1_TX_KER_EVQ, 0,
EF1_TX_KER_MODE, 0 /* IP mode */,
EF1_TX_KER_CONT, 0,
wmb();
udelay ( 10 );
}
/**
* Update TX descriptor write pointer
*
*/
/* Nothing to do */
}
/** An event */
typedef efab_qword_t ef1002_event_t;
/**
* Retrieve event from event queue
*
*/
struct efab_event *event ) {
int ev_code;
int words;
/* Check event FIFO depth */
if ( ! words )
return 0;
/* Read event data */
/* Decode event */
switch ( ev_code ) {
case EF1_TX_EV_DECODE:
break;
case EF1_RX_EV_DECODE:
/* RX len not available via event FIFO */
break;
case EF1_TIMER_EV_DECODE:
/* These are safe to ignore. We seem to get some at
* start of day, presumably due to the timers starting
* up with random contents.
*/
break;
default:
}
/* Clear any pending interrupts */
return 1;
}
/**
*
*/
EF1_IRQ_EVQ, enabled );
}
/**
* Generate interrupt
*
*/
}
/**
* Write dword to an EF1002 MAC register
*
*/
}
/**
* Read dword from an EF1002 MAC register
*
*/
}
/**
* Initialise MAC
*
*/
static struct efab_mentormac_parameters ef1002_mentormac_params = {
.gmf_cfgfrth = 0x13,
.gmf_cfgftth = 0x10,
.gmf_cfghwmft = 0x555,
.gmf_cfghwm = 0x2a,
.gmf_cfglwm = 0x15,
};
unsigned int mac_clk;
/* Initialise PHY */
alaska_init ( efab );
/* Initialise MAC */
/* Write Level 5 watermark register */
udelay ( 10 );
/* Set MAC clock speed */
} else {
}
udelay ( 10 );
return 1;
}
/** MDIO write */
int value ) {
}
/** MDIO read */
}
static struct efab_operations ef1002_operations = {
.reset = ef1002_reset,
};
/**************************************************************************
*
* Falcon routines
*
**************************************************************************
*/
/* I/O BAR address register */
#define FCN_IOM_IND_ADR_REG 0x0
/* I/O BAR data register */
#define FCN_IOM_IND_DAT_REG 0x4
/* Interrupt enable register */
#define FCN_INT_EN_REG_KER 0x0010
#define FCN_MEM_PERR_INT_EN_KER_LBN 5
#define FCN_MEM_PERR_INT_EN_KER_WIDTH 1
#define FCN_KER_INT_CHAR_LBN 4
#define FCN_KER_INT_CHAR_WIDTH 1
#define FCN_KER_INT_KER_LBN 3
#define FCN_KER_INT_KER_WIDTH 1
#define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2
#define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1
#define FCN_SRM_PERR_INT_EN_KER_LBN 1
#define FCN_SRM_PERR_INT_EN_KER_WIDTH 1
#define FCN_DRV_INT_EN_KER_LBN 0
#define FCN_DRV_INT_EN_KER_WIDTH 1
/* Interrupt status register */
#define FCN_INT_ADR_REG_KER 0x0030
#define FCN_INT_ADR_KER_LBN 0
/* Interrupt acknowledge register */
#define FCN_INT_ACK_KER_REG 0x0050
/* SPI host command register */
#define FCN_EE_SPI_HCMD_REG_KER 0x0100
#define FCN_EE_SPI_HCMD_CMD_EN_LBN 31
#define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1
#define FCN_EE_WR_TIMER_ACTIVE_LBN 28
#define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1
#define FCN_EE_SPI_HCMD_SF_SEL_LBN 24
#define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1
#define FCN_EE_SPI_EEPROM 0
#define FCN_EE_SPI_FLASH 1
#define FCN_EE_SPI_HCMD_DABCNT_LBN 16
#define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5
#define FCN_EE_SPI_HCMD_READ_LBN 15
#define FCN_EE_SPI_HCMD_READ_WIDTH 1
#define FCN_EE_SPI_READ 1
#define FCN_EE_SPI_WRITE 0
#define FCN_EE_SPI_HCMD_DUBCNT_LBN 12
#define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2
#define FCN_EE_SPI_HCMD_ADBCNT_LBN 8
#define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2
#define FCN_EE_SPI_HCMD_ENC_LBN 0
#define FCN_EE_SPI_HCMD_ENC_WIDTH 8
/* SPI host address register */
#define FCN_EE_SPI_HADR_REG_KER 0x0110
#define FCN_EE_SPI_HADR_DUBYTE_LBN 24
#define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8
#define FCN_EE_SPI_HADR_ADR_LBN 0
#define FCN_EE_SPI_HADR_ADR_WIDTH 24
/* SPI host data register */
#define FCN_EE_SPI_HDATA_REG_KER 0x0120
#define FCN_EE_SPI_HDATA3_LBN 96
#define FCN_EE_SPI_HDATA3_WIDTH 32
#define FCN_EE_SPI_HDATA2_LBN 64
#define FCN_EE_SPI_HDATA2_WIDTH 32
#define FCN_EE_SPI_HDATA1_LBN 32
#define FCN_EE_SPI_HDATA1_WIDTH 32
#define FCN_EE_SPI_HDATA0_LBN 0
#define FCN_EE_SPI_HDATA0_WIDTH 32
/* GPIO control register */
#define FCN_GPIO_CTL_REG_KER 0x0210
#define FCN_FLASH_PRESENT_LBN 7
#define FCN_FLASH_PRESENT_WIDTH 1
#define FCN_EEPROM_PRESENT_LBN 6
#define FCN_EEPROM_PRESENT_WIDTH 1
/* Global control register */
#define FCN_GLB_CTL_REG_KER 0x0220
#define FCN_EXT_PHY_RST_CTL_LBN 63
#define FCN_EXT_PHY_RST_CTL_WIDTH 1
#define FCN_PCIE_SD_RST_CTL_LBN 61
#define FCN_PCIE_SD_RST_CTL_WIDTH 1
#define FCN_PCIX_RST_CTL_LBN 60
#define FCN_PCIX_RST_CTL_WIDTH 1
#define FCN_RST_EXT_PHY_LBN 31
#define FCN_RST_EXT_PHY_WIDTH 1
#define FCN_INT_RST_DUR_LBN 4
#define FCN_INT_RST_DUR_WIDTH 3
#define FCN_EXT_PHY_RST_DUR_LBN 1
#define FCN_EXT_PHY_RST_DUR_WIDTH 3
#define FCN_SWRST_LBN 0
#define FCN_SWRST_WIDTH 1
#define FCN_INCLUDE_IN_RESET 0
#define FCN_EXCLUDE_FROM_RESET 1
/* Timer table for kernel access */
#define FCN_TIMER_CMD_REG_KER 0x420
#define FCN_TIMER_MODE_LBN 12
#define FCN_TIMER_MODE_WIDTH 2
#define FCN_TIMER_MODE_DIS 0
#define FCN_TIMER_MODE_INT_HLDOFF 1
#define FCN_TIMER_VAL_LBN 0
#define FCN_TIMER_VAL_WIDTH 12
/* SRAM receive descriptor cache configuration register */
#define FCN_SRM_RX_DC_CFG_REG_KER 0x610
#define FCN_SRM_RX_DC_BASE_ADR_LBN 0
#define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21
/* SRAM transmit descriptor cache configuration register */
#define FCN_SRM_TX_DC_CFG_REG_KER 0x620
#define FCN_SRM_TX_DC_BASE_ADR_LBN 0
#define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21
/* Receive filter control register */
#define FCN_RX_FILTER_CTL_REG_KER 0x810
#define FCN_NUM_KER_LBN 24
#define FCN_NUM_KER_WIDTH 2
/* Receive descriptor update register */
#define FCN_RX_DESC_UPD_REG_KER 0x0830
#define FCN_RX_DESC_WPTR_LBN 96
#define FCN_RX_DESC_WPTR_WIDTH 12
#define FCN_RX_DESC_WPTR_DWORD_LBN 0
#define FCN_RX_DESC_WPTR_DWORD_WIDTH 12
/* Receive descriptor cache configuration register */
#define FCN_RX_DC_CFG_REG_KER 0x840
#define FCN_RX_DC_SIZE_LBN 0
#define FCN_RX_DC_SIZE_WIDTH 2
/* Transmit descriptor update register */
#define FCN_TX_DESC_UPD_REG_KER 0x0a10
#define FCN_TX_DESC_WPTR_LBN 96
#define FCN_TX_DESC_WPTR_WIDTH 12
#define FCN_TX_DESC_WPTR_DWORD_LBN 0
#define FCN_TX_DESC_WPTR_DWORD_WIDTH 12
/* Transmit descriptor cache configuration register */
#define FCN_TX_DC_CFG_REG_KER 0xa20
#define FCN_TX_DC_SIZE_LBN 0
#define FCN_TX_DC_SIZE_WIDTH 2
/* PHY management transmit data register */
#define FCN_MD_TXD_REG_KER 0xc00
#define FCN_MD_TXD_LBN 0
#define FCN_MD_TXD_WIDTH 16
/* PHY management receive data register */
#define FCN_MD_RXD_REG_KER 0xc10
#define FCN_MD_RXD_LBN 0
#define FCN_MD_RXD_WIDTH 16
/* PHY management configuration & status register */
#define FCN_MD_CS_REG_KER 0xc20
#define FCN_MD_GC_LBN 4
#define FCN_MD_GC_WIDTH 1
#define FCN_MD_RIC_LBN 2
#define FCN_MD_RIC_WIDTH 1
#define FCN_MD_WRC_LBN 0
#define FCN_MD_WRC_WIDTH 1
/* PHY management PHY address register */
#define FCN_MD_PHY_ADR_REG_KER 0xc30
#define FCN_MD_PHY_ADR_LBN 0
#define FCN_MD_PHY_ADR_WIDTH 16
/* PHY management ID register */
#define FCN_MD_ID_REG_KER 0xc40
#define FCN_MD_PRT_ADR_LBN 11
#define FCN_MD_PRT_ADR_WIDTH 5
#define FCN_MD_DEV_ADR_LBN 6
#define FCN_MD_DEV_ADR_WIDTH 5
/* PHY management status & mask register */
#define FCN_MD_STAT_REG_KER 0xc50
#define FCN_MD_BSY_LBN 0
#define FCN_MD_BSY_WIDTH 1
/* Port 0 and 1 MAC control registers */
#define FCN_MAC0_CTRL_REG_KER 0xc80
#define FCN_MAC1_CTRL_REG_KER 0xc90
#define FCN_MAC_XOFF_VAL_LBN 16
#define FCN_MAC_XOFF_VAL_WIDTH 16
#define FCN_MAC_BCAD_ACPT_LBN 4
#define FCN_MAC_BCAD_ACPT_WIDTH 1
#define FCN_MAC_UC_PROM_LBN 3
#define FCN_MAC_UC_PROM_WIDTH 1
#define FCN_MAC_LINK_STATUS_LBN 2
#define FCN_MAC_LINK_STATUS_WIDTH 1
#define FCN_MAC_SPEED_LBN 0
#define FCN_MAC_SPEED_WIDTH 2
/* XGMAC global configuration - port 0*/
#define FCN_XM_GLB_CFG_REG_P0_KER 0x1220
#define FCN_XM_RX_STAT_EN_LBN 11
#define FCN_XM_RX_STAT_EN_WIDTH 1
#define FCN_XM_TX_STAT_EN_LBN 10
#define FCN_XM_TX_STAT_EN_WIDTH 1
#define FCN_XM_CUT_THRU_MODE_LBN 7
#define FCN_XM_CUT_THRU_MODE_WIDTH 1
#define FCN_XM_RX_JUMBO_MODE_LBN 6
#define FCN_XM_RX_JUMBO_MODE_WIDTH 1
/* XGMAC transmit configuration - port 0 */
#define FCN_XM_TX_CFG_REG_P0_KER 0x1230
#define FCN_XM_IPG_LBN 16
#define FCN_XM_IPG_WIDTH 4
#define FCN_XM_WTF_DOES_THIS_DO_LBN 9
#define FCN_XM_WTF_DOES_THIS_DO_WIDTH 1
#define FCN_XM_TXCRC_LBN 8
#define FCN_XM_TXCRC_WIDTH 1
#define FCN_XM_AUTO_PAD_LBN 5
#define FCN_XM_AUTO_PAD_WIDTH 1
#define FCN_XM_TX_PRMBL_LBN 2
#define FCN_XM_TX_PRMBL_WIDTH 1
#define FCN_XM_TXEN_LBN 1
#define FCN_XM_TXEN_WIDTH 1
/* XGMAC receive configuration - port 0 */
#define FCN_XM_RX_CFG_REG_P0_KER 0x1240
#define FCN_XM_PASS_CRC_ERR_LBN 25
#define FCN_XM_PASS_CRC_ERR_WIDTH 1
#define FCN_XM_AUTO_DEPAD_LBN 8
#define FCN_XM_AUTO_DEPAD_WIDTH 1
#define FCN_XM_RXEN_LBN 1
#define FCN_XM_RXEN_WIDTH 1
/* Receive descriptor pointer table */
#define FCN_RX_DESC_PTR_TBL_KER 0x11800
#define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36
#define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20
#define FCN_RX_DESCQ_EVQ_ID_LBN 24
#define FCN_RX_DESCQ_EVQ_ID_WIDTH 12
#define FCN_RX_DESCQ_OWNER_ID_LBN 10
#define FCN_RX_DESCQ_OWNER_ID_WIDTH 14
#define FCN_RX_DESCQ_SIZE_LBN 3
#define FCN_RX_DESCQ_SIZE_WIDTH 2
#define FCN_RX_DESCQ_SIZE_4K 3
#define FCN_RX_DESCQ_SIZE_2K 2
#define FCN_RX_DESCQ_SIZE_1K 1
#define FCN_RX_DESCQ_SIZE_512 0
#define FCN_RX_DESCQ_TYPE_LBN 2
#define FCN_RX_DESCQ_TYPE_WIDTH 1
#define FCN_RX_DESCQ_JUMBO_LBN 1
#define FCN_RX_DESCQ_JUMBO_WIDTH 1
#define FCN_RX_DESCQ_EN_LBN 0
#define FCN_RX_DESCQ_EN_WIDTH 1
/* Transmit descriptor pointer table */
#define FCN_TX_DESC_PTR_TBL_KER 0x11900
#define FCN_TX_DESCQ_EN_LBN 88
#define FCN_TX_DESCQ_EN_WIDTH 1
#define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36
#define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20
#define FCN_TX_DESCQ_EVQ_ID_LBN 24
#define FCN_TX_DESCQ_EVQ_ID_WIDTH 12
#define FCN_TX_DESCQ_OWNER_ID_LBN 10
#define FCN_TX_DESCQ_OWNER_ID_WIDTH 14
#define FCN_TX_DESCQ_SIZE_LBN 3
#define FCN_TX_DESCQ_SIZE_WIDTH 2
#define FCN_TX_DESCQ_SIZE_4K 3
#define FCN_TX_DESCQ_SIZE_2K 2
#define FCN_TX_DESCQ_SIZE_1K 1
#define FCN_TX_DESCQ_SIZE_512 0
#define FCN_TX_DESCQ_TYPE_LBN 1
#define FCN_TX_DESCQ_TYPE_WIDTH 2
#define FCN_TX_DESCQ_FLUSH_LBN 0
#define FCN_TX_DESCQ_FLUSH_WIDTH 1
/* Event queue pointer */
#define FCN_EVQ_PTR_TBL_KER 0x11a00
#define FCN_EVQ_EN_LBN 23
#define FCN_EVQ_EN_WIDTH 1
#define FCN_EVQ_SIZE_LBN 20
#define FCN_EVQ_SIZE_WIDTH 3
#define FCN_EVQ_SIZE_32K 6
#define FCN_EVQ_SIZE_16K 5
#define FCN_EVQ_SIZE_8K 4
#define FCN_EVQ_SIZE_4K 3
#define FCN_EVQ_SIZE_2K 2
#define FCN_EVQ_SIZE_1K 1
#define FCN_EVQ_SIZE_512 0
#define FCN_EVQ_BUF_BASE_ID_LBN 0
#define FCN_EVQ_BUF_BASE_ID_WIDTH 20
/* Event queue read pointer */
#define FCN_EVQ_RPTR_REG_KER 0x11b00
#define FCN_EVQ_RPTR_LBN 0
#define FCN_EVQ_RPTR_WIDTH 14
#define FCN_EVQ_RPTR_REG_KER_DWORD ( FCN_EVQ_RPTR_REG_KER + 0 )
#define FCN_EVQ_RPTR_DWORD_LBN 0
#define FCN_EVQ_RPTR_DWORD_WIDTH 14
/* Special buffer descriptors */
#define FCN_BUF_FULL_TBL_KER 0x18000
#define FCN_IP_DAT_BUF_SIZE_LBN 50
#define FCN_IP_DAT_BUF_SIZE_WIDTH 1
#define FCN_IP_DAT_BUF_SIZE_8K 1
#define FCN_IP_DAT_BUF_SIZE_4K 0
#define FCN_BUF_ADR_FBUF_LBN 14
#define FCN_BUF_ADR_FBUF_WIDTH 34
#define FCN_BUF_OWNER_ID_FBUF_LBN 0
#define FCN_BUF_OWNER_ID_FBUF_WIDTH 14
/* MAC registers */
#define FALCON_MAC_REGBANK 0xe00
#define FALCON_MAC_REGBANK_SIZE 0x200
#define FALCON_MAC_REG_SIZE 0x10
/** Offset of a MAC register within Falcon */
( FALCON_MAC_REGBANK + \
( (mac_reg) * FALCON_MAC_REG_SIZE ) )
#define FCN_MAC_DATA_LBN 0
#define FCN_MAC_DATA_WIDTH 32
/* Transmit descriptor */
#define FCN_TX_KER_PORT_LBN 63
#define FCN_TX_KER_PORT_WIDTH 1
#define FCN_TX_KER_BYTE_CNT_LBN 48
#define FCN_TX_KER_BYTE_CNT_WIDTH 14
#define FCN_TX_KER_BUF_ADR_LBN 0
/* Receive descriptor */
#define FCN_RX_KER_BUF_SIZE_LBN 48
#define FCN_RX_KER_BUF_SIZE_WIDTH 14
#define FCN_RX_KER_BUF_ADR_LBN 0
/* Event queue entries */
#define FCN_EV_CODE_LBN 60
#define FCN_EV_CODE_WIDTH 4
#define FCN_RX_IP_EV_DECODE 0
#define FCN_TX_IP_EV_DECODE 2
#define FCN_DRIVER_EV_DECODE 5
/* Receive events */
#define FCN_RX_PORT_LBN 30
#define FCN_RX_PORT_WIDTH 1
#define FCN_RX_EV_BYTE_CNT_LBN 16
#define FCN_RX_EV_BYTE_CNT_WIDTH 14
#define FCN_RX_EV_DESC_PTR_LBN 0
#define FCN_RX_EV_DESC_PTR_WIDTH 12
/* Transmit events */
#define FCN_TX_EV_DESC_PTR_LBN 0
#define FCN_TX_EV_DESC_PTR_WIDTH 12
/* Fixed special buffer numbers to use */
#define FALCON_EVQ_ID 0
#define FALCON_TXD_ID 1
#define FALCON_RXD_ID 2
/* Write dword via the I/O BAR */
unsigned int reg ) {
}
/* Read dword via the I/O BAR */
unsigned int reg ) {
}
#else /* FALCON_USE_IO_BAR */
#endif /* FALCON_USE_IO_BAR */
/**
* Write to a Falcon register
*
*/
unsigned int reg ) {
wmb();
}
/**
* Write to Falcon SRAM
*
*/
unsigned int index ) {
unsigned int reg = ( FCN_BUF_FULL_TBL_KER +
wmb();
}
/**
* Write dword to Falcon register that allows partial writes
*
*/
unsigned int reg ) {
}
/**
* Read from a Falcon register
*
*/
unsigned int reg ) {
}
/**
* Read from Falcon SRAM
*
*/
unsigned int index ) {
unsigned int reg = ( FCN_BUF_FULL_TBL_KER +
}
/**
* Read dword from a portion of a Falcon register
*
*/
unsigned int reg ) {
}
/**
* Verified write to Falcon SRAM
*
*/
unsigned int index ) {
udelay ( 1000 );
EFAB_QWORD_VAL ( *value ),
EFAB_QWORD_VAL ( verify ) );
}
}
/**
* Get memory base
*
*/
unsigned long membase_phys;
}
efab_oword_t reg; \
EFAB_OWORD_VAL ( reg ) ); \
} while ( 0 );
efab_dword_t reg; \
EFAB_DWORD_VAL ( reg ) ); \
} while ( 0 );
/**
* Dump register contents (for debugging)
*
* Marked as static inline so that it will not be compiled in if not
* used.
*/
}
/**
* Create special buffer
*
*/
unsigned long dma_addr;
FCN_BUF_OWNER_ID_FBUF, 0 );
}
/**
* Update event queue read pointer
*
*/
efab->eventq_read_ptr );
}
/**
* Reset device
*
*/
/* Initiate software reset */
FCN_SWRST, 1 );
/* Allow 20ms for reset */
mdelay ( 20 );
/* Check for device reset complete */
printf ( "Reset failed\n" );
return 0;
}
return 1;
}
/**
* Initialise NIC
*
*/
/* Set up TX and RX descriptor caches in SRAM */
0x130000 /* recommended in datasheet */ );
0x100000 /* recommended in datasheet */ );
/* Set number of RSS CPUs */
udelay ( 1000 );
/* Reset the MAC */
mentormac_reset ( efab );
/* Set up event queue */
FCN_EVQ_EN, 1,
udelay ( 1000 );
/* Set timer register */
FCN_TIMER_VAL, 0 );
udelay ( 1000 );
/* Initialise event queue read pointer */
/* Set up TX descriptor ring */
FCN_TX_DESCQ_EN, 1,
FCN_TX_DESCQ_TYPE, 0 /* kernel queue */ );
/* Set up RX descriptor ring */
FCN_RX_DESCQ_TYPE, 0 /* kernel queue */,
FCN_RX_DESCQ_EN, 1 );
/* Program INT_ADR_REG_KER */
udelay ( 1000 );
return 1;
}
/** SPI device */
struct efab_spi_device {
/** Device ID */
unsigned int device_id;
/** Address length (in bytes) */
unsigned int addr_len;
/** Read command */
unsigned int read_command;
};
/**
* Wait for SPI command completion
*
*/
int count;
count = 0;
do {
udelay ( 100 );
return 1;
} while ( ++count < 1000 );
printf ( "Timed out waiting for SPI\n" );
return 0;
}
/**
* Perform SPI read
*
*/
struct efab_spi_device *spi,
/* Program address register */
/* Issue read command */
/* Wait for read to complete */
if ( ! falcon_spi_wait ( efab ) )
return 0;
/* Read data */
return 1;
}
#define SPI_READ_CMD 0x03
#define AT25F1024_ADDR_LEN 3
#define AT25F1024_READ_CMD SPI_READ_CMD
#define MC25XX640_ADDR_LEN 2
#define MC25XX640_READ_CMD SPI_READ_CMD
/** Falcon Flash SPI device */
static struct efab_spi_device falcon_spi_flash = {
};
/** Falcon EEPROM SPI device */
static struct efab_spi_device falcon_spi_large_eeprom = {
};
/** Offset of MAC address within EEPROM or Flash */
/**
* Read MAC address from EEPROM
*
*/
int has_flash;
struct efab_spi_device *spi;
/* Determine the SPI device containing the MAC address */
}
/** RX descriptor */
typedef efab_qword_t falcon_rx_desc_t;
/**
* Build RX descriptor
*
*/
struct efab_rx_buf *rx_buf ) {
}
/**
* Update RX descriptor write pointer
*
*/
efab->rx_write_ptr );
}
/** TX descriptor */
typedef efab_qword_t falcon_tx_desc_t;
/**
* Build TX descriptor
*
*/
struct efab_tx_buf *tx_buf ) {
}
/**
* Update TX descriptor write pointer
*
*/
efab->tx_write_ptr );
}
/** An event */
typedef efab_qword_t falcon_event_t;
/**
* Retrieve event from event queue
*
*/
struct efab_event *event ) {
int ev_code;
int rx_port;
/* Check for event */
if ( EFAB_QWORD_IS_ZERO ( *evt ) ) {
/* No event */
return 0;
}
/* Decode event */
switch ( ev_code ) {
case FCN_TX_IP_EV_DECODE:
break;
case FCN_RX_IP_EV_DECODE:
/* Ignore packets on the wrong port. We can't
* just set event->type = EFAB_EV_NONE,
* because then the descriptor ring won't get
* refilled.
*/
}
break;
case FCN_DRIVER_EV_DECODE:
/* Ignore start-of-day events */
break;
default:
}
/* Clear event and any pending interrupts */
EFAB_ZERO_QWORD ( *evt );
udelay ( 10 );
/* Increment and update event queue read pointer */
% EFAB_EVQ_SIZE );
return 1;
}
/**
*
*/
int force ) {
}
/**
*
*/
if ( enabled ) {
/* Events won't trigger interrupts until we do this */
}
}
/**
* Generate interrupt
*
*/
}
/**
* Write dword to a Falcon MAC register
*
*/
}
/**
* Read dword from a Falcon MAC register
*
*/
unsigned int mac_reg ) {
}
/**
* Initialise MAC
*
*/
static struct efab_mentormac_parameters falcon_mentormac_params = {
.gmf_cfgfrth = 0x12,
.gmf_cfgftth = 0x08,
.gmf_cfghwmft = 0x1c,
.gmf_cfghwm = 0x3f,
.gmf_cfglwm = 0xa,
};
int link_speed;
/* Initialise PHY */
alaska_init ( efab );
/* Initialise MAC */
/* Configure the Falcon MAC wrapper */
FCN_XM_RX_STAT_EN, 1);
FCN_XM_TXEN, 1,
FCN_XM_TX_PRMBL, 1,
FCN_XM_AUTO_PAD, 1,
FCN_XM_TXCRC, 1,
FCN_XM_IPG, 0x3 );
FCN_XM_RXEN, 1,
FCN_XM_PASS_CRC_ERR, 1 );
#warning "10G support not yet present"
#define LPA_10000 0
link_speed = 0x3;
link_speed = 0x2;
link_speed = 0x1;
} else {
link_speed = 0x0;
}
FCN_MAC_UC_PROM, 0,
return 1;
}
/**
* Wait for GMII access to complete
*
*/
int count;
udelay ( 10 );
return 1;
}
printf ( "Timed out waiting for GMII\n" );
return 0;
}
/** MDIO write */
int value ) {
#warning "10G PHY access not yet in place"
EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n",
/* Check MII not currently being accessed */
if ( ! falcon_gmii_wait ( efab ) )
return;
/* Write the address registers */
udelay ( 10 );
udelay ( 10 );
/* Write data */
udelay ( 10 );
FCN_MD_WRC, 1,
FCN_MD_GC, 1 );
udelay ( 10 );
/* Wait for data to be written */
falcon_gmii_wait ( efab );
}
/** MDIO read */
int value;
/* Check MII not currently being accessed */
if ( ! falcon_gmii_wait ( efab ) )
return 0xffff;
/* Write the address registers */
udelay ( 10 );
udelay ( 10 );
/* Request data to be read */
FCN_MD_RIC, 1,
FCN_MD_GC, 1 );
udelay ( 10 );
/* Wait for data to become available */
falcon_gmii_wait ( efab );
/* Read the data */
EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
return value;
}
static struct efab_operations falcon_operations = {
.reset = falcon_reset,
};
/**************************************************************************
*
* Etherfabric abstraction layer
*
**************************************************************************
*/
/**
* Push RX buffer to RXD ring
*
*/
struct efab_rx_buf *rx_buf ) {
/* Create RX descriptor */
/* Update RX write pointer */
}
/**
* Push TX buffer to TXD ring
*
*/
struct efab_tx_buf *tx_buf ) {
/* Create TX descriptor */
/* Update TX write pointer */
}
/**
* Initialise MAC and wait for link up
*
*/
int count;
/* This can take several seconds */
printf ( "Waiting for link.." );
count = 0;
do {
putchar ( '.' );
printf ( "failed\n" );
return 0;
}
/* PHY init printed the message for us */
return 1;
}
sleep ( 1 );
} while ( ++count < 5 );
printf ( "timed out\n" );
return 0;
}
/**
* Initialise NIC
*
*/
int i;
/* Initialise NIC */
return 0;
/* Push RX descriptors */
for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
}
/* Read MAC address from EEPROM */
return 0;
/* Initialise MAC and wait for link up */
if ( ! efab_init_mac ( efab ) )
return 0;
return 1;
}
/**************************************************************************
*
* Etherboot interface
*
**************************************************************************
*/
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
struct efab_event event;
int i;
/* Process the event queue until we hit either a packet
* received event or an empty event slot.
*/
/* TX completed - mark as done */
DBG ( "TX id %x complete\n",
efab->tx_in_progress = 0;
/* RX - find corresponding buffer */
for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
DBG ( "RX id %x (len %x) received\n",
break;
}
}
if ( ! rx_buf ) {
}
DBG ( "Ignorable event\n" );
} else {
DBG ( "Unknown event\n" );
}
}
/* If there is no packet, return 0 */
if ( ! rx_buf )
return 0;
/* If we don't want to retrieve it just yet, return 1 */
if ( ! retrieve )
return 1;
/* There seems to be a hardware race. The event can show up
* on the event FIFO before the DMA has completed, so we
* insert a tiny delay. If this proves unreliable, we should
* switch to using event DMA rather than the event FIFO, since
* event DMA ordering is guaranteed.
*/
udelay ( 1 );
/* Copy packet contents */
/* Give this buffer back to the NIC */
/* Prepare to receive next packet */
return 1;
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
const char *data ) {
/* We can only transmit one packet at a time; a TX completion
* event must be received before we can transmit the next
* packet. Since there is only one static TX buffer, we don't
* worry unduly about overflow, but we report it anyway.
*/
if ( efab->tx_in_progress ) {
printf ( "TX overflow!\n" );
}
/* Fill TX buffer, pad to ETH_ZLEN */
}
/* Push TX descriptor */
/* There is no way to wait for TX complete (i.e. TX buffer
* available to re-use for the next transmit) without reading
* from the event queue. We therefore simply leave the TX
* buffer marked as "in use" until a TX completion event
* happens to be picked up by a call to etherfabric_poll().
*/
return;
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
}
/**************************************************************************
IRQ - handle interrupts
***************************************************************************/
switch ( action ) {
case DISABLE :
break;
case ENABLE :
break;
case FORCE :
/* Force NIC to generate a receive interrupt */
break;
}
return;
}
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
***************************************************************************/
static int nic_port = 1;
struct efab_buffers *buffers;
int i;
/* Set up our private data structure */
/* Hook in appropriate operations table. Do this early. */
} else {
}
/* Initialise efab data structure */
buffers = ( ( struct efab_buffers * )
( ( ( void * ) &efab_buffers ) +
for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
}
/* Enable the PCI device */
adjust_pci_device ( pci );
/* Switch NIC ports (i.e. try different ports on each probe) */
/* Initialise hardware */
if ( ! efab_init_nic ( &efab ) )
return 0;
/* hello world */
/* point to NIC specific routines */
return 1;
}
static struct pci_id etherfabric_nics[] = {
};
.type = NIC_DRIVER,
.name = "EFAB",
.ids = etherfabric_nics,
.class = 0,
};
/*
* Local variables:
* c-basic-offset: 8
* c-indent-level: 8
* tab-width: 8
* End:
*/