ops_sse.h revision 677833bc953b6cb418c701facbdcf4aa18d6c44e
/*
*
* Copyright (c) 2005 Fabrice Bellard
*
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if SHIFT == 0
#define XMM_ONLY(x...)
#define B(n) MMX_B(n)
#define W(n) MMX_W(n)
#define L(n) MMX_L(n)
#define Q(n) q
#else
#define XMM_ONLY(x...) x
#define B(n) XMM_B(n)
#define W(n) XMM_W(n)
#define L(n) XMM_L(n)
#define Q(n) XMM_Q(n)
#endif
{
Reg *d, *s;
int shift;
if (s->Q(0) > 15) {
d->Q(0) = 0;
#if SHIFT == 1
d->Q(1) = 0;
#endif
} else {
shift = s->B(0);
d->W(0) >>= shift;
d->W(1) >>= shift;
d->W(2) >>= shift;
d->W(3) >>= shift;
#if SHIFT == 1
d->W(4) >>= shift;
d->W(5) >>= shift;
d->W(6) >>= shift;
d->W(7) >>= shift;
#endif
}
FORCE_RET();
}
{
Reg *d, *s;
int shift;
if (s->Q(0) > 15) {
shift = 15;
} else {
shift = s->B(0);
}
#if SHIFT == 1
#endif
}
{
Reg *d, *s;
int shift;
if (s->Q(0) > 15) {
d->Q(0) = 0;
#if SHIFT == 1
d->Q(1) = 0;
#endif
} else {
shift = s->B(0);
d->W(0) <<= shift;
d->W(1) <<= shift;
d->W(2) <<= shift;
d->W(3) <<= shift;
#if SHIFT == 1
d->W(4) <<= shift;
d->W(5) <<= shift;
d->W(6) <<= shift;
d->W(7) <<= shift;
#endif
}
FORCE_RET();
}
{
Reg *d, *s;
int shift;
if (s->Q(0) > 31) {
d->Q(0) = 0;
#if SHIFT == 1
d->Q(1) = 0;
#endif
} else {
shift = s->B(0);
d->L(0) >>= shift;
d->L(1) >>= shift;
#if SHIFT == 1
d->L(2) >>= shift;
d->L(3) >>= shift;
#endif
}
FORCE_RET();
}
{
Reg *d, *s;
int shift;
if (s->Q(0) > 31) {
shift = 31;
} else {
shift = s->B(0);
}
#if SHIFT == 1
#endif
}
{
Reg *d, *s;
int shift;
if (s->Q(0) > 31) {
d->Q(0) = 0;
#if SHIFT == 1
d->Q(1) = 0;
#endif
} else {
shift = s->B(0);
d->L(0) <<= shift;
d->L(1) <<= shift;
#if SHIFT == 1
d->L(2) <<= shift;
d->L(3) <<= shift;
#endif
}
FORCE_RET();
}
{
Reg *d, *s;
int shift;
if (s->Q(0) > 63) {
d->Q(0) = 0;
#if SHIFT == 1
d->Q(1) = 0;
#endif
} else {
shift = s->B(0);
d->Q(0) >>= shift;
#if SHIFT == 1
d->Q(1) >>= shift;
#endif
}
FORCE_RET();
}
{
Reg *d, *s;
int shift;
if (s->Q(0) > 63) {
d->Q(0) = 0;
#if SHIFT == 1
d->Q(1) = 0;
#endif
} else {
shift = s->B(0);
d->Q(0) <<= shift;
#if SHIFT == 1
d->Q(1) <<= shift;
#endif
}
FORCE_RET();
}
#if SHIFT == 1
{
Reg *d, *s;
int shift, i;
shift = s->L(0);
if (shift > 16)
shift = 16;
for(i = 0; i < 16 - shift; i++)
d->B(i) = d->B(i + shift);
d->B(i) = 0;
FORCE_RET();
}
{
Reg *d, *s;
int shift, i;
shift = s->L(0);
if (shift > 16)
shift = 16;
for(i = 15; i >= shift; i--)
d->B(i) = d->B(i - shift);
for(i = 0; i < shift; i++)
d->B(i) = 0;
FORCE_RET();
}
#endif
{\
Reg *d, *s;\
d->B(0) = F(d->B(0), s->B(0));\
d->B(1) = F(d->B(1), s->B(1));\
d->B(2) = F(d->B(2), s->B(2));\
d->B(3) = F(d->B(3), s->B(3));\
d->B(4) = F(d->B(4), s->B(4));\
d->B(5) = F(d->B(5), s->B(5));\
d->B(6) = F(d->B(6), s->B(6));\
d->B(7) = F(d->B(7), s->B(7));\
XMM_ONLY(\
d->B(8) = F(d->B(8), s->B(8));\
d->B(9) = F(d->B(9), s->B(9));\
d->B(10) = F(d->B(10), s->B(10));\
d->B(11) = F(d->B(11), s->B(11));\
d->B(12) = F(d->B(12), s->B(12));\
d->B(13) = F(d->B(13), s->B(13));\
d->B(14) = F(d->B(14), s->B(14));\
d->B(15) = F(d->B(15), s->B(15));\
)\
}
{\
Reg *d, *s;\
d->W(0) = F(d->W(0), s->W(0));\
d->W(1) = F(d->W(1), s->W(1));\
d->W(2) = F(d->W(2), s->W(2));\
d->W(3) = F(d->W(3), s->W(3));\
XMM_ONLY(\
d->W(4) = F(d->W(4), s->W(4));\
d->W(5) = F(d->W(5), s->W(5));\
d->W(6) = F(d->W(6), s->W(6));\
d->W(7) = F(d->W(7), s->W(7));\
)\
}
{\
Reg *d, *s;\
d->L(0) = F(d->L(0), s->L(0));\
d->L(1) = F(d->L(1), s->L(1));\
XMM_ONLY(\
d->L(2) = F(d->L(2), s->L(2));\
d->L(3) = F(d->L(3), s->L(3));\
)\
}
{\
Reg *d, *s;\
d->Q(0) = F(d->Q(0), s->Q(0));\
XMM_ONLY(\
d->Q(1) = F(d->Q(1), s->Q(1));\
)\
}
#if SHIFT == 0
static inline int satub(int x)
{
if (x < 0)
return 0;
else if (x > 255)
return 255;
else
return x;
}
static inline int satuw(int x)
{
if (x < 0)
return 0;
else if (x > 65535)
return 65535;
else
return x;
}
static inline int satsb(int x)
{
if (x < -128)
return -128;
else if (x > 127)
return 127;
else
return x;
}
static inline int satsw(int x)
{
if (x < -32768)
return -32768;
else if (x > 32767)
return 32767;
else
return x;
}
#define FADD(a, b) ((a) + (b))
#define FSUB(a, b) ((a) - (b))
#define FMINUB(a, b) ((a) < (b)) ? (a) : (b)
#define FMAXUB(a, b) ((a) > (b)) ? (a) : (b)
#define FAND(a, b) (a) & (b)
#define FANDN(a, b) ((~(a)) & (b))
#define FOR(a, b) (a) | (b)
#define FXOR(a, b) (a) ^ (b)
#define FCMPEQ(a, b) (a) == (b) ? -1 : 0
#define FMULLW(a, b) (a) * (b)
#define FMULHUW(a, b) (a) * (b) >> 16
#endif
{
Reg *d, *s;
#if SHIFT == 1
#endif
}
{
int i;
Reg *d, *s;
for(i = 0; i < (2 << SHIFT); i++) {
}
FORCE_RET();
}
#if SHIFT == 0
static inline int abs1(int a)
{
if (a < 0)
return -a;
else
return a;
}
#endif
{
unsigned int val;
Reg *d, *s;
val = 0;
d->Q(0) = val;
#if SHIFT == 1
val = 0;
d->Q(1) = val;
#endif
}
{
int i;
Reg *d, *s;
for(i = 0; i < (8 << SHIFT); i++) {
if (s->B(i) & 0x80)
}
FORCE_RET();
}
{
Reg *d;
d->L(0) = T0;
d->L(1) = 0;
#if SHIFT == 1
d->Q(1) = 0;
#endif
}
{
Reg *s;
T0 = s->L(0);
}
#if SHIFT == 0
{
Reg r, *d, *s;
int order;
r.W(0) = s->W(order & 3);
*d = r;
}
#else
{
Reg r, *d, *s;
int order;
r.L(0) = d->L(order & 3);
*d = r;
}
{
Reg r, *d, *s;
int order;
r.Q(0) = d->Q(order & 1);
*d = r;
}
{
Reg r, *d, *s;
int order;
r.L(0) = s->L(order & 3);
*d = r;
}
{
Reg r, *d, *s;
int order;
r.W(0) = s->W(order & 3);
r.Q(1) = s->Q(1);
*d = r;
}
{
Reg r, *d, *s;
int order;
r.Q(0) = s->Q(0);
*d = r;
}
#endif
#if SHIFT == 1
/* FPU ops */
/* XXX: not accurate */
{\
Reg *d, *s;\
}\
\
{\
Reg *d, *s;\
}\
{\
Reg *d, *s;\
}\
\
{\
Reg *d, *s;\
}
/* float to float conversions */
void OPPROTO op_cvtps2pd(void)
{
Reg *d, *s;
}
void OPPROTO op_cvtpd2ps(void)
{
Reg *d, *s;
d->Q(1) = 0;
}
void OPPROTO op_cvtss2sd(void)
{
Reg *d, *s;
}
void OPPROTO op_cvtsd2ss(void)
{
Reg *d, *s;
}
/* integer to float */
void OPPROTO op_cvtdq2ps(void)
{
}
void OPPROTO op_cvtdq2pd(void)
{
}
void OPPROTO op_cvtpi2ps(void)
{
}
void OPPROTO op_cvtpi2pd(void)
{
}
void OPPROTO op_cvtsi2ss(void)
{
}
void OPPROTO op_cvtsi2sd(void)
{
}
#ifdef TARGET_X86_64
void OPPROTO op_cvtsq2ss(void)
{
}
void OPPROTO op_cvtsq2sd(void)
{
}
#endif
/* float to integer */
void OPPROTO op_cvtps2dq(void)
{
}
void OPPROTO op_cvtpd2dq(void)
{
d->XMM_Q(1) = 0;
}
void OPPROTO op_cvtps2pi(void)
{
}
void OPPROTO op_cvtpd2pi(void)
{
}
void OPPROTO op_cvtss2si(void)
{
}
void OPPROTO op_cvtsd2si(void)
{
}
#ifdef TARGET_X86_64
void OPPROTO op_cvtss2sq(void)
{
}
void OPPROTO op_cvtsd2sq(void)
{
}
#endif
/* float to integer truncated */
void OPPROTO op_cvttps2dq(void)
{
}
void OPPROTO op_cvttpd2dq(void)
{
d->XMM_Q(1) = 0;
}
void OPPROTO op_cvttps2pi(void)
{
}
void OPPROTO op_cvttpd2pi(void)
{
}
void OPPROTO op_cvttss2si(void)
{
}
void OPPROTO op_cvttsd2si(void)
{
}
#ifdef TARGET_X86_64
void OPPROTO op_cvttss2sq(void)
{
}
void OPPROTO op_cvttsd2sq(void)
{
}
#endif
void OPPROTO op_rsqrtps(void)
{
}
void OPPROTO op_rsqrtss(void)
{
}
{
}
{
}
{
XMMReg r;
*d = r;
}
{
XMMReg r;
*d = r;
}
{
XMMReg r;
*d = r;
}
{
XMMReg r;
*d = r;
}
void OPPROTO op_addsubps(void)
{
}
void OPPROTO op_addsubpd(void)
{
}
/* XXX: unordered */
#define SSE_OP_CMP(name, F)\
{\
Reg *d, *s;\
}\
\
{\
Reg *d, *s;\
}\
{\
Reg *d, *s;\
}\
\
{\
Reg *d, *s;\
}
void OPPROTO op_ucomiss(void)
{
int ret;
Reg *d, *s;
FORCE_RET();
}
{
int ret;
Reg *d, *s;
FORCE_RET();
}
void OPPROTO op_ucomisd(void)
{
int ret;
Reg *d, *s;
FORCE_RET();
}
{
int ret;
Reg *d, *s;
FORCE_RET();
}
void OPPROTO op_movmskps(void)
{
Reg *s;
}
void OPPROTO op_movmskpd(void)
{
Reg *s;
}
#endif
{
Reg *s;
T0 = 0;
#if SHIFT == 1
#endif
}
{
}
{
}
{
Reg r, *d, *s;
#if SHIFT == 1
#endif
#if SHIFT == 1
#endif
*d = r;
}
{
Reg r, *d, *s;
#if SHIFT == 1
#endif
#if SHIFT == 1
#endif
*d = r;
}
{
Reg r, *d, *s;
r.W(0) = satsw(d->L(0));
#if SHIFT == 1
#endif
#if SHIFT == 1
#endif
*d = r;
}
\
{ \
Reg r, *d, *s; \
\
XMM_ONLY( \
) \
*d = r; \
} \
\
{ \
Reg r, *d, *s; \
\
XMM_ONLY( \
) \
*d = r; \
} \
\
{ \
Reg r, *d, *s; \
\
XMM_ONLY( \
) \
*d = r; \
} \
\
XMM_ONLY( \
{ \
Reg r, *d, *s; \
\
r.Q(0) = d->Q(base); \
r.Q(1) = s->Q(base); \
*d = r; \
} \
)
UNPCK_OP(l, 0)
UNPCK_OP(h, 1)
#undef B
#undef W
#undef L
#undef Q