eepro.c revision 677833bc953b6cb418c701facbdcf4aa18d6c44e
#ifdef ALLMULTI
#endif
/**************************************************************************
Intel EEPRO/10 NIC driver for Etherboot
Adapted from Linux eepro.c from kernel 2.2.17
This board accepts a 32 pin EEPROM (29C256), however a test with a
27C010 shows that this EPROM also works in the socket, but it's not clear
how repeatably. The two top address pins appear to be held low, thus
the bottom 32kB of the 27C010 is visible in the CPU's address space.
To be sure you could put 4 copies of the code in the 27C010, then
it doesn't matter whether the extra lines are held low or high, just
hopefully not floating as CMOS chips don't like floating inputs.
Be careful with seating the EPROM as the socket on my board actually
has 34 pins, the top row of 2 are not used.
***************************************************************************/
/*
timlegge 2005-05-18 remove the relocation changes cards that
write directly to the hardware don't need it
*/
/*
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
/* to get some global routines like printf */
#include "etherboot.h"
/* to get the interface to the body of the program */
#include "nic.h"
#include "isa.h"
/* we use timer2 for microsecond waits */
#include "timer.h"
/* Different 82595 chips */
#define LAN595 0
#define LAN595TX 1
#define LAN595FX 2
#define LAN595FX_10ISA 3
/* The station (ethernet) address prefix, used for IDing the board. */
#define SA_ADDR1 0xaa
#define SA_ADDR2 0x00
#define GetBit(x,y) ((x & (1<<y))>>y)
/* EEPROM Word 0: */
#define ee_PnP 0 /* Plug 'n Play enable bit */
#define ee_IO0Mask 0x /*...*/
/* EEPROM Word 1: */
#define ee_IntSel 0 /* Interrupt */
#define ee_IntMask 0x7
#define ee_Duplex 15
/* Word2,3,4: */
#define ee_IA5 0 /*bit start for individual Addr Byte 5 */
#define ee_IA3 0 /*bit start for individual Addr Byte 5 */
#define ee_IA1 0 /*bit start for individual Addr Byte 5 */
/* Word 5: */
#define ee_BNC_TPE 0 /* 0=TPE */
#define ee_BootTypeMask 0x3
#define ee_PortTPE 5
#define ee_PortBNC 6
#define ee_PortAUI 7
#define ee_CPMask 0x7
/* Word 6: */
#define ee_Stepping 0 /* Stepping info */
#define ee_StepMask 0x0F
#define ee_BoardMask 0x0FFF
/* Word 7: */
#define ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */
/*..*/
/* Card identification via EEprom: */
#define ee_vendor_intel1 0xD4
#define ee_id_eepro10p1 0x31
/* now this section could be used by both boards: the oldies and the ee10:
* ee10 uses tx buffer before of rx buffer and the oldies the inverse.
* (aris)
*/
#define RAM_SIZE 0x8000
#define RCV_HEADER 8
#define RCV_DEFAULT_RAM 0x6000
static unsigned rcv_ram = RCV_DEFAULT_RAM;
#define XMT_HEADER 8
#define RCV_START_PRO 0x00
#define RCV_START_10 XMT_RAM
/* by default the old driver */
static unsigned rcv_start = RCV_START_PRO;
#define RCV_DONE 0x0008
#define RX_OK 0x2000
#define RX_ERROR 0x0d81
#define TX_DONE_BIT 0x0080
#define CHAIN_BIT 0x8000
#define XMT_STATUS 0x02
#define XMT_CHAIN 0x04
#define XMT_COUNT 0x06
#define BANK0_SELECT 0x00
#define BANK1_SELECT 0x40
#define BANK2_SELECT 0x80
/* Bank 0 registers */
#define MC_SETUP 0x03
#define XMT_CMD 0x04
#define DIAGNOSE_CMD 0x07
#define RCV_ENABLE_CMD 0x08
#define RCV_DISABLE_CMD 0x0a
#define STOP_RCV_CMD 0x0b
#define RESET_CMD 0x0e
#define POWER_DOWN_CMD 0x18
#define RESUME_XMT_CMD 0x1c
#define SEL_RESET_CMD 0x1e
#define RX_INT 0x02
#define TX_INT 0x04
#define EXEC_STATUS 0x30
#define ID_REG_MASK 0x2c
#define ID_REG_SIG 0x24
#define AUTO_ENABLE 0x10
#define RX_STOP_MASK 0x01
#define RX_MASK 0x02
#define TX_MASK 0x04
#define EXEC_MASK 0x08
#define ALL_MASK 0x0f
#define IO_32_BIT 0x10
#define RCV_STOP 0x06
#define XMT_BAR_PRO 0x0a
#define XMT_BAR_10 0x0b
static unsigned xmt_bar = XMT_BAR_PRO;
#define HOST_ADDRESS_REG 0x0c
#define IO_PORT 0x0e
#define IO_PORT_32_BIT 0x0c
/* Bank 1 registers */
#define REG1 0x01
#define WORD_WIDTH 0x02
#define INT_ENABLE 0x80
#define INT_NO_REG 0x02
#define RCV_LOWER_LIMIT_REG 0x08
#define RCV_UPPER_LIMIT_REG 0x09
#define XMT_LOWER_LIMIT_REG_PRO 0x0a
#define XMT_UPPER_LIMIT_REG_PRO 0x0b
#define XMT_LOWER_LIMIT_REG_10 0x0b
#define XMT_UPPER_LIMIT_REG_10 0x0a
static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO;
static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO;
/* Bank 2 registers */
#define REG2 0x02
#define PRMSC_Mode 0x01
#define Multi_IA 0x20
#define REG3 0x03
#define TPE_BIT 0x04
#define BNC_BIT 0x20
#define REG13 0x0d
#define FDX 0x00
#define A_N_ENABLE 0x02
#define I_ADD_REG0 0x04
#define I_ADD_REG1 0x05
#define I_ADD_REG2 0x06
#define I_ADD_REG3 0x07
#define I_ADD_REG4 0x08
#define I_ADD_REG5 0x09
#define EEPROM_REG_PRO 0x0a
#define EEPROM_REG_10 0x0b
static unsigned eeprom_reg = EEPROM_REG_PRO;
#define EESK 0x01
#define EECS 0x02
#define EEDI 0x04
#define EEDO 0x08
/* The horrible routine to read a word from the serial EEPROM. */
/* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */
/* The delay between EEPROM clock transitions. */
/* do a full reset; data sheet asks for 250us delay */
/* do a nice reset */
#define eepro_sel_reset(ioaddr) { \
SLOW_DOWN; \
SLOW_DOWN; \
}
/* clear all interrupts */
/* enable rx */
/* disable rx */
/* switch bank */
static int tx_last;
static unsigned int tx_end;
static int eepro = 0;
static unsigned short ioaddr = 0;
/**************************************************************************
RESET - Reset adapter
***************************************************************************/
{
int temp_reg, i;
/* put the card in its initial state */
#ifdef DEBUG
#endif
for (i = 0; i < ETH_ALEN; i++) /* fill the MAC address */
/* setup Transmit Chaining and discard bad RCV frames */
/* set the receiving mode */
/* initialise the RCV and XMT upper and lower limits */
/* Initialise RCV */
/* Make sure 1st poll won't find a valid packet header */
/* Intialise XMT */
tx_last = 0;
}
/* extern void hex_dump(const char *data, const unsigned int len); */
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
#if 0
return (0);
#endif
return (0);
/* FIXME: I'm guessing this might not work with this card, since
it looks like once a rcv_event is started it must be completed.
maybe there's another way. */
if ( ! retrieve ) return 1;
#if 0
#endif
return (0);
}
rcv_size &= 0x3FFF;
#if 0
{
int i;
for (i = 0; i < 48; i++) {
}
}
#endif
/*
hex_dump(rcv_car, nic->packetlen);
*/
if (rcv_car == 0)
return (1);
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
static void eepro_transmit(
const char *d, /* Destination */
unsigned int t, /* Type */
unsigned int s, /* size */
const char *p) /* Packet */
{
unsigned short type;
int boguscount = 20;
else
}
/* A dummy read to flush the DRAM write pipeline */
#if 0
#endif
while (boguscount > 0) {
udelay(40);
boguscount--;
continue;
}
#if DEBUG
if ((status & 0x2000) == 0)
#endif
}
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
{
/* Flush the Tx and disable Rx */
tx_last = 0;
/* Reset the 82595 */
}
/**************************************************************************
DISABLE - Enable, Disable, or Force interrupts
***************************************************************************/
{
switch ( action ) {
case DISABLE :
break;
case ENABLE :
break;
case FORCE :
break;
}
}
static int read_eeprom(int location)
{
int i;
unsigned short retval = 0;
if (eepro == LAN595FX_10ISA) {
}
/* shift the read command bits out */
for (i = 8; i >= 0; i--) {
eeprom_delay();
eeprom_delay();
}
for (i = 16; i > 0; i--) {
eeprom_delay();
eeprom_delay();
}
/* terminate the EEPROM access */
eeprom_delay();
eeprom_delay();
return (retval);
}
{
union {
} station_addr;
char *name;
return (0);
return (0);
/* yes the 82595 has been found */
l_eepro = 3;
}
if (l_eepro)
name = "Intel EtherExpress 10 ISA";
name = "Intel EtherExpress Pro/10+ ISA";
l_eepro = 2;
name = "Intel EtherExpress Pro/10 ISA";
l_eepro = 1;
} else {
l_eepro = 0;
name = "Intel 82595-based LAN card";
}
for (i = 0; i < ETH_ALEN; i++) {
}
else {
}
return (1);
}
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
***************************************************************************/
{
unsigned short *p;
/* same probe list as the Linux driver */
static unsigned short ioaddrs[] = {
0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360, 0};
if (probe_addrs == 0 || probe_addrs[0] == 0)
for (p = probe_addrs; (ioaddr = *p) != 0; p++) {
if (eepro_probe1(nic))
break;
}
if (*p == 0)
return (0);
/* point to NIC specific routines */
/* Based on PnP ISA map */
return 1;
}
.type = NIC_DRIVER,
.name = "EEPRO",
.probe = eepro_probe,
.ioaddrs = 0,
};