Searched refs:clock (Results 1 - 25 of 27) sorted by relevance

12

/solaris-x11-s11/open-src/lib/libXaw4/sun-src/
H A DXaw3_1Clock.c65 #define offset(field) XtOffset(ClockWidget,clock.field)
166 if (w->clock.font != NULL)
167 myXGCV.font = w->clock.font->fid;
172 if(!w->clock.analog) {
179 if (w->clock.font == NULL)
180 w->clock.font = XQueryFont( XtDisplay(w),
183 min_width = XTextWidth(w->clock.font, str, strlen(str)) +
184 2 * w->clock.padding;
185 min_height = w->clock.font->ascent +
186 w->clock
[all...]
H A DXaw3_1ClockP.h40 /* New fields for the clock widget instance record */
79 ClockPart clock; member in struct:_ClockRec
/solaris-x11-s11/open-src/kernel/drm/src/
H A Ddrm_modes.c56 mode->base.id, mode->name, mode->vrefresh, mode->clock,
262 /* 15/13. Find pixel clock frequency (kHz for xf86) */
263 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
264 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
430 /* 21.Find pixel clock frequency: */
455 drm_mode->clock = pixel_freq;
524 dmode->clock = vm->pixelclock / 1000;
673 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */
707 calc_val = (mode->clock * 100
[all...]
H A Ddrm_edid.c56 /* Reported 135MHz pixel clock is too high, needs adjustment */
1659 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1771 if (mode->clock > max_clock)
2244 * Calculate the alternate clock for the CEA mode
2250 unsigned int clock = cea_mode->clock; local
2253 return clock;
2261 clock = clock * 1001 / 1000;
2263 clock
[all...]
/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_display.c60 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
222 * We calculate clock using (register_value + 2) for N/M1/M2, so here
412 static void pineview_clock(int refclk, intel_clock_t *clock) argument
414 clock->m = clock->m2 + 2;
415 clock->p = clock->p1 * clock->p2;
416 clock->vco = refclk * clock
425 i9xx_clock(int refclk, intel_clock_t *clock) argument
454 intel_PLL_is_valid(struct drm_device *dev, const intel_limit_t *limit, const intel_clock_t *clock) argument
489 intel_clock_t clock; local
550 intel_clock_t clock; local
609 intel_clock_t clock; local
4534 struct dpll *clock = &crtc->config.dpll; local
4633 struct dpll *clock = &crtc->config.dpll; local
4858 intel_clock_t clock, reduced_clock; local
5503 ironlake_compute_clocks(struct drm_crtc *crtc, intel_clock_t *clock, bool *has_reduced_clock, intel_clock_t *reduced_clock) argument
5708 intel_clock_t clock, reduced_clock; local
6949 intel_clock_t clock; local
[all...]
H A Dintel_pm.c55 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
1030 * @clock_in_khz: pixel clock
1040 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1055 * Note: we need to make sure we don't overflow for various clock &
1111 int clock = crtc->mode.clock; local
1115 wm = intel_calculate_wm(clock, &pineview_display_wm,
1125 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1134 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1143 wm = intel_calculate_wm(clock,
1172 int htotal, hdisplay, clock, pixel_size; local
1256 int hdisplay, htotal, pixel_size, clock; local
1302 int clock, pixel_size; local
1494 int clock = crtc->mode.clock; local
1613 int clock = enabled->mode.clock; local
1751 int hdisplay, htotal, pixel_size, clock; local
2662 int clock; local
2695 int clock; local
[all...]
H A Dintel_bios.c100 panel_fixed_mode->clock = dvo_timing->clock * 10;
256 downclock = panel_dvo_timing->clock;
264 dvo_timing->clock < downclock)
265 downclock = dvo_timing->clock;
268 if (downclock < panel_dvo_timing->clock && i915_lvds_downclock) {
273 panel_fixed_mode->clock, 10*downclock);
H A Dintel_sdvo.c89 /* Pixel clock limitations reported by the SDVO device, in kHz */
582 if (mode->clock >= 100000)
584 else if (mode->clock >= 50000)
745 uint16_t clock,
752 args.clock = clock;
802 mode_clock = mode->clock;
804 dtd->part1.clock = (u16) mode_clock;
860 mode->clock = dtd->part1.clock * 1
744 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, uint16_t clock, uint16_t width, uint16_t height) argument
1057 struct dpll *clock = &pipe_config->dpll; local
[all...]
H A Dintel_tv.c359 int clock; member in struct:tv_mode
412 * The constants below were all computed using a 107.520MHz clock
424 .clock = 108000,
451 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
467 .clock = 108000,
493 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
509 .clock = 108000,
536 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
552 .clock = 108000,
579 /* desired 3.5800000 actual 3.5800000 clock 107.5
[all...]
H A Ddvo_ch7xxx.c278 if (mode->clock > 165000)
291 if (mode->clock <= 65000) {
H A Dintel_ddi.c433 static unsigned wrpll_get_budget_for_freq(int clock) argument
437 switch (clock) {
522 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
567 intel_ddi_calculate_wrpll(int clock /* in Hz */,
575 freq2k = clock / 100;
577 budget = wrpll_get_budget_for_freq(clock);
579 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
631 clock, *p_out, *n2_out, *r2_out);
644 int clock = intel_crtc->config.port_clock; local
695 intel_ddi_calculate_wrpll(clock * 100
[all...]
H A Ddvo_ch7017.c257 if (mode->clock > 160000)
278 if (mode->clock < 100000) {
H A Dintel_lvds.c736 temp_downclock = fixed_mode->clock;
753 if (scan->clock < temp_downclock) {
758 temp_downclock = scan->clock;
762 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
767 "Normal clock %dKhz, downclock %dKhz\n",
768 fixed_mode->clock, temp_downclock);
H A Dintel_crt.c211 if (mode->clock < 25000)
218 if (mode->clock > max_clock)
223 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
H A Dintel_dp.c105 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
132 int target_clock = mode->clock;
142 target_clock = fixed_mode->clock;
154 if (mode->clock < 10000)
307 /* The clock divider is based off the hrawclk,
312 * clock divider.
321 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
323 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
690 int lane_count, clock; local
717 "max bw %02x pixel clock
[all...]
H A Dintel_sdvo_regs.h81 u16 clock; /**< pixel clock, in 10kHz units */ member in struct:intel_sdvo_dtd::__anon169
111 u16 min; /**< pixel clock, in 10kHz units */
112 u16 max; /**< pixel clock, in 10kHz units */
118 u16 clock; member in struct:intel_sdvo_preferred_input_timing_args
H A Ddvo_ivch.c64 /** Enables the DVO clock */
290 if (mode->clock > 112000)
H A Dintel_panel.c53 adjusted_mode->clock = fixed_mode->clock;
H A Dintel_hdmi.c816 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
818 if (mode->clock < 20000)
833 int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
855 * outputs. We also need to check that the higher clock still fits
875 if (adjusted_mode->clock > portclock_limit) {
876 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1044 /* Enable clock channels for this port */
1070 /* Program lane clock */
H A Di915_gem_debug.c463 print_clock(char *name, int clock) { argument
464 if (clock == -1)
465 DRM_ERROR("%s clock: unknown", name);
467 DRM_ERROR("%s clock: %d Mhz", name, clock);
H A Dintel_bios.h354 u16 clock; /**< In 10khz */ member in struct:lvds_dvo_timing
H A Dintel_dvo.c236 /* XXX: Validate clock range */
269 C(clock);
/solaris-x11-s11/open-src/kernel/efb/src/
H A Ddrm_mode.h89 __u32 clock; member in struct:drm_mode_modeinfo
/solaris-x11-s11/open-src/kernel/sys/drm/
H A Ddrm_mode.h89 __u32 clock; member in struct:drm_mode_modeinfo
H A Ddrm_crtc.h90 MODE_NOCLOCK, /* no fixed clock available */
91 MODE_CLOCK_HIGH, /* clock required is too high */
92 MODE_CLOCK_LOW, /* clock required is too low */
93 MODE_CLOCK_RANGE, /* clock/mode isn't in a ClockRange */
120 .name = nm, .status = 0, .type = (t), .clock = (c), \
140 int clock; /* in kHz */ member in struct:drm_display_mode
575 * @max_tmds_clock: max clock rate, if found

Completed in 118 milliseconds

12