Lines Matching refs:clock
89 /* Pixel clock limitations reported by the SDVO device, in kHz */
582 if (mode->clock >= 100000)
584 else if (mode->clock >= 50000)
745 uint16_t clock,
752 args.clock = clock;
802 mode_clock = mode->clock;
804 dtd->part1.clock = (u16) mode_clock;
860 mode->clock = dtd->part1.clock * 10;
1039 mode->clock / 10,
1056 unsigned dotclock = pipe_config->adjusted_mode.clock;
1057 struct dpll *clock = &pipe_config->dpll;
1059 /* SDVO TV has fixed PLL values depend on its clock range,
1062 clock->p1 = 2;
1063 clock->p2 = 10;
1064 clock->n = 3;
1065 clock->m1 = 16;
1066 clock->m2 = 8;
1068 clock->p1 = 1;
1069 clock->p2 = 10;
1070 clock->n = 6;
1071 clock->m1 = 12;
1072 clock->m2 = 8;
1074 DRM_ERROR("SDVO TV clock out of range: %i\n", dotclock);
1121 adjusted_mode->clock *= pipe_config->pixel_multiplier;
1511 if (intel_sdvo->pixel_clock_min > mode->clock)
1514 if (intel_sdvo->pixel_clock_max < mode->clock)
1737 /* May update encoder flag for like clock for SDVO TV, etc.*/
2933 "clock range %dMHz - %dMHz, "