Lines Matching refs:clock
60 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
222 * We calculate clock using (register_value + 2) for N/M1/M2, so here
412 static void pineview_clock(int refclk, intel_clock_t *clock)
414 clock->m = clock->m2 + 2;
415 clock->p = clock->p1 * clock->p2;
416 clock->vco = refclk * clock->m / clock->n;
417 clock->dot = clock->vco / clock->p;
425 static void i9xx_clock(int refclk, intel_clock_t *clock)
427 clock->m = i9xx_dpll_compute_m(clock);
428 clock->p = clock->p1 * clock->p2;
429 clock->vco = refclk * clock->m / (clock->n + 2);
430 clock->dot = clock->vco / clock->p;
456 const intel_clock_t *clock)
458 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
460 if (clock->p < limit->p.min || limit->p.max < clock->p)
462 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
464 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
466 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
468 if (clock->m < limit->m.min || limit->m.max < clock->m)
470 if (clock->n < limit->n.min || limit->n.max < clock->n)
472 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
474 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
477 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
489 intel_clock_t clock;
499 clock.p2 = limit->p2.p2_fast;
501 clock.p2 = limit->p2.p2_slow;
504 clock.p2 = limit->p2.p2_slow;
506 clock.p2 = limit->p2.p2_fast;
511 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
512 clock.m1++) {
513 for (clock.m2 = limit->m2.min;
514 clock.m2 <= limit->m2.max; clock.m2++) {
515 if (clock.m2 >= clock.m1)
517 for (clock.n = limit->n.min;
518 clock.n <= limit->n.max; clock.n++) {
519 for (clock.p1 = limit->p1.min;
520 clock.p1 <= limit->p1.max; clock.p1++) {
523 i9xx_clock(refclk, &clock);
525 &clock))
528 clock.p != match_clock->p)
531 this_err = abs(clock.dot - target);
533 *best_clock = clock;
550 intel_clock_t clock;
560 clock.p2 = limit->p2.p2_fast;
562 clock.p2 = limit->p2.p2_slow;
565 clock.p2 = limit->p2.p2_slow;
567 clock.p2 = limit->p2.p2_fast;
572 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
573 clock.m1++) {
574 for (clock.m2 = limit->m2.min;
575 clock.m2 <= limit->m2.max; clock.m2++) {
576 for (clock.n = limit->n.min;
577 clock.n <= limit->n.max; clock.n++) {
578 for (clock.p1 = limit->p1.min;
579 clock.p1 <= limit->p1.max; clock.p1++) {
582 pineview_clock(refclk, &clock);
584 &clock))
587 clock.p != match_clock->p)
590 this_err = abs(clock.dot - target);
592 *best_clock = clock;
609 intel_clock_t clock;
618 clock.p2 = limit->p2.p2_fast;
620 clock.p2 = limit->p2.p2_slow;
623 clock.p2 = limit->p2.p2_slow;
625 clock.p2 = limit->p2.p2_fast;
631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
633 for (clock.m1 = limit->m1.max;
634 clock.m1 >= limit->m1.min; clock.m1--) {
635 for (clock.m2 = limit->m2.max;
636 clock.m2 >= limit->m2.min; clock.m2--) {
637 for (clock.p1 = limit->p1.max;
638 clock.p1 >= limit->p1.min; clock.p1--) {
641 i9xx_clock(refclk, &clock);
643 &clock))
646 this_err = abs(clock.dot - target) ;
648 *best_clock = clock;
650 max_n = clock.n;
1395 * drives the transcoder clock.
2337 /* Ironlake workaround, enable clock pointer after FDI enable*/
2735 /* Ironlake workaround, disable clock pointer after downing FDI */
2805 /* Program iCLKIP clock to the desired frequency */
2827 if (crtc->mode.clock == 20000) {
2832 /* The iCLK virtual clock root frequency is in MHz,
2833 * but the crtc->mode.clock in in KHz. To get the divisors,
2835 * convert the virtual clock precision to KHz here for higher
2842 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2857 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2858 crtc->mode.clock,
2945 * transcoder that already use the clock when we share it.
4019 * is stored as a divider into a 100MHz clock, and the
4020 * mode pixel clock is stored in units of 1KHz.
4026 fdi_dotclock = adjusted_mode->clock;
4073 /* FDI link clock is fixed at 2.7G */
4074 if (pipe_config->requested_mode.clock * 3
4103 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4104 * clock survives for now. */
4284 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4447 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4499 /* Enable DPIO clock input */
4534 struct dpll *clock = &crtc->config.dpll;
4561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4567 switch (clock->p2) {
4633 struct dpll *clock = &crtc->config.dpll;
4640 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4642 if (clock->p1 == 2)
4645 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4646 if (clock->p2 == 4)
4791 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4797 if (intel_crtc->config.requested_mode.clock >
4858 intel_clock_t clock, reduced_clock;
4879 * Returns a set of divisors for the desired target clock with the given
4880 * refclk, or FALSE. The returned values represent the clock equation:
4886 refclk, NULL, &clock);
4897 * Ensure we match the reduced clock's P to the target clock.
4898 * If the clocks don't match, we can't switch the display clock
4905 refclk, &clock,
4910 intel_crtc->config.dpll.n = clock.n;
4911 intel_crtc->config.dpll.m1 = clock.m1;
4912 intel_crtc->config.dpll.m2 = clock.m2;
4913 intel_crtc->config.dpll.p1 = clock.p1;
4914 intel_crtc->config.dpll.p2 = clock.p2;
5064 /* Ironlake: try to setup display ref clock before DPLL
5365 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5504 intel_clock_t *clock,
5526 * Returns a set of divisors for the desired target clock with the given
5527 * refclk, or FALSE. The returned values represent the clock equation:
5533 refclk, NULL, clock);
5539 * Ensure we match the reduced clock's P to the target clock.
5540 * If the clocks don't match, we can't switch the display clock
5547 refclk, clock,
5639 /* Enable autotuning of the PLL clock (if permissible) */
5708 intel_clock_t clock, reduced_clock;
5729 ok = ironlake_compute_clocks(crtc, &clock,
5737 intel_crtc->config.dpll.n = clock.n;
5738 intel_crtc->config.dpll.m1 = clock.m1;
5739 intel_crtc->config.dpll.m2 = clock.m2;
5740 intel_crtc->config.dpll.p1 = clock.p1;
5741 intel_crtc->config.dpll.p2 = clock.p2;
6941 /* Returns the clock of the currently programmed mode of the given pipe. */
6949 intel_clock_t clock;
6956 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6958 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6959 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6961 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6962 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6967 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6970 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6975 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6979 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6989 pineview_clock(96000, &clock);
6991 i9xx_clock(96000, &clock);
6996 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6998 clock.p2 = 14;
7003 i9xx_clock(66000, &clock);
7005 i9xx_clock(48000, &clock);
7008 clock.p1 = 2;
7010 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7014 clock.p2 = 4;
7016 clock.p2 = 2;
7018 i9xx_clock(48000, &clock);
7027 return clock.dot;
7047 mode->clock = intel_crtc_clock_get(dev, crtc);
7874 /* Ensure the port clock defaults are reset when retrying. */
7906 /* Set default port clock if not overwritten by the encoder. Needs to be
7909 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
9357 /* Returns the core display clock speed */