1450N/A#include "drm_edid.h"
1450N/A#include "drm_sun_i2c.h"
1450N/A#include "drm_crtc.h"
1450N/A * This table is copied from xfree86/modes/xf86EdidModes.c.
1450N/A DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
1450N/A for (i = 0; i < sizeof(edid_header); i++)
1450N/A for (i = 0; i < EDID_LENGTH; i++)
1450N/A if (print_bad_edid) {
1450N/A if (print_bad_edid) {
1450N/A j, EDID_LENGTH))
1450N/A if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) {
1450N/A if (print_bad_edid) {
1450N/A list_for_each_entry_safe(cur_mode, t, struct drm_display_mode, &connector->probed_modes, head) {
1450N/A for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1450N/A return LEVEL_GTF2;
1450N/Astatic struct drm_display_mode *
1450N/A if (aspect_ratio == 0) {
1450N/A switch (timing_level) {
1450N/A case LEVEL_GTF2:
1450N/A vrefresh_rate, 0, 0,
1450N/A unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1450N/A unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1450N/A unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
1450N/A unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1450N/A struct drm_display_mode *m;
1450N/A est3_modes[m].w,
1450N/A est3_modes[m].h,
1450N/A est3_modes[m].r,
1450N/A for (i = 0; i <= EDID_EST_TIMINGS; i++) {
1450N/A for (i = 0; i < EDID_STD_TIMINGS; i++) {
1450N/A for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
1450N/A case AUDIO_BLOCK:
1450N/A case SPEAKER_BLOCK:
1450N/A case VENDOR_BLOCK:
1450N/A list_for_each_entry(connector, struct drm_connector, &dev->mode_config.connector_list, head)