1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright (c) 2006, 2013, Intel Corporation 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 1450N/A * DEALINGS IN THE SOFTWARE. 1450N/A * Eric Anholt <eric@anholt.net> 1450N/A * register definitions for the i82807aa. 1450N/A * Documentation on this chipset can be found in datasheet #29069001 at 1450N/A * VCH Revision & GMBus Base Addr 1450N/A * This must not be set while VR01_DVO_BYPASS_ENABLE is set. 1450N/A/** Enables the DVO repeater. */ 1450N/A/** Enables the DVO clock */ 1450N/A/** Enables LVDS output instead of CMOS */ 1450N/A/** Enables 18-bit LVDS output. */ 1450N/A/** Enables 24-bit LVDS or CMOS output */ 1450N/A/** Enables 2x18-bit LVDS or CMOS output. */ 1450N/A/** Enables 2x24-bit LVDS output */ 1450N/A * VR20 LCD Horizontal Display Size 1450N/A * LCD Vertical Display Size 1450N/A/** Read only bit indicating that the panel is not in a safe poweroff state. */ 1450N/A * Panel Fitting Vertical Ratio 1450N/A * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 1450N/A * Panel Fitting Horizontal Ratio 1450N/A * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 1450N/A * Reads a register on the ivch. 1450N/A * Each of the 256 registers are 16 bits long. 1450N/A/** Writes a 16-bit register on the ivch */ 1450N/A/** Probes the given bus and slave address for an ivch */ 1450N/A /* Since the identification bits are probably zeroes, which doesn't seem 1450N/A * very unique, check that the value in the base address field matches 1450N/A * the address it's responding on. 1450N/A/** Sets the power state of the panel connected to the ivch */ 1450N/A /* Set the new power state of the panel. */ 1450N/A /* Wait for the panel to make its state transition */ 1450N/A for (i = 0; i <
100; i++) {
1450N/A /* wait some more; vch may fail to resync sometimes without this */ 1450N/A /* Set the new power state of the panel. */ 1450N/A /* Scratch register 0 - AIM Panel type */ 1450N/A /* Scratch register 1 - Status register */