Lines Matching refs:clock
105 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
132 int target_clock = mode->clock;
142 target_clock = fixed_mode->clock;
154 if (mode->clock < 10000)
307 /* The clock divider is based off the hrawclk,
312 * clock divider.
321 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
323 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
690 int lane_count, clock;
717 "max bw %02x pixel clock %iKHz\n",
718 max_lane_count, bws[max_clock], adjusted_mode->clock);
727 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
729 for (clock = 0; clock <= max_clock; clock++) {
731 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
760 intel_dp->link_bw = bws[clock];
765 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
772 adjusted_mode->clock, pipe_config->port_clock,
803 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
809 * 160MHz clock. If we're really unlucky, it's still required.
811 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
2088 DRM_DEBUG_KMS("clock recovery OK\n");
2158 /* Make sure clock is still ok */
2170 /* Try 5 times, then try clock recovery if that fails */
2969 /* Compute the divisor for the pp clock, simply match the Bspec