1450N/A/*
1450N/A * Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A/*
1450N/A * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
1450N/A * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
1450N/A * Copyright (c) 2008 Red Hat Inc.
1450N/A * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
1450N/A * Copyright (c) 2007-2008, 2013, Intel Corporation
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice shall be included in
1450N/A * all copies or substantial portions of the Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
1450N/A * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
1450N/A * IN THE SOFTWARE.
1450N/A */
1450N/A
1450N/A#ifndef _DRM_MODE_H
1450N/A#define _DRM_MODE_H
1450N/A#include "drm.h"
1450N/A#define DRM_DISPLAY_INFO_LEN 32
1450N/A#define DRM_CONNECTOR_NAME_LEN 32
1450N/A#define DRM_DISPLAY_MODE_LEN 32
1450N/A#define DRM_PROP_NAME_LEN 32
1450N/A
1450N/A#define DRM_MODE_TYPE_BUILTIN (1<<0)
1450N/A#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
1450N/A#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
1450N/A#define DRM_MODE_TYPE_PREFERRED (1<<3)
1450N/A#define DRM_MODE_TYPE_DEFAULT (1<<4)
1450N/A#define DRM_MODE_TYPE_USERDEF (1<<5)
1450N/A#define DRM_MODE_TYPE_DRIVER (1<<6)
1450N/A
1450N/A/* Video mode flags */
1450N/A/* bit compatible with the xorg definitions. */
1450N/A#define DRM_MODE_FLAG_PHSYNC (1<<0)
1450N/A#define DRM_MODE_FLAG_NHSYNC (1<<1)
1450N/A#define DRM_MODE_FLAG_PVSYNC (1<<2)
1450N/A#define DRM_MODE_FLAG_NVSYNC (1<<3)
1450N/A#define DRM_MODE_FLAG_INTERLACE (1<<4)
1450N/A#define DRM_MODE_FLAG_DBLSCAN (1<<5)
1450N/A#define DRM_MODE_FLAG_CSYNC (1<<6)
1450N/A#define DRM_MODE_FLAG_PCSYNC (1<<7)
1450N/A#define DRM_MODE_FLAG_NCSYNC (1<<8)
1450N/A#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
1450N/A#define DRM_MODE_FLAG_BCAST (1<<10)
1450N/A#define DRM_MODE_FLAG_PIXMUX (1<<11)
1450N/A#define DRM_MODE_FLAG_DBLCLK (1<<12)
1450N/A#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
1450N/A
1450N/A/* DPMS flags */
1450N/A/* bit compatible with the xorg definitions. */
1450N/A#define DRM_MODE_DPMS_ON 0
1450N/A#define DRM_MODE_DPMS_STANDBY 1
1450N/A#define DRM_MODE_DPMS_SUSPEND 2
1450N/A#define DRM_MODE_DPMS_OFF 3
1450N/A
1450N/A/* Scaling mode options */
1450N/A#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
1450N/A software can still scale) */
1450N/A#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
1450N/A#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
1450N/A#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
1450N/A
1450N/A/* Dithering mode options */
1450N/A#define DRM_MODE_DITHERING_OFF 0
1450N/A#define DRM_MODE_DITHERING_ON 1
1450N/A#define DRM_MODE_DITHERING_AUTO 2
1450N/A
1450N/A/* Dirty info options */
1450N/A#define DRM_MODE_DIRTY_OFF 0
1450N/A#define DRM_MODE_DIRTY_ON 1
1450N/A#define DRM_MODE_DIRTY_ANNOTATE 2
1450N/A
1450N/Astruct drm_mode_modeinfo {
1450N/A __u32 clock;
1450N/A __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
1450N/A __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
1450N/A
1450N/A __u32 vrefresh;
1450N/A
1450N/A __u32 flags;
1450N/A __u32 type;
1450N/A char name[DRM_DISPLAY_MODE_LEN];
1450N/A};
1450N/A
1450N/Astruct drm_mode_card_res {
1450N/A __u64 fb_id_ptr;
1450N/A __u64 crtc_id_ptr;
1450N/A __u64 connector_id_ptr;
1450N/A __u64 encoder_id_ptr;
1450N/A __u32 count_fbs;
1450N/A __u32 count_crtcs;
1450N/A __u32 count_connectors;
1450N/A __u32 count_encoders;
1450N/A __u32 min_width, max_width;
1450N/A __u32 min_height, max_height;
1450N/A};
1450N/A
1450N/Astruct drm_mode_crtc {
1450N/A __u64 set_connectors_ptr;
1450N/A __u32 count_connectors;
1450N/A
1450N/A __u32 crtc_id; /**< Id */
1450N/A __u32 fb_id; /**< Id of framebuffer */
1450N/A
1450N/A __u32 x, y; /**< Position on the frameuffer */
1450N/A
1450N/A __u32 gamma_size;
1450N/A __u32 mode_valid;
1450N/A struct drm_mode_modeinfo mode;
1450N/A};
1450N/A
1450N/A#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
1450N/A#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
1450N/A
1450N/A/* Planes blend with or override other bits on the CRTC */
1450N/Astruct drm_mode_set_plane {
1450N/A __u32 plane_id;
1450N/A __u32 crtc_id;
1450N/A __u32 fb_id; /* fb object contains surface format type */
1450N/A __u32 flags; /* see above flags */
1450N/A
1450N/A /* Signed dest location allows it to be partially off screen */
1450N/A __s32 crtc_x, crtc_y;
1450N/A __u32 crtc_w, crtc_h;
1450N/A
1450N/A /* Source values are 16.16 fixed point */
1450N/A __u32 src_x, src_y;
1450N/A __u32 src_h, src_w;
1450N/A};
1450N/A
1450N/Astruct drm_mode_get_plane {
1450N/A __u32 plane_id;
1450N/A
1450N/A __u32 crtc_id;
1450N/A __u32 fb_id;
1450N/A
1450N/A __u32 possible_crtcs;
1450N/A __u32 gamma_size;
1450N/A
1450N/A __u32 count_format_types;
1450N/A __u64 format_type_ptr;
1450N/A};
1450N/A
1450N/Astruct drm_mode_get_plane_res {
1450N/A __u64 plane_id_ptr;
1450N/A __u32 count_planes;
1450N/A};
1450N/A
1450N/A#define DRM_MODE_ENCODER_NONE 0
1450N/A#define DRM_MODE_ENCODER_DAC 1
1450N/A#define DRM_MODE_ENCODER_TMDS 2
1450N/A#define DRM_MODE_ENCODER_LVDS 3
1450N/A#define DRM_MODE_ENCODER_TVDAC 4
1450N/A#define DRM_MODE_ENCODER_VIRTUAL 5
1450N/A
1450N/Astruct drm_mode_get_encoder {
1450N/A __u32 encoder_id;
1450N/A __u32 encoder_type;
1450N/A
1450N/A __u32 crtc_id; /**< Id of crtc */
1450N/A
1450N/A __u32 possible_crtcs;
1450N/A __u32 possible_clones;
1450N/A};
1450N/A
1450N/A/* This is for connectors with multiple signal types. */
1450N/A/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
1450N/A#define DRM_MODE_SUBCONNECTOR_Automatic 0
1450N/A#define DRM_MODE_SUBCONNECTOR_Unknown 0
1450N/A#define DRM_MODE_SUBCONNECTOR_DVID 3
1450N/A#define DRM_MODE_SUBCONNECTOR_DVIA 4
1450N/A#define DRM_MODE_SUBCONNECTOR_Composite 5
1450N/A#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
1450N/A#define DRM_MODE_SUBCONNECTOR_Component 8
1450N/A#define DRM_MODE_SUBCONNECTOR_SCART 9
1450N/A
1450N/A#define DRM_MODE_CONNECTOR_Unknown 0
1450N/A#define DRM_MODE_CONNECTOR_VGA 1
1450N/A#define DRM_MODE_CONNECTOR_DVII 2
1450N/A#define DRM_MODE_CONNECTOR_DVID 3
1450N/A#define DRM_MODE_CONNECTOR_DVIA 4
1450N/A#define DRM_MODE_CONNECTOR_Composite 5
1450N/A#define DRM_MODE_CONNECTOR_SVIDEO 6
1450N/A#define DRM_MODE_CONNECTOR_LVDS 7
1450N/A#define DRM_MODE_CONNECTOR_Component 8
1450N/A#define DRM_MODE_CONNECTOR_9PinDIN 9
1450N/A#define DRM_MODE_CONNECTOR_DisplayPort 10
1450N/A#define DRM_MODE_CONNECTOR_HDMIA 11
1450N/A#define DRM_MODE_CONNECTOR_HDMIB 12
1450N/A#define DRM_MODE_CONNECTOR_TV 13
1450N/A#define DRM_MODE_CONNECTOR_eDP 14
1450N/A#define DRM_MODE_CONNECTOR_VIRTUAL 15
1450N/A
1450N/Astruct drm_mode_get_connector {
1450N/A
1450N/A __u64 encoders_ptr;
1450N/A __u64 modes_ptr;
1450N/A __u64 props_ptr;
1450N/A __u64 prop_values_ptr;
1450N/A
1450N/A __u32 count_modes;
1450N/A __u32 count_props;
1450N/A __u32 count_encoders;
1450N/A
1450N/A __u32 encoder_id; /**< Current Encoder */
1450N/A __u32 connector_id; /**< Id */
1450N/A __u32 connector_type;
1450N/A __u32 connector_type_id;
1450N/A
1450N/A __u32 connection;
1450N/A __u32 mm_width, mm_height; /**< HxW in millimeters */
1450N/A __u32 subpixel;
1450N/A};
1450N/A
1450N/A#define DRM_MODE_PROP_PENDING (1<<0)
1450N/A#define DRM_MODE_PROP_RANGE (1<<1)
1450N/A#define DRM_MODE_PROP_IMMUTABLE (1<<2)
1450N/A#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
1450N/A#define DRM_MODE_PROP_BLOB (1<<4)
1450N/A#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
1450N/A
1450N/Astruct drm_mode_property_enum {
1450N/A __u64 value;
1450N/A char name[DRM_PROP_NAME_LEN];
1450N/A};
1450N/A
1450N/Astruct drm_mode_get_property {
1450N/A __u64 values_ptr; /* values and blob lengths */
1450N/A __u64 enum_blob_ptr; /* enum and blob id ptrs */
1450N/A
1450N/A __u32 prop_id;
1450N/A __u32 flags;
1450N/A char name[DRM_PROP_NAME_LEN];
1450N/A
1450N/A __u32 count_values;
1450N/A __u32 count_enum_blobs;
1450N/A};
1450N/A
1450N/Astruct drm_mode_connector_set_property {
1450N/A __u64 value;
1450N/A __u32 prop_id;
1450N/A __u32 connector_id;
1450N/A};
1450N/A
1450N/Astruct drm_mode_obj_get_properties {
1450N/A __u64 props_ptr;
1450N/A __u64 prop_values_ptr;
1450N/A __u32 count_props;
1450N/A __u32 obj_id;
1450N/A __u32 obj_type;
1450N/A};
1450N/A
1450N/Astruct drm_mode_obj_set_property {
1450N/A __u64 value;
1450N/A __u32 prop_id;
1450N/A __u32 obj_id;
1450N/A __u32 obj_type;
1450N/A};
1450N/A
1450N/Astruct drm_mode_get_blob {
1450N/A __u32 blob_id;
1450N/A __u32 length;
1450N/A __u64 data;
1450N/A};
1450N/A
1450N/Astruct drm_mode_fb_cmd {
1450N/A __u32 fb_id;
1450N/A __u32 width, height;
1450N/A __u32 pitch;
1450N/A __u32 bpp;
1450N/A __u32 depth;
1450N/A /* driver specific handle */
1450N/A __u32 handle;
1450N/A};
1450N/A
1450N/A#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
1450N/A
1450N/Astruct drm_mode_fb_cmd2 {
1450N/A __u32 fb_id;
1450N/A __u32 width, height;
1450N/A __u32 pixel_format; /* fourcc code from drm_fourcc.h */
1450N/A __u32 flags; /* see above flags */
1450N/A
1450N/A /*
1450N/A * In case of planar formats, this ioctl allows up to 4
1450N/A * buffer objects with offets and pitches per plane.
1450N/A * The pitch and offset order is dictated by the fourcc,
1450N/A * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
1450N/A *
1450N/A * YUV 4:2:0 image with a plane of 8 bit Y samples
1450N/A * followed by an interleaved U/V plane containing
1450N/A * 8 bit 2x2 subsampled colour difference samples.
1450N/A *
1450N/A * So it would consist of Y as offset[0] and UV as
1450N/A * offeset[1]. Note that offset[0] will generally
1450N/A * be 0.
1450N/A */
1450N/A __u32 handles[4];
1450N/A __u32 pitches[4]; /* pitch for each plane */
1450N/A __u32 offsets[4]; /* offset of each plane */
1450N/A};
1450N/A
1450N/A#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
1450N/A#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
1450N/A#define DRM_MODE_FB_DIRTY_FLAGS 0x03
1450N/A
1450N/A#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
1450N/A
1450N/A/*
1450N/A * Mark a region of a framebuffer as dirty.
1450N/A *
1450N/A * Some hardware does not automatically update display contents
1450N/A * as a hardware or software draw to a framebuffer. This ioctl
1450N/A * allows userspace to tell the kernel and the hardware what
1450N/A * regions of the framebuffer have changed.
1450N/A *
1450N/A * The kernel or hardware is free to update more then just the
1450N/A * region specified by the clip rects. The kernel or hardware
1450N/A * may also delay and/or coalesce several calls to dirty into a
1450N/A * single update.
1450N/A *
1450N/A * Userspace may annotate the updates, the annotates are a
1450N/A * promise made by the caller that the change is either a copy
1450N/A * of pixels or a fill of a single color in the region specified.
1450N/A *
1450N/A * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
1450N/A * the number of updated regions are half of num_clips given,
1450N/A * where the clip rects are paired in src and dst. The width and
1450N/A * height of each one of the pairs must match.
1450N/A *
1450N/A * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
1450N/A * promises that the region specified of the clip rects is filled
1450N/A * completely with a single color as given in the color argument.
1450N/A */
1450N/A
1450N/Astruct drm_mode_fb_dirty_cmd {
1450N/A __u32 fb_id;
1450N/A __u32 flags;
1450N/A __u32 color;
1450N/A __u32 num_clips;
1450N/A __u64 clips_ptr;
1450N/A};
1450N/A
1450N/Astruct drm_mode_mode_cmd {
1450N/A __u32 connector_id;
1450N/A struct drm_mode_modeinfo mode;
1450N/A};
1450N/A
1450N/A#define DRM_MODE_CURSOR_BO 0x01
1450N/A#define DRM_MODE_CURSOR_MOVE 0x02
1450N/A#define DRM_MODE_CURSOR_FLAGS 0x03
1450N/A
1450N/A/*
1450N/A * depending on the value in flags diffrent members are used.
1450N/A *
1450N/A * CURSOR_BO uses
1450N/A * crtc
1450N/A * width
1450N/A * height
1450N/A * handle - if 0 turns the cursor of
1450N/A *
1450N/A * CURSOR_MOVE uses
1450N/A * crtc
1450N/A * x
1450N/A * y
1450N/A */
1450N/Astruct drm_mode_cursor {
1450N/A __u32 flags;
1450N/A __u32 crtc_id;
1450N/A __s32 x;
1450N/A __s32 y;
1450N/A __u32 width;
1450N/A __u32 height;
1450N/A /* driver specific handle */
1450N/A __u32 handle;
1450N/A};
1450N/A
1450N/Astruct drm_mode_cursor2 {
1450N/A __u32 flags;
1450N/A __u32 crtc_id;
1450N/A __s32 x;
1450N/A __s32 y;
1450N/A __u32 width;
1450N/A __u32 height;
1450N/A /* driver specific handle */
1450N/A __u32 handle;
1450N/A __s32 hot_x;
1450N/A __s32 hot_y;
1450N/A};
1450N/A
1450N/Astruct drm_mode_crtc_lut {
1450N/A __u32 crtc_id;
1450N/A __u32 gamma_size;
1450N/A
1450N/A /* pointers to arrays */
1450N/A __u64 red;
1450N/A __u64 green;
1450N/A __u64 blue;
1450N/A};
1450N/A
1450N/A#define DRM_MODE_PAGE_FLIP_EVENT 0x01
1450N/A#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
1450N/A
1450N/A/*
1450N/A * Request a page flip on the specified crtc.
1450N/A *
1450N/A * This ioctl will ask KMS to schedule a page flip for the specified
1450N/A * crtc. Once any pending rendering targeting the specified fb (as of
1450N/A * ioctl time) has completed, the crtc will be reprogrammed to display
1450N/A * that fb after the next vertical refresh. The ioctl returns
1450N/A * immediately, but subsequent rendering to the current fb will block
1450N/A * in the execbuffer ioctl until the page flip happens. If a page
1450N/A * flip is already pending as the ioctl is called, EBUSY will be
1450N/A * returned.
1450N/A *
1450N/A * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
1450N/A * request that drm sends back a vblank event (see drm.h: struct
1450N/A * drm_event_vblank) when the page flip is done. The user_data field
1450N/A * passed in with this ioctl will be returned as the user_data field
1450N/A * in the vblank event struct.
1450N/A *
1450N/A * The reserved field must be zero until we figure out something
1450N/A * clever to use it for.
1450N/A */
1450N/A
1450N/Astruct drm_mode_crtc_page_flip {
1450N/A __u32 crtc_id;
1450N/A __u32 fb_id;
1450N/A __u32 flags;
1450N/A __u32 reserved;
1450N/A __u64 user_data;
1450N/A};
1450N/A
1450N/A/* create a dumb scanout buffer */
1450N/Astruct drm_mode_create_dumb {
1450N/A uint32_t height;
1450N/A uint32_t width;
1450N/A uint32_t bpp;
1450N/A uint32_t flags;
1450N/A /* handle, pitch, size will be returned */
1450N/A uint32_t handle;
1450N/A uint32_t pitch;
1450N/A uint64_t size;
1450N/A};
1450N/A
1450N/A/* set up for mmap of a dumb scanout buffer */
1450N/Astruct drm_mode_map_dumb {
1450N/A /** Handle for the object being mapped. */
1450N/A __u32 handle;
1450N/A __u32 pad;
1450N/A /**
1450N/A * Fake offset to use for subsequent mmap call
1450N/A *
1450N/A * This is a fixed-size type for 32/64 compatibility.
1450N/A */
1450N/A __u64 offset;
1450N/A};
1450N/A
1450N/Astruct drm_mode_destroy_dumb {
1450N/A uint32_t handle;
1450N/A};
1450N/A
1450N/A#endif /* _DRM_MODE_H */