1450N/A/*
1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A/*
1450N/A * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
1450N/A */
1450N/A/**************************************************************************
1450N/A
1450N/ACopyright © 2006 Dave Airlie
1450N/A
1450N/AAll Rights Reserved.
1450N/A
1450N/APermission is hereby granted, free of charge, to any person obtaining a
1450N/Acopy of this software and associated documentation files (the
1450N/A"Software"), to deal in the Software without restriction, including
1450N/Awithout limitation the rights to use, copy, modify, merge, publish,
1450N/Adistribute, sub license, and/or sell copies of the Software, and to
1450N/Apermit persons to whom the Software is furnished to do so, subject to
1450N/Athe following conditions:
1450N/A
1450N/AThe above copyright notice and this permission notice (including the
1450N/Anext paragraph) shall be included in all copies or substantial portions
1450N/Aof the Software.
1450N/A
1450N/ATHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
1450N/AOR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
1450N/AMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
1450N/AIN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
1450N/AANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
1450N/ATORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
1450N/ASOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1450N/A
1450N/A**************************************************************************/
1450N/A
1450N/A#include "dvo.h"
1450N/A
1450N/A#define CH7xxx_REG_VID 0x4a
1450N/A#define CH7xxx_REG_DID 0x4b
1450N/A
1450N/A#define CH7011_VID 0x83 /* 7010 as well */
1450N/A#define CH7010B_VID 0x05
1450N/A#define CH7009A_VID 0x84
1450N/A#define CH7009B_VID 0x85
1450N/A#define CH7301_VID 0x95
1450N/A
1450N/A#define CH7xxx_VID 0x84
1450N/A#define CH7xxx_DID 0x17
1450N/A#define CH7010_DID 0x16
1450N/A
1450N/A#define CH7xxx_NUM_REGS 0x4c
1450N/A
1450N/A#define CH7xxx_CM 0x1c
1450N/A#define CH7xxx_CM_XCM (1<<0)
1450N/A#define CH7xxx_CM_MCP (1<<2)
1450N/A#define CH7xxx_INPUT_CLOCK 0x1d
1450N/A#define CH7xxx_GPIO 0x1e
1450N/A#define CH7xxx_GPIO_HPIR (1<<3)
1450N/A#define CH7xxx_IDF 0x1f
1450N/A
1450N/A#define CH7xxx_IDF_HSP (1<<3)
1450N/A#define CH7xxx_IDF_VSP (1<<4)
1450N/A
1450N/A#define CH7xxx_CONNECTION_DETECT 0x20
1450N/A#define CH7xxx_CDET_DVI (1<<5)
1450N/A
1450N/A#define CH7301_DAC_CNTL 0x21
1450N/A#define CH7301_HOTPLUG 0x23
1450N/A#define CH7xxx_TCTL 0x31
1450N/A#define CH7xxx_TVCO 0x32
1450N/A#define CH7xxx_TPCP 0x33
1450N/A#define CH7xxx_TPD 0x34
1450N/A#define CH7xxx_TPVT 0x35
1450N/A#define CH7xxx_TLPF 0x36
1450N/A#define CH7xxx_TCT 0x37
1450N/A#define CH7301_TEST_PATTERN 0x48
1450N/A
1450N/A#define CH7xxx_PM 0x49
1450N/A#define CH7xxx_PM_FPD (1<<0)
1450N/A#define CH7301_PM_DACPD0 (1<<1)
1450N/A#define CH7301_PM_DACPD1 (1<<2)
1450N/A#define CH7301_PM_DACPD2 (1<<3)
1450N/A#define CH7xxx_PM_DVIL (1<<6)
1450N/A#define CH7xxx_PM_DVIP (1<<7)
1450N/A
1450N/A#define CH7301_SYNC_POLARITY 0x56
1450N/A#define CH7301_SYNC_RGB_YUV (1<<0)
1450N/A#define CH7301_SYNC_POL_DVI (1<<5)
1450N/A
1450N/A/** @file
1450N/A * driver for the Chrontel 7xxx DVI chip over DVO.
1450N/A */
1450N/A
1450N/Astatic struct ch7xxx_id_struct {
1450N/A uint8_t vid;
1450N/A char *name;
1450N/A} ch7xxx_ids[] = {
1450N/A { CH7011_VID, "CH7011" },
1450N/A { CH7010B_VID, "CH7010B" },
1450N/A { CH7009A_VID, "CH7009A" },
1450N/A { CH7009B_VID, "CH7009B" },
1450N/A { CH7301_VID, "CH7301" },
1450N/A};
1450N/A
1450N/Astatic struct ch7xxx_did_struct {
1450N/A uint8_t did;
1450N/A char *name;
1450N/A} ch7xxx_dids[] = {
1450N/A { CH7xxx_DID, "CH7XXX" },
1450N/A { CH7010_DID, "CH7010B" },
1450N/A};
1450N/A
1450N/Astruct ch7xxx_priv {
1450N/A bool quiet;
1450N/A};
1450N/A
1450N/Astatic char *ch7xxx_get_id(uint8_t vid)
1450N/A{
1450N/A int i;
1450N/A
1450N/A for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) {
1450N/A if (ch7xxx_ids[i].vid == vid)
1450N/A return ch7xxx_ids[i].name;
1450N/A }
1450N/A
1450N/A return NULL;
1450N/A}
1450N/A
1450N/Astatic char *ch7xxx_get_did(uint8_t did)
1450N/A{
1450N/A int i;
1450N/A
1450N/A for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) {
1450N/A if (ch7xxx_dids[i].did == did)
1450N/A return ch7xxx_dids[i].name;
1450N/A }
1450N/A
1450N/A return NULL;
1450N/A}
1450N/A
1450N/A/** Reads an 8 bit register */
1450N/Astatic bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
1450N/A{
1450N/A struct ch7xxx_priv *ch7xxx= dvo->dev_priv;
1450N/A struct i2c_adapter *adapter = dvo->i2c_bus;
1450N/A u8 out_buf[2];
1450N/A u8 in_buf[2];
1450N/A
1450N/A struct i2c_msg msgs[] = {
1450N/A {
1450N/A .addr = dvo->slave_addr,
1450N/A .flags = 0,
1450N/A .len = 1,
1450N/A .buf = out_buf,
1450N/A },
1450N/A {
1450N/A .addr = dvo->slave_addr,
1450N/A .flags = I2C_M_RD,
1450N/A .len = 1,
1450N/A .buf = in_buf,
1450N/A }
1450N/A };
1450N/A
1450N/A out_buf[0] = (u8) addr;
1450N/A out_buf[1] = 0;
1450N/A
1450N/A if (i2c_transfer(adapter, msgs, 2) == 2) {
1450N/A *ch = in_buf[0];
1450N/A return true;
1450N/A };
1450N/A
1450N/A if (!ch7xxx->quiet) {
1450N/A DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
1450N/A addr, adapter->name, dvo->slave_addr);
1450N/A }
1450N/A return false;
1450N/A}
1450N/A
1450N/A/** Writes an 8 bit register */
1450N/Astatic bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
1450N/A{
1450N/A struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
1450N/A struct i2c_adapter *adapter = dvo->i2c_bus;
1450N/A uint8_t out_buf[2];
1450N/A struct i2c_msg msg = {
1450N/A .addr = dvo->slave_addr,
1450N/A .flags = 0,
1450N/A .len = 2,
1450N/A .buf = out_buf,
1450N/A };
1450N/A
1450N/A out_buf[0] = (uint8_t) addr;
1450N/A out_buf[1] = ch;
1450N/A
1450N/A if (i2c_transfer(adapter, &msg, 1) == 1)
1450N/A return true;
1450N/A
1450N/A if (!ch7xxx->quiet) {
1450N/A DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
1450N/A addr, adapter->name, dvo->slave_addr);
1450N/A }
1450N/A
1450N/A return false;
1450N/A}
1450N/A
1450N/Astatic bool ch7xxx_init(struct intel_dvo_device *dvo,
1450N/A struct i2c_adapter *adapter)
1450N/A{
1450N/A /* this will detect the CH7xxx chip on the specified i2c bus */
1450N/A struct ch7xxx_priv *ch7xxx;
1450N/A uint8_t vendor, device;
1450N/A char *name, *devid;
1450N/A
1450N/A ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL);
1450N/A if (ch7xxx == NULL)
1450N/A return false;
1450N/A
1450N/A dvo->i2c_bus = adapter;
1450N/A dvo->dev_priv = ch7xxx;
1450N/A ch7xxx->quiet = true;
1450N/A
1450N/A if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor))
1450N/A goto out;
1450N/A
1450N/A name = ch7xxx_get_id(vendor);
1450N/A if (!name) {
1450N/A DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
1450N/A "slave %d.\n",
1450N/A vendor, adapter->name, dvo->slave_addr);
1450N/A goto out;
1450N/A }
1450N/A
1450N/A
1450N/A if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device))
1450N/A goto out;
1450N/A
1450N/A devid = ch7xxx_get_did(device);
1450N/A if (!devid) {
1450N/A DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
1450N/A "slave %d.\n",
1450N/A vendor, adapter->name, dvo->slave_addr);
1450N/A goto out;
1450N/A }
1450N/A
1450N/A ch7xxx->quiet = false;
1450N/A DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
1450N/A name, vendor, device);
1450N/A return true;
1450N/Aout:
1450N/A kfree(ch7xxx, sizeof (struct ch7xxx_priv));
1450N/A return false;
1450N/A}
1450N/A
1450N/Astatic enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo)
1450N/A{
1450N/A uint8_t cdet, orig_pm, pm;
1450N/A
1450N/A (void) ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm);
1450N/A
1450N/A pm = orig_pm;
1450N/A pm &= ~CH7xxx_PM_FPD;
1450N/A pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP;
1450N/A
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_PM, pm);
1450N/A
1450N/A (void) ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet);
1450N/A
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm);
1450N/A
1450N/A if (cdet & CH7xxx_CDET_DVI)
1450N/A return connector_status_connected;
1450N/A return connector_status_disconnected;
1450N/A}
1450N/A
1450N/A/* LINTED */
1450N/Astatic int ch7xxx_mode_valid(struct intel_dvo_device *dvo,
1450N/A struct drm_display_mode *mode)
1450N/A{
1450N/A if (mode->clock > 165000)
1450N/A return MODE_CLOCK_HIGH;
1450N/A
1450N/A return MODE_OK;
1450N/A}
1450N/A
1450N/Astatic void ch7xxx_mode_set(struct intel_dvo_device *dvo,
1450N/A struct drm_display_mode *mode,
1450N/A /* LINTED */
1450N/A struct drm_display_mode *adjusted_mode)
1450N/A{
1450N/A uint8_t tvco, tpcp, tpd, tlpf, idf;
1450N/A
1450N/A if (mode->clock <= 65000) {
1450N/A tvco = 0x23;
1450N/A tpcp = 0x08;
1450N/A tpd = 0x16;
1450N/A tlpf = 0x60;
1450N/A } else {
1450N/A tvco = 0x2d;
1450N/A tpcp = 0x06;
1450N/A tpd = 0x26;
1450N/A tlpf = 0xa0;
1450N/A }
1450N/A
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00);
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco);
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp);
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_TPD, tpd);
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30);
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf);
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00);
1450N/A
1450N/A (void) ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
1450N/A
1450N/A idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
1450N/A if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1450N/A idf |= CH7xxx_IDF_HSP;
1450N/A
1450N/A if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1450N/A idf |= CH7xxx_IDF_HSP;
1450N/A
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
1450N/A}
1450N/A
1450N/A/* set the CH7xxx power state */
1450N/Astatic void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable)
1450N/A{
1450N/A if (enable)
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP);
1450N/A else
1450N/A (void) ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD);
1450N/A}
1450N/A
1450N/Astatic bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo)
1450N/A{
1450N/A u8 val;
1450N/A
1450N/A ch7xxx_readb(dvo, CH7xxx_PM, &val);
1450N/A
1450N/A if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP))
1450N/A return true;
1450N/A else
1450N/A return false;
1450N/A}
1450N/A
1450N/Astatic void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
1450N/A{
1450N/A int i;
1450N/A
1450N/A for (i = 0; i < CH7xxx_NUM_REGS; i++) {
1450N/A uint8_t val;
1450N/A if ((i % 8) == 0 )
1450N/A DRM_LOG_KMS("\n %02X: ", i);
1450N/A (void) ch7xxx_readb(dvo, i, &val);
1450N/A DRM_LOG_KMS("%02X ", val);
1450N/A}
1450N/A}
1450N/A
1450N/Astatic void ch7xxx_destroy(struct intel_dvo_device *dvo)
1450N/A{
1450N/A struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
1450N/A
1450N/A if (ch7xxx) {
1450N/A kfree(ch7xxx, sizeof (struct ch7xxx_priv));
1450N/A dvo->dev_priv = NULL;
1450N/A }
1450N/A}
1450N/A
1450N/Astruct intel_dvo_dev_ops ch7xxx_ops = {
1450N/A .init = ch7xxx_init,
1450N/A .detect = ch7xxx_detect,
1450N/A .mode_valid = ch7xxx_mode_valid,
1450N/A .mode_set = ch7xxx_mode_set,
1450N/A .dpms = ch7xxx_dpms,
1450N/A .get_hw_state = ch7xxx_get_hw_state,
1450N/A .dump_regs = ch7xxx_dump_regs,
1450N/A .destroy = ch7xxx_destroy,
1450N/A};