1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright (c) 2006-2007, 2013, Intel Corporation 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 1450N/A * DEALINGS IN THE SOFTWARE. 1450N/A * Eric Anholt <eric@anholt.net> 1450N/A * @file SDVO command definitions and structures. 1450N/A/* Note: SDVO detailed timing flags match EDID misc flags. */ 1450N/A/** This matches the EDID DTD structure, more or less */ 1450N/A /** lower 4 bits each vsync offset, vsync width */ 1450N/A * 2 high bits of hsync offset, 2 high bits of hsync width, 1450N/A * bits 4-5 of vsync offset, and 2 high bits of vsync width. 1450N/A /** bits 6-7 of vsync offset at bits 6-7 */ 1450N/A/* I2C registers for SDVO */ 1450N/A/** Returns a struct intel_sdvo_caps */ 1450N/A * Reports which inputs are trained (managed to sync). 1450N/A * Devices must have trained within 2 vsyncs of a mode change. 1450N/A/** Returns a struct intel_sdvo_output_flags of active outputs. */ 1450N/A * Sets the current set of active outputs. 1450N/A * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP 1450N/A * Returns the current mapping of SDVO inputs to outputs on the device. 1450N/A * Returns two struct intel_sdvo_output_flags structures. 1450N/A * Sets the current mapping of SDVO inputs to outputs on the device. 1450N/A * Takes two struct i380_sdvo_output_flags structures. 1450N/A * Returns a struct intel_sdvo_output_flags of attached displays. 1450N/A * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. 1450N/A * Takes a struct intel_sdvo_output_flags. 1450N/A * Returns a struct intel_sdvo_output_flags of displays with hot plug 1450N/A * Selects which input is affected by future input commands. 1450N/A * Commands affected include SET_INPUT_TIMINGS_PART[12], 1450N/A * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], 1450N/A * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. 1450N/A * Takes a struct intel_sdvo_output_flags of which outputs are targetted by 1450N/A * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 1450N/A * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. 1450N/A * Generates a DTD based on the given width, height, and flags. 1450N/A * This will be supported by any device supporting scaling or interlaced 1450N/A/** Returns a struct intel_sdvo_pixel_clock_range */ 1450N/A/** Returns a struct intel_sdvo_pixel_clock_range */ 1450N/A/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 1450N/A/** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 1450N/A/** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 1450N/A/** 5 bytes of bit flags for TV formats shared by all TV format functions */ 1450N/A/** Returns the resolutiosn that can be used with the given TV format */ 1450N/A/* Get supported resolution with squire pixel aspect ratio that can be 1450N/A scaled for the requested HDTV format */ 1450N/A/* Get supported power state returns info for encoder and monitor, rely on 1450N/A last SetTargetInput and SetTargetOutput calls */ 1450N/A/* Get power state returns info for encoder and monitor, rely on last 1450N/A SetTargetInput and SetTargetOutput calls */ 1450N/A * The panel power sequencing parameters are in units of milliseconds. 1450N/A * The high fields are bits 8:9 of the 10-bit values. 1450N/A/* Set display power state */ 1450N/A/* Picture enhancement limits below are dependent on the current TV format, 1450N/A * and thus need to be queried and set after it. 1450N/A#
endif /* _INTEL_SDVO_REGS_H */