Searched refs:u32 (Results 1 - 25 of 57) sorted by relevance

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/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_ringbuffer.h77 u32 seqno;
78 u32 acthd;
92 u32 mmio_base;
97 u32 head;
98 u32 tail;
112 u32 last_retired_head;
115 u32 gt; /* protected by dev_priv->irq_lock */
116 u32 pm; /* protected by dev_priv->rps.lock (sucks) */
118 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
119 u32 trace_irq_seqn
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H A Di915_drv.h236 u32 *lid_state;
272 u32 eir;
273 u32 pgtbl_er;
274 u32 ier;
275 u32 ccid;
276 u32 derrmr;
277 u32 forcewake;
279 u32 pipestat[I915_MAX_PIPES];
280 u32 tail[I915_NUM_RINGS];
281 u32 hea
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H A Dintel_sideband.c29 static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
30 u32 port, u32 opcode, u32 addr, u32 *val)
32 u32 cmd, be = 0xf, bar = 0;
66 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
68 u32 val = 0;
80 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
90 u32 vlv_nc_rea
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H A Dintel_overlay.c125 u32 OBUF_0Y;
126 u32 OBUF_1Y;
127 u32 OBUF_0U;
128 u32 OBUF_0V;
129 u32 OBUF_1U;
130 u32 OBUF_1V;
131 u32 OSTRIDE;
132 u32 YRGB_VPH;
133 u32 UV_VPH;
134 u32 HORZ_P
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H A Dintel_panel.c86 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
87 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
130 u32 border, sync_pos, blank_width, sync_width;
152 u32 border, sync_pos, blank_width, sync_width;
169 static inline u32 panel_fitter_scaling(u32 source, u32 target)
178 u32 ratio = source * FACTOR / target;
187 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
214 u32 scaled_widt
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H A Dintel_i2c.c74 u32 val;
88 static u32 get_reserved(struct intel_gmbus *bus)
92 u32 reserved = 0;
121 u32 reserved = get_reserved(bus);
131 u32 reserved = get_reserved(bus);
141 u32 reserved = get_reserved(bus);
142 u32 clock_bits;
158 u32 reserved = get_reserved(bus);
159 u32 data_bits;
201 intel_gpio_setup(struct intel_gmbus *bus, u32 pi
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H A Dintel_ringbuffer.c46 volatile u32 *cpu_page;
47 u32 gtt_offset;
60 u32 invalidate_domains,
61 u32 flush_domains)
63 u32 cmd;
86 u32 invalidate_domains,
87 u32 flush_domains)
90 u32 cmd;
183 u32 scratch_addr = pc->gtt_offset + 128;
217 u32 invalidate_domain
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H A Dintel_bios.h45 u32 bdb_offset; /**< from beginning of VBT */
46 u32 aim_offset[4]; /**< from beginning of VBT */
338 u32 lvds_reg;
339 u32 lvds_reg_val;
340 u32 pp_on_reg;
341 u32 pp_on_reg_val;
342 u32 pp_off_reg;
343 u32 pp_off_reg_val;
344 u32 pp_cycle_reg;
345 u32 pp_cycle_reg_va
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H A Ddvo.h44 u32 dvo_reg;
46 u32 gpio;
H A Dintel_hdmi.c87 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
100 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
113 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
126 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
147 u32 val = I915_READ(VIDEO_DIP_CTL);
188 u32 val = I915_READ(reg);
228 u32 val = I915_READ(reg);
271 u32 val = I915_READ(reg);
309 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
310 u32 data_re
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H A Dintel_tv.c58 u32 save_TV_H_CTL_1;
59 u32 save_TV_H_CTL_2;
60 u32 save_TV_H_CTL_3;
61 u32 save_TV_V_CTL_1;
62 u32 save_TV_V_CTL_2;
63 u32 save_TV_V_CTL_3;
64 u32 save_TV_V_CTL_4;
65 u32 save_TV_V_CTL_5;
66 u32 save_TV_V_CTL_6;
67 u32 save_TV_V_CTL_
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H A Di915_irq.c40 static const u32 hpd_ibx[] = {
48 static const u32 hpd_cpt[] = {
56 static const u32 hpd_mask_i915[] = {
65 static const u32 hpd_status_gen4[] = {
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
97 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
318 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
320 u32 reg = PIPESTAT(pipe);
321 u32 pipesta
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H A Di915_gem_stolen.c52 u32 base;
216 u32 offset, u32 size)
306 i915_gem_object_create_stolen(struct drm_device *dev, u32 size)
339 u32 stolen_offset,
340 u32 gtt_offset,
341 u32 size)
H A Dintel_crt.c55 u32 adpa_reg;
75 u32 tmp;
95 u32 tmp, flags = 0;
119 u32 temp;
256 u32 adpa;
290 u32 adpa;
296 u32 save_adpa;
335 u32 adpa;
337 u32 save_adpa;
379 u32 hotplug_e
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H A Dintel_dvo.c131 u32 tmp;
148 u32 tmp, flags = 0;
167 u32 dvo_reg = intel_dvo->dev.dvo_reg;
168 u32 temp = I915_READ(dvo_reg);
179 u32 dvo_reg = intel_dvo->dev.dvo_reg;
180 u32 temp = I915_READ(dvo_reg);
288 u32 dvo_val;
289 u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
H A Dintel_drv.h258 u32 control;
259 u32 pgm_ratios;
260 u32 lvds_border_bits;
265 u32 pos;
266 u32 size;
324 u32 lut_r[1024], lut_g[1024], lut_b[1024];
441 u32 hdmi_reg;
487 u32 saved_port_bits;
608 u32 level, u32 ma
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/solaris-x11-s11/open-src/kernel/sys/drm/
H A Ddrm_fb_helper.h45 u32 fb_width;
46 u32 fb_height;
47 u32 surface_width;
48 u32 surface_height;
49 u32 surface_bpp;
50 u32 surface_depth;
93 u32 pseudo_palette[17];
H A Ddrm_sun_pci.h75 extern void pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
78 extern void pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
H A Ddrm_sun_i2c.h42 u32 (*functionality) (struct i2c_adapter *);
/solaris-x11-s11/open-src/kernel/drm/src/
H A Dati_pcigart.c66 u32 *pci_gart = NULL, page_base;
87 pci_gart = (u32 *)entry->dmah_gart->vaddr;
105 page_base = (u32) entry->busaddr[pagenum];
/solaris-x11-s11/open-src/kernel/efb/src/
H A Dati_pcigart.c48 u32 *pci_gart = NULL, page_base;
69 pci_gart = (u32 *)entry->dmah_gart->vaddr;
88 page_base = (u32) entry->busaddr[pagenum];
H A Dradeon_drv.h178 u32 *start;
179 u32 *end;
183 u32 tail;
184 u32 tail_mask;
191 u32 rb3d_cntl;
192 u32 rb3d_zstencilcntl;
193 u32 se_cntl;
213 u32 lower;
214 u32 upper;
215 u32 flag
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H A Dr300_cmdbuf.c286 if (!radeon_check_offset(dev_priv, (u32) values[i])) {
425 drm_radeon_kcmd_buffer_t *cmdbuf, u32 header)
429 u32 payload[MAX_ARRAY_PACKET];
430 u32 narrays;
494 u32 *cmd = (u32 *)(uintptr_t)cmdbuf->buf;
501 u32 offset;
542 u32 *cmd = (u32 *)(uintptr_t)cmdbuf->buf;
573 u32 heade
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H A Ddrm_ioctl.c57 drm_unique_32_t u32; local
59 DRM_COPYFROM_WITH_RETURN(&u32, (void *)data, sizeof (u32));
60 u1.unique_len = u32.unique_len;
61 u1.unique = (char __user *)(uintptr_t)u32.unique;
78 drm_unique_32_t u32; local
80 u32.unique_len = (uint32_t)u1.unique_len;
81 u32.unique = (caddr32_t)(uintptr_t)u1.unique;
82 DRM_COPYTO_WITH_RETURN((void *)data, &u32, sizeof (u32));
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H A Dradeon_irq.c42 static inline u32
43 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask)
76 u32 stat;
340 u32 flag;
341 u32 value;

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