/*
*/
/*
* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
*
* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
*/
#ifndef __RADEON_DRV_H__
#define __RADEON_DRV_H__
/*
* Enable debugging information outputs. Need to recompile
*
* #define RADEON_FIFO_DEBUG 1
*/
/* General customization: */
/*
* Interface history:
*
* 1.1 - ??
* 1.2 - Add vertex2 ioctl (keith)
* - Add stencil capability to clear ioctl (gareth, keith)
* - Increase MAX_TEXTURE_LEVELS (brian)
* 1.3 - Add cmdbuf ioctl (keith)
* - Add support for new radeon packets (keith)
* - Add getparam ioctl (keith)
* - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
* 1.4 - Add scratch registers to get_param ioctl.
* 1.5 - Add r200 packets to cmdbuf ioctl
* - Add r200 function to init ioctl
* - Add 'scalar2' instruction to cmdbuf
* 1.6 - Add static GART memory manager
* Add irq handler (won't be turned on unless X server knows to)
* Add irq ioctls and irq_active getparam.
* Add wait command for cmdbuf ioctl
* Add GART offset query for getparam
* 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
* and R200_PP_CUBIC_OFFSET_F1_[0..5].
* Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
* R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
* 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
* Add 'GET' queries for starting additional clients on different
* VT's.
* 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
* Add texture rectangle support for r100.
* 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
* clients use to tell the DRM where they think the framebuffer is
* located in the card's address space
* 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
* and GL_EXT_blend_[func|equation]_separate on r200
* 1.12- Add R300 CP microcode support - this just loads the CP on r300
* (No 3D support yet - just microcode loading).
* 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
* - Add hyperz support, add hyperz flags to clear ioctl.
* 1.14- Add support for color tiling
* - Add R100/R200 surface allocation/free support
* 1.15- Add support for texture micro tiling
* - Add support for r100 cube maps
* 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
* texture filtering on r200
* 1.17- Add initial support for R300 (3D).
* 1.18- Add support for GL_ATI_fragment_shader, new packets
* R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
* R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and
* R200_EMIT_ATF_TFACTOR
* (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
* 1.19- Add support for gart table in FB memory and PCIE r300
* 1.20- Add support for r300 texrect
* 1.21- Add support for card type getparam
* 1.22- Add support for texture cache flushes (R300_TX_CNTL)
* 1.23- Add new radeon memory map work from benh
* 1.24- Add general-purpose packet for manipulating scratch registers (r300)
* 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
* new packet type)
*/
#define DRIVER_PATCHLEVEL 0
/*
* Radeon chip families
*/
enum radeon_family {
};
enum radeon_cp_microcode_version {
};
/*
* Chip flags
*/
(dev_priv->writeback_works ? \
typedef struct drm_radeon_freelist {
unsigned int age;
typedef struct drm_radeon_ring_buffer {
int size;
int size_l2qw;
int space;
int high_mark;
typedef struct drm_radeon_depth_clear_t {
struct drm_radeon_driver_file_fields {
#ifdef __sparc
void *private_data;
#endif /* sparc */
};
struct mem_block {
int start;
int size;
};
struct radeon_surface {
int refcount;
};
struct radeon_virt_surface {
int surface_index;
};
typedef struct drm_radeon_private {
int new_memmap;
int gart_size;
unsigned long gart_buffers_offset;
int cp_mode;
int cp_running;
int last_buf;
int writeback_works;
int usec_timeout;
int microcode_version;
struct {
int freelist_timeouts;
int freelist_loops;
int requested_bufs;
int last_frame_reads;
int last_clear_reads;
int clears;
int texture_uploads;
} stats;
int do_boxes;
int page_flipping;
int current_page;
unsigned int front_offset;
unsigned int front_pitch;
unsigned int back_offset;
unsigned int back_pitch;
unsigned int depth_offset;
unsigned int depth_pitch;
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long gart_textures_offset;
/* SW interrupt */
int vblank_crtc;
int irq_enabled;
unsigned long pcigart_offset;
/* starting from here on, data is preserved across an open */
#ifdef __sparc
void *private_data;
#endif /* sparc */
typedef struct drm_radeon_buf_priv {
typedef struct drm_radeon_kcmd_buffer {
int bufsz;
char *buf;
int nbox;
extern int radeon_no_wb;
extern drm_ioctl_desc_t radeon_ioctls[];
extern int radeon_max_ioctl;
/*
* Check whether the given hardware address is inside the framebuffer or the
* GART area.
*/
static inline int
{
}
/* radeon_cp.c */
extern int radeon_cp_init(DRM_IOCTL_ARGS);
extern int radeon_cp_start(DRM_IOCTL_ARGS);
extern int radeon_cp_stop(DRM_IOCTL_ARGS);
extern int radeon_cp_reset(DRM_IOCTL_ARGS);
extern int radeon_cp_idle(DRM_IOCTL_ARGS);
extern int radeon_cp_resume(DRM_IOCTL_ARGS);
extern int radeon_engine_reset(DRM_IOCTL_ARGS);
extern int radeon_fullscreen(DRM_IOCTL_ARGS);
extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
extern int radeon_mem_free(DRM_IOCTL_ARGS);
extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
/* radeon_irq.c */
extern int radeon_irq_emit(DRM_IOCTL_ARGS);
extern int radeon_irq_wait(DRM_IOCTL_ARGS);
unsigned int *sequence);
unsigned int *sequence);
unsigned long arg);
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(void);
/* Flags for stats.boxes */
/*
* Register definitions, register access macros and drmAddMap constants
* for Radeon kernel driver.
*/
#define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
#define RADEON_FFACE_CULL_CW (0 << 0)
#define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
/* CP registers */
#define RADEON_PRE_WRITE_TIMER_SHIFT 0
/* CP command packets */
/* GEN_INDX_PRIM is unsupported starting with R300 */
#define RADEON_PRIM_TYPE_NONE (0 << 0)
#define RADEON_TXFORMAT_I8 0
/* MPEG settings from VHA code */
// set as reference header
/* Constants */
do { \
} while (__lintzero)
do { \
((addr) & 0xff)); \
} while (__lintzero)
#define CP_PACKET2() \
/*
* Engine control helper macros
*/
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
} while (__lintzero)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
} while (__lintzero)
#define RADEON_WAIT_UNTIL_IDLE() do { \
} while (__lintzero)
#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
} while (__lintzero)
#define RADEON_FLUSH_CACHE() do { \
} while (__lintzero)
#define RADEON_PURGE_CACHE() do { \
} while (__lintzero)
#define RADEON_FLUSH_ZCACHE() do { \
} while (__lintzero)
#define RADEON_PURGE_ZCACHE() do { \
} while (__lintzero)
/*
* Misc helper macros
*/
/* Perfbox functionality only. */
do { \
} \
} while (__lintzero)
do { \
if (__ret) \
return (__ret); \
sarea_priv->last_dispatch = 0; \
} \
} while (__lintzero)
} while (__lintzero)
} while (__lintzero)
} while (__lintzero)
/*
* Ring control
*/
#define BEGIN_RING(n) do { \
COMMIT_RING(); \
} \
} while (__lintzero)
#define ADVANCE_RING() do { \
DRM_ERROR( \
"ADVANCE_RING(): mismatch: nr: " \
"%x write: %x line: %d\n", \
} else \
} while (__lintzero)
#else
#define COMMIT_RING() do { \
/* Flush writes to ring */ \
DRM_MEMORYBARRIER(); \
/* read from PCI bus to ensure correct posting */ \
} while (__lintzero)
#endif
#define OUT_RING(x) do { \
} while (__lintzero)
} while (__lintzero)
\
while (_i > 0) { \
write++; \
_i--; \
} \
write = 0; \
} \
while (_size > 0) { \
write++; \
_size--; \
} \
} while (__lintzero)
#endif /* __RADEON_DRV_H__ */