1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 1450N/A * Copyright (c) 2007-2008, 2013, Intel Corporation 1450N/A * Jesse Barnes <jesse.barnes@intel.com> 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the "Software"), 1450N/A * to deal in the Software without restriction, including without limitation 1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1450N/A * and/or sell copies of the Software, and to permit persons to whom the 1450N/A * Software is furnished to do so, subject to the following conditions: 1450N/A * The above copyright notice and this permission notice (including the next 1450N/A * paragraph) shall be included in all copies or substantial portions of the 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1450N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1450N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1450N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 1450N/A/* store information about an Ixxx DVO */ 1450N/A/* The i830->i865 use multiple DVOs with multiple i2cs */ 1450N/A/* the i915, i945 have a single sDVO i2c bus - which is different */ 1450N/A/* maximum connectors per crtcs in the mode set */ 1450N/A/* these are outputs from the chip - integrated only 1450N/A external chips are via DVO or SDVO output */ 1450N/A * The new crtc this encoder will be driven from. Only differs from 1450N/A * base->crtc while a modeset is in progress. 1450N/A * Intel hw has only one MUX where encoders could be clone, hence a 1450N/A * simple flag is enough to compute the possible_clones mask. 1450N/A /* Read out the current hw state of this connector, returning true if 1450N/A * the encoder is active. If the encoder is enabled it also set the pipe 1450N/A * it is connected to in the pipe parameter. */ 1450N/A /* Reconstructs the equivalent mode flags for the current hardware 1450N/A * state. This must be called _after_ display->get_pipe_config has 1450N/A * pre-filled the pipe config. Note that intel_encoder->base.crtc must 1450N/A * be set correctly before calling this function. */ 1450N/A * The fixed encoder this connector is connected to. 1450N/A * The new encoder this connector will be driven. Only differs from 1450N/A * encoder while a modeset is in progress. 1450N/A /* Reads out the current hw, returning true if the connector is enabled 1450N/A * and active (i.e. dpms ON state). */ 1450N/A /* Panel info for eDP and LVDS */ 1450N/A /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 1450N/A /* since POLL and HPD connectors may use the same HPD line keep the native 1450N/A state of connector->polled in case hotplug storm detection changes it */ 1450N/A * quirks - bitfield with hw state readout quirks 1450N/A * For various reasons the hw state readout code might not be able to 1450N/A * completely faithfully read out the current state. These cases are 1450N/A * tracked with quirk flags so that fastboot and state checker can act 1450N/A /* This flag must be set by the encoder's compute_config callback if it 1450N/A * changes the crtc timings in the mode to prevent the crtc fixup from 1450N/A * overwriting them. Currently only lvds needs that. */ 1450N/A /* Whether to set up the PCH/FDI. Note that we never allow sharing 1450N/A * between pch encoders and cpu encoders. */ 1450N/A /* CPU Transcoder for the pipe. Currently this can only differ from the 1450N/A * pipe on Haswell (where we have a special eDP transcoder). */ 1450N/A * range fed into the crtcs. 1450N/A /* DP has a bunch of special case unfortunately, so mark the pipe 1450N/A * Enable dithering, used when the selected pipe bpp doesn't match the 1450N/A /* Controls for the clock computation, to override various stages. */ 1450N/A /* SDVO TV has a bunch of special case. To make multifunction encoders 1450N/A * work correctly, we need to track this at runtime.*/ 1450N/A * crtc bandwidth limit, don't increase pipe bpp or clock if not really 1450N/A * required. This is set in the 2nd loop of calling encoder's 1450N/A * ->compute_config if the first pick doesn't work out. 1450N/A /* Settings for the intel dpll used on pretty much everything but 1450N/A /* Selected dpll when shared or DPLL_ID_PRIVATE. */ 1450N/A /* Actual register state of the dpll, for shared dpll cross-checking. */ 1450N/A * Frequence the dpll for the port should run at. Differs from the 1450N/A * adjusted dotclock e.g. for DP or 12bpc hdmi mode. 1450N/A /* Used by SDVO (and if we ever fix it, HDMI). */ 1450N/A /* Panel fitter controls for gen2-gen4 + VLV */ 1450N/A /* Panel fitter placement and size for Ironlake+ */ 1450N/A /* FDI configuration, only valid if has_pch_encoder is set. */ 1450N/A * Whether the crtc and the connected output pipeline is active. Implies 1450N/A * that crtc->enabled is set, i.e. the current mode configuration has 1450N/A * some outputs connected to this crtc. 1450N/A /* Display surface base address adjustement for pageflips. Note that on 1450N/A * gen4+ this only adjusts up to a tile, offsets within a tile are 1450N/A * handled in the hw itself (with the TILEOFF register). */ 1450N/A /* reset counter value when the last flip was submitted */ 1450N/A /* Access to these should be protected by dev_priv->irq_lock. */ 1450N/A * as the other pieces of the struct may not reflect the values we want 1450N/A * for the watermark calculations. Currently only Haswell uses this. 1450N/A /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ 1450N/A /* PB2 - C 7:6, M 5:4, R 3:0 */ 1450N/A /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ 1450N/A#
endif /* __INTEL_DRV_H__ */