Lines Matching refs:u32
40 static const u32 hpd_ibx[] = {
48 static const u32 hpd_cpt[] = {
56 static const u32 hpd_mask_i915[] = {
65 static const u32 hpd_status_gen4[] = {
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
97 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
318 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
320 u32 reg = PIPESTAT(pipe);
321 u32 pipestat = I915_READ(reg) & 0x7fff0000;
333 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
335 u32 reg = PIPESTAT(pipe);
336 u32 pipestat = I915_READ(reg) & 0x7fff0000;
374 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
379 u32 high1, high2, low;
406 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
424 u32 vbl = 0, position = 0;
550 u32 hpd_event_bits;
612 u32 busy_up, busy_down, max_avg, min_avg;
668 u32 pm_iir, pm_imr;
724 u32 error_status, row, bank, subbank;
778 u32 gt_iir)
801 u32 pm_iir)
828 u32 hotplug_trigger,
829 const u32 *hpd)
889 u32 pm_iir)
920 u32 iir, gt_iir, pm_iir;
924 u32 pipe_stats[I915_MAX_PIPES];
969 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
970 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
996 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1000 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1052 u32 err_int = I915_READ(GEN7_ERR_INT);
1075 u32 serr_int = I915_READ(SERR_INT);
1098 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1102 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1140 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1205 u32 pch_iir = I915_READ(SDEIIR);
1246 u32 gt_iir)
1260 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1325 u32 pch_iir = I915_READ(SDEIIR);
1463 u32 reloc_offset;
1468 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1594 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1609 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1664 u32 seqno;
1670 u32 acthd = I915_READ(ACTHD);
1959 u32 eir = I915_READ(EIR);
1971 u32 ipeir = I915_READ(IPEIR_I965);
1989 u32 pgtbl_err = I915_READ(PGTBL_ER);
2000 u32 pgtbl_err = I915_READ(PGTBL_ER);
2021 u32 ipeir = I915_READ(IPEIR);
2034 u32 ipeir = I915_READ(IPEIR_I965);
2209 u32 imr;
2272 u32 imr;
2286 static u32
2296 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2303 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2306 u32 cmd, ipehr, acthd, acthd_min;
2307 u32 *tmp;
2320 tmp = (u32 *)((intptr_t)ring->virtual_start + acthd);
2330 tmp = (u32 *)((intptr_t)ring->virtual_start + acthd + 4 );
2339 u32 seqno, ctl;
2365 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2369 u32 tmp;
2432 u32 seqno, acthd;
2629 u32 mask = ~I915_READ(SDEIMR);
2630 u32 hotplug;
2663 u32 mask;
2687 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2691 u32 gt_irqs;
2739 u32 display_mask =
2746 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
2747 u32 gt_irqs;
2797 u32 gt_irqs;
2798 u32 enable_mask;
2799 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2984 u32 pipe_stats[2];
3083 u32 enable_mask;
3126 int plane, int pipe, u32 iir)
3129 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3158 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3160 u32 flip_mask =
3201 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3202 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3300 u32 enable_mask;
3301 u32 error_mask;
3356 u32 hotplug_en;
3387 u32 iir, new_iir;
3388 u32 pipe_stats[I915_MAX_PIPES];
3392 u32 flip_mask =
3437 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3438 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?