Lines Matching refs:u32
87 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
100 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
113 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
126 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
147 u32 val = I915_READ(VIDEO_DIP_CTL);
188 u32 val = I915_READ(reg);
228 u32 val = I915_READ(reg);
271 u32 val = I915_READ(reg);
309 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
310 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder);
312 u32 val = I915_READ(ctl_reg);
391 u32 reg = VIDEO_DIP_CTL;
392 u32 val = I915_READ(reg);
393 u32 port;
456 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
457 u32 val = I915_READ(reg);
458 u32 port;
516 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
517 u32 val = I915_READ(reg);
551 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
552 u32 val = I915_READ(reg);
585 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
586 u32 val = I915_READ(reg);
615 u32 hdmi_val;
659 u32 tmp;
679 u32 tmp, flags = 0;
702 u32 temp;
703 u32 enable_bits = SDVO_ENABLE;
750 u32 temp;
751 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
1039 u32 val;
1225 u32 temp = I915_READ(PEG_BAND_GAP_DATA);