Lines Matching refs:u32
236 u32 *lid_state;
272 u32 eir;
273 u32 pgtbl_er;
274 u32 ier;
275 u32 ccid;
276 u32 derrmr;
277 u32 forcewake;
279 u32 pipestat[I915_MAX_PIPES];
280 u32 tail[I915_NUM_RINGS];
281 u32 head[I915_NUM_RINGS];
282 u32 ctl[I915_NUM_RINGS];
283 u32 ipeir[I915_NUM_RINGS];
284 u32 ipehr[I915_NUM_RINGS];
285 u32 instdone[I915_NUM_RINGS];
286 u32 acthd[I915_NUM_RINGS];
287 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
288 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
289 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
291 u32 cpu_ring_head[I915_NUM_RINGS];
292 u32 cpu_ring_tail[I915_NUM_RINGS];
293 u32 error; /* gen6+ */
294 u32 err_int; /* gen7 */
295 u32 instpm[I915_NUM_RINGS];
296 u32 instps[I915_NUM_RINGS];
297 u32 extra_instdone[I915_NUM_INSTDONE_REG];
298 u32 seqno[I915_NUM_RINGS];
300 u32 fault_reg[I915_NUM_RINGS];
301 u32 done_reg;
302 u32 faddr[I915_NUM_RINGS];
308 u32 gtt_offset;
309 u32 **pages;
313 u32 seqno;
314 u32 tail;
320 u32 name;
321 u32 rseqno, wseqno;
322 u32 gtt_offset;
323 u32 read_domains;
324 u32 write_domain;
327 u32 tiling:2;
328 u32 dirty:1;
329 u32 purgeable:1;
330 u32 ring:4;
331 u32 cache_level:2;
333 u32 active_bo_count, pinned_bo_count;
437 u32 display_mmio_offset;
571 u32 reg0;
572 u32 gpio_reg;
583 u32 saveDSPACNTR;
584 u32 saveDSPBCNTR;
585 u32 saveDSPARB;
586 u32 saveHWS;
587 u32 savePIPEACONF;
588 u32 savePIPEBCONF;
589 u32 savePIPEASRC;
590 u32 savePIPEBSRC;
591 u32 saveFPA0;
592 u32 saveFPA1;
593 u32 saveDPLL_A;
594 u32 saveDPLL_A_MD;
595 u32 saveHTOTAL_A;
596 u32 saveHBLANK_A;
597 u32 saveHSYNC_A;
598 u32 saveVTOTAL_A;
599 u32 saveVBLANK_A;
600 u32 saveVSYNC_A;
601 u32 saveBCLRPAT_A;
602 u32 saveTRANSACONF;
603 u32 saveTRANS_HTOTAL_A;
604 u32 saveTRANS_HBLANK_A;
605 u32 saveTRANS_HSYNC_A;
606 u32 saveTRANS_VTOTAL_A;
607 u32 saveTRANS_VBLANK_A;
608 u32 saveTRANS_VSYNC_A;
609 u32 savePIPEASTAT;
610 u32 saveDSPASTRIDE;
611 u32 saveDSPASIZE;
612 u32 saveDSPAPOS;
613 u32 saveDSPAADDR;
614 u32 saveDSPASURF;
615 u32 saveDSPATILEOFF;
616 u32 savePFIT_PGM_RATIOS;
617 u32 saveBLC_HIST_CTL;
618 u32 saveBLC_PWM_CTL;
619 u32 saveBLC_PWM_CTL2;
620 u32 saveBLC_CPU_PWM_CTL;
621 u32 saveBLC_CPU_PWM_CTL2;
622 u32 saveFPB0;
623 u32 saveFPB1;
624 u32 saveDPLL_B;
625 u32 saveDPLL_B_MD;
626 u32 saveHTOTAL_B;
627 u32 saveHBLANK_B;
628 u32 saveHSYNC_B;
629 u32 saveVTOTAL_B;
630 u32 saveVBLANK_B;
631 u32 saveVSYNC_B;
632 u32 saveBCLRPAT_B;
633 u32 saveTRANSBCONF;
634 u32 saveTRANS_HTOTAL_B;
635 u32 saveTRANS_HBLANK_B;
636 u32 saveTRANS_HSYNC_B;
637 u32 saveTRANS_VTOTAL_B;
638 u32 saveTRANS_VBLANK_B;
639 u32 saveTRANS_VSYNC_B;
640 u32 savePIPEBSTAT;
641 u32 saveDSPBSTRIDE;
642 u32 saveDSPBSIZE;
643 u32 saveDSPBPOS;
644 u32 saveDSPBADDR;
645 u32 saveDSPBSURF;
646 u32 saveDSPBTILEOFF;
647 u32 saveVGA0;
648 u32 saveVGA1;
649 u32 saveVGA_PD;
650 u32 saveVGACNTRL;
651 u32 saveADPA;
652 u32 saveLVDS;
653 u32 savePP_ON_DELAYS;
654 u32 savePP_OFF_DELAYS;
655 u32 saveDVOA;
656 u32 saveDVOB;
657 u32 saveDVOC;
658 u32 savePP_ON;
659 u32 savePP_OFF;
660 u32 savePP_CONTROL;
661 u32 savePP_DIVISOR;
662 u32 savePFIT_CONTROL;
663 u32 save_palette_a[256];
664 u32 save_palette_b[256];
665 u32 saveDPFC_CB_BASE;
666 u32 saveFBC_CFB_BASE;
667 u32 saveFBC_LL_BASE;
668 u32 saveFBC_CONTROL;
669 u32 saveFBC_CONTROL2;
670 u32 saveIER;
671 u32 saveIIR;
672 u32 saveIMR;
673 u32 saveDEIER;
674 u32 saveDEIMR;
675 u32 saveGTIER;
676 u32 saveGTIMR;
677 u32 saveFDI_RXA_IMR;
678 u32 saveFDI_RXB_IMR;
679 u32 saveCACHE_MODE_0;
680 u32 saveMI_ARB_STATE;
681 u32 saveSWF0[16];
682 u32 saveSWF1[16];
683 u32 saveSWF2[3];
692 u32 saveCURACNTR;
693 u32 saveCURAPOS;
694 u32 saveCURABASE;
695 u32 saveCURBCNTR;
696 u32 saveCURBPOS;
697 u32 saveCURBBASE;
698 u32 saveCURSIZE;
699 u32 saveDP_B;
700 u32 saveDP_C;
701 u32 saveDP_D;
702 u32 savePIPEA_GMCH_DATA_M;
703 u32 savePIPEB_GMCH_DATA_M;
704 u32 savePIPEA_GMCH_DATA_N;
705 u32 savePIPEB_GMCH_DATA_N;
706 u32 savePIPEA_DP_LINK_M;
707 u32 savePIPEB_DP_LINK_M;
708 u32 savePIPEA_DP_LINK_N;
709 u32 savePIPEB_DP_LINK_N;
710 u32 saveFDI_RXA_CTL;
711 u32 saveFDI_TXA_CTL;
712 u32 saveFDI_RXB_CTL;
713 u32 saveFDI_TXB_CTL;
714 u32 savePFA_CTL_1;
715 u32 savePFB_CTL_1;
716 u32 savePFA_WIN_SZ;
717 u32 savePFB_WIN_SZ;
718 u32 savePFA_WIN_POS;
719 u32 savePFB_WIN_POS;
720 u32 savePCH_DREF_CONTROL;
721 u32 saveDISP_ARB_CTL;
722 u32 savePIPEA_DATA_M1;
723 u32 savePIPEA_DATA_N1;
724 u32 savePIPEA_LINK_M1;
725 u32 savePIPEA_LINK_N1;
726 u32 savePIPEB_DATA_M1;
727 u32 savePIPEB_DATA_N1;
728 u32 savePIPEB_LINK_M1;
729 u32 savePIPEB_LINK_N1;
730 u32 saveMCHBAR_RENDER_STANDBY;
731 u32 savePCH_PORT_HOTPLUG;
732 u32 pgtbl_ctl;
747 u32 pm_iir;
818 u32 *remap_info;
907 u32 object_count;
1048 u32 trace_irq_seqno;
1057 u32 irq_mask;
1058 u32 gt_irq_mask;
1071 u32 hpd_event_bits;
1185 u32 fdi_rx_config;
1395 u32 head;
1398 u32 tail;
1627 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1630 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1711 int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1712 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1767 u32 *seqno);
1779 u32 alignment,
1813 u32 id);
1856 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1859 u32 stolen_offset,
1860 u32 gtt_offset,
1861 u32 size);
1966 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1967 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1970 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
1971 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1972 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
1973 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
1974 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
1975 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1977 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1984 u ## x i915_read ## x(struct drm_i915_private *dev_priv, u32 reg);
1993 void i915_write ## x(struct drm_i915_private *dev_priv, u32 reg, \
2003 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (u32)(val))