1450N/A/*
1450N/A * Copyright (c) 2008, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
1450N/A/*
1450N/A * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
1450N/A *
1450N/A * The Weather Channel (TM) funded Tungsten Graphics to develop the
1450N/A * initial release of the Radeon 8500 driver under the XFree86 license.
1450N/A * This notice must be preserved.
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice (including the next
1450N/A * paragraph) shall be included in all copies or substantial portions of the
1450N/A * Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1450N/A * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
1450N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1450N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
1450N/A * DEALINGS IN THE SOFTWARE.
1450N/A *
1450N/A * Authors:
1450N/A * Keith Whitwell <keith@tungstengraphics.com>
1450N/A * Michel D�zer <michel@daenzer.net>
1450N/A */
1450N/A
1450N/A#include "drmP.h"
1450N/A#include "radeon_drm.h"
1450N/A#include "radeon_drv.h"
1450N/A#include "radeon_io32.h"
1450N/A
1450N/Astatic inline u32
1450N/Aradeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask)
1450N/A{
1450N/A uint32_t irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
1450N/A if (irqs)
1450N/A RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
1450N/A return (irqs);
1450N/A}
1450N/A
1450N/A/*
1450N/A * Interrupts - Used for device synchronization and flushing in the
1450N/A * following circumstances:
1450N/A *
1450N/A * - Exclusive FB access with hw idle:
1450N/A * - Wait for GUI Idle (?) interrupt, then do normal flush.
1450N/A *
1450N/A * - Frame throttling, NV_fence:
1450N/A * - Drop marker irq's into command stream ahead of time.
1450N/A * - Wait on irq's with lock *not held*
1450N/A * - Check each for termination condition
1450N/A *
1450N/A * - Internally in cp_getbuffer, etc:
1450N/A * - as above, but wait with lock held???
1450N/A *
1450N/A * NOTE: These functions are misleadingly named -- the irq's aren't
1450N/A * tied to dma at all, this is just a hangover from dri prehistory.
1450N/A */
1450N/A
1450N/Airqreturn_t
1450N/Aradeon_driver_irq_handler(DRM_IRQ_ARGS)
1450N/A{
1450N/A drm_device_t *dev = (drm_device_t *)(uintptr_t)arg;
1450N/A drm_radeon_private_t *dev_priv =
1450N/A (drm_radeon_private_t *)dev->dev_private;
1450N/A u32 stat;
1450N/A
1450N/A /*
1450N/A * Only consider the bits we're interested in - others could be used
1450N/A * outside the DRM
1450N/A */
1450N/A stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
1450N/A RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT));
1450N/A if (!stat)
1450N/A return (IRQ_NONE);
1450N/A
1450N/A stat &= dev_priv->irq_enable_reg;
1450N/A
1450N/A /* SW interrupt */
1450N/A if (stat & RADEON_SW_INT_TEST) {
1450N/A DRM_WAKEUP(&dev_priv->swi_queue);
1450N/A }
1450N/A
1450N/A /* VBLANK interrupt */
1450N/A if (stat & (RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT)) {
1450N/A int vblank_crtc = dev_priv->vblank_crtc;
1450N/A
1450N/A if ((vblank_crtc &
1450N/A (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
1450N/A (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
1450N/A if (stat & RADEON_CRTC_VBLANK_STAT)
1450N/A atomic_inc(&dev->vbl_received);
1450N/A if (stat & RADEON_CRTC2_VBLANK_STAT)
1450N/A atomic_inc(&dev->vbl_received2);
1450N/A } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
1450N/A (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
1450N/A ((stat & RADEON_CRTC2_VBLANK_STAT) &&
1450N/A (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
1450N/A atomic_inc(&dev->vbl_received);
1450N/A
1450N/A DRM_WAKEUP(&dev->vbl_queue);
1450N/A drm_vbl_send_signals(dev);
1450N/A }
1450N/A
1450N/A return (IRQ_HANDLED);
1450N/A}
1450N/A
1450N/Astatic int radeon_emit_irq(drm_device_t *dev)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv = dev->dev_private;
1450N/A unsigned int ret;
1450N/A RING_LOCALS;
1450N/A
1450N/A atomic_inc(&dev_priv->swi_emitted);
1450N/A ret = atomic_read(&dev_priv->swi_emitted);
1450N/A
1450N/A BEGIN_RING(4);
1450N/A OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
1450N/A OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
1450N/A ADVANCE_RING();
1450N/A COMMIT_RING();
1450N/A
1450N/A return (ret);
1450N/A}
1450N/A
1450N/Astatic int radeon_wait_irq(drm_device_t *dev, int swi_nr)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv =
1450N/A (drm_radeon_private_t *)dev->dev_private;
1450N/A int ret = 0;
1450N/A
1450N/A if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
1450N/A return (0);
1450N/A
1450N/A dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1450N/A
1450N/A DRM_WAIT_ON(ret, &dev_priv->swi_queue, 3 * DRM_HZ,
1450N/A RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
1450N/A
1450N/A return (ret);
1450N/A}
1450N/A
1450N/Astatic int radeon_driver_vblank_do_wait(struct drm_device *dev,
1450N/A unsigned int *sequence, int crtc)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv =
1450N/A (drm_radeon_private_t *)dev->dev_private;
1450N/A unsigned int cur_vblank;
1450N/A int ret = 0;
1450N/A atomic_t *counter;
1450N/A if (!dev_priv) {
1450N/A DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1450N/A return (EINVAL);
1450N/A }
1450N/A
1450N/A /*
1450N/A * I don't know why reset Intr Status Register here,
1450N/A * it might miss intr. So, I remove the code which
1450N/A * exists in open source, and changes as follows:
1450N/A */
1450N/A
1450N/A if (crtc == DRM_RADEON_VBLANK_CRTC1) {
1450N/A counter = &dev->vbl_received;
1450N/A } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
1450N/A counter = &dev->vbl_received2;
1450N/A } else
1450N/A return (EINVAL);
1450N/A
1450N/A dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1450N/A
1450N/A /*
1450N/A * Assume that the user has missed the current sequence number
1450N/A * by about a day rather than she wants to wait for years
1450N/A * using vertical blanks...
1450N/A */
1450N/A DRM_WAIT_ON(ret, &dev->vbl_queue, 3 * DRM_HZ,
1450N/A (((cur_vblank = atomic_read(counter)) - *sequence) <= (1 << 23)));
1450N/A
1450N/A *sequence = cur_vblank;
1450N/A
1450N/A return (ret);
1450N/A}
1450N/A
1450N/Aint
1450N/Aradeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
1450N/A{
1450N/A return (radeon_driver_vblank_do_wait(dev, sequence,
1450N/A DRM_RADEON_VBLANK_CRTC1));
1450N/A}
1450N/A
1450N/Aint
1450N/Aradeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
1450N/A{
1450N/A return (radeon_driver_vblank_do_wait(dev, sequence,
1450N/A DRM_RADEON_VBLANK_CRTC2));
1450N/A}
1450N/A
1450N/A/*
1450N/A * Needs the lock as it touches the ring.
1450N/A */
1450N/A/*ARGSUSED*/
1450N/Aint
1450N/Aradeon_irq_emit(DRM_IOCTL_ARGS)
1450N/A{
1450N/A DRM_DEVICE;
1450N/A drm_radeon_private_t *dev_priv = dev->dev_private;
1450N/A drm_radeon_irq_emit_t emit;
1450N/A int result;
1450N/A
1450N/A LOCK_TEST_WITH_RETURN(dev, fpriv);
1450N/A
1450N/A if (!dev_priv) {
1450N/A DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1450N/A return (EINVAL);
1450N/A }
1450N/A
1450N/A#ifdef _MULTI_DATAMODEL
1450N/A if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
1450N/A drm_radeon_irq_emit_32_t emit32;
1450N/A
1450N/A DRM_COPYFROM_WITH_RETURN(&emit32, (void *) data,
1450N/A sizeof (emit32));
1450N/A emit.irq_seq = (void *)(uintptr_t)(emit32.irq_seq);
1450N/A } else {
1450N/A#endif
1450N/A
1450N/A DRM_COPYFROM_WITH_RETURN(&emit, (void *) data, sizeof (emit));
1450N/A#ifdef _MULTI_DATAMODEL
1450N/A}
1450N/A#endif
1450N/A
1450N/A result = radeon_emit_irq(dev);
1450N/A
1450N/A if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof (int))) {
1450N/A DRM_ERROR("copy_to_user\n");
1450N/A return (EFAULT);
1450N/A }
1450N/A
1450N/A return (0);
1450N/A}
1450N/A
1450N/A/*
1450N/A * Doesn't need the hardware lock.
1450N/A */
1450N/A/*ARGSUSED*/
1450N/Aint
1450N/Aradeon_irq_wait(DRM_IOCTL_ARGS)
1450N/A{
1450N/A DRM_DEVICE;
1450N/A drm_radeon_private_t *dev_priv = dev->dev_private;
1450N/A drm_radeon_irq_wait_t irqwait;
1450N/A
1450N/A if (!dev_priv) {
1450N/A DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1450N/A return (EINVAL);
1450N/A }
1450N/A
1450N/A DRM_COPYFROM_WITH_RETURN(&irqwait, (void *) data, sizeof (irqwait));
1450N/A
1450N/A return (radeon_wait_irq(dev, irqwait.irq_seq));
1450N/A}
1450N/A
1450N/Astatic void radeon_enable_interrupt(struct drm_device *dev)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv;
1450N/A
1450N/A dev_priv = (drm_radeon_private_t *)dev->dev_private;
1450N/A dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
1450N/A
1450N/A if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1) {
1450N/A dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
1450N/A }
1450N/A
1450N/A if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2) {
1450N/A dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
1450N/A }
1450N/A
1450N/A RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
1450N/A dev_priv->irq_enabled = 1;
1450N/A}
1450N/A
1450N/A
1450N/A/*
1450N/A * drm_dma.h hooks
1450N/A */
1450N/Avoid
1450N/Aradeon_driver_irq_preinstall(drm_device_t *dev)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv =
1450N/A (drm_radeon_private_t *)dev->dev_private;
1450N/A
1450N/A /* Disable *all* interrupts */
1450N/A RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1450N/A
1450N/A /* Clear bits if they're already high */
1450N/A (void) radeon_acknowledge_irqs(dev_priv,
1450N/A (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT |
1450N/A RADEON_CRTC2_VBLANK_STAT));
1450N/A}
1450N/A
1450N/Avoid
1450N/Aradeon_driver_irq_postinstall(drm_device_t *dev)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv =
1450N/A (drm_radeon_private_t *)dev->dev_private;
1450N/A
1450N/A atomic_set(&dev_priv->swi_emitted, 0);
1450N/A DRM_INIT_WAITQUEUE(&dev_priv->swi_queue, DRM_INTR_PRI(dev));
1450N/A
1450N/A radeon_enable_interrupt(dev);
1450N/A}
1450N/A
1450N/Avoid
1450N/Aradeon_driver_irq_uninstall(drm_device_t *dev)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv =
1450N/A (drm_radeon_private_t *)dev->dev_private;
1450N/A if (!dev_priv)
1450N/A return;
1450N/A
1450N/A /* Disable *all* interrupts */
1450N/A RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1450N/A DRM_FINI_WAITQUEUE(&dev_priv->swi_queue);
1450N/A}
1450N/A
1450N/Aint
1450N/Aradeon_vblank_crtc_get(drm_device_t *dev)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv;
1450N/A u32 flag;
1450N/A u32 value;
1450N/A
1450N/A dev_priv = (drm_radeon_private_t *)dev->dev_private;
1450N/A flag = RADEON_READ(RADEON_GEN_INT_CNTL);
1450N/A value = 0;
1450N/A
1450N/A if (flag & RADEON_CRTC_VBLANK_MASK)
1450N/A value |= DRM_RADEON_VBLANK_CRTC1;
1450N/A
1450N/A if (flag & RADEON_CRTC2_VBLANK_MASK)
1450N/A value |= DRM_RADEON_VBLANK_CRTC2;
1450N/A return (value);
1450N/A}
1450N/A
1450N/Aint
1450N/Aradeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
1450N/A{
1450N/A drm_radeon_private_t *dev_priv;
1450N/A
1450N/A dev_priv = (drm_radeon_private_t *)dev->dev_private;
1450N/A if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
1450N/A DRM_ERROR("called with invalid crtc 0x%x\n",
1450N/A (unsigned int)value);
1450N/A return (EINVAL);
1450N/A }
1450N/A dev_priv->vblank_crtc = (unsigned int)value;
1450N/A radeon_enable_interrupt(dev);
1450N/A return (0);
1450N/A}