1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 1450N/A * Copyright (c) 2009, 2013, Intel Corporation. 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the 1450N/A * "Software"), to deal in the Software without restriction, including 1450N/A * without limitation the rights to use, copy, modify, merge, publish, 1450N/A * distribute, sub license, and/or sell copies of the Software, and to 1450N/A * permit persons to whom the Software is furnished to do so, subject to 1450N/A * the following conditions: 1450N/A * The above copyright notice and this permission notice (including the 1450N/A * next paragraph) shall be included in all copies or substantial portions 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1450N/A * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1450N/A * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 1450N/A * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 1450N/A * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 1450N/A * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 1450N/A * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 1450N/A /* real shared dpll ids must be >= 0 */ 1450N/A int active;
/* count of number of active CRTCs (i.e. DPMS on) */ 1450N/A bool on;
/* is the PLL actually active? Disabled during modeset */ 1450N/A /* should match the index in the dev_priv->shared_dplls array */ 1450N/A/* Used by dp and fdi links */ 1450N/A * 1.2: Add Power Management 1450N/A * 1.4: Fix cmdbuffer path, add heap destroy 1450N/A * 1.5: Add vblank pipe configuration 1450N/A * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1450N/A * - Support vertical blank on secondary display pipe 1450N/A/* 16 fences + sign bit for FENCE_REG_NONE */ 1450N/A /* our own tracking of ring head and tail */ 1450N/A * find_dpll() - Find the best values for the PLL 1450N/A * @limit: limits for the PLL 1450N/A * @target: target frequency in kHz 1450N/A * @refclk: reference clock frequency in kHz 1450N/A * @match_clock: if provided, @best_clock P divider must 1450N/A * match the P divider from @match_clock 1450N/A * used for LVDS downclocking 1450N/A * @best_clock: best PLL values found 1450N/A * Returns true on success, false on failure. 1450N/A /* Returns the active state of the crtc, and if the crtc is active, 1450N/A * fills out the pipe-config with the hw state. */ 1450N/A /* clock updates for mode set */ 1450N/A/* The Graphics Translation Table is the way in which GEN hardware translates a 1450N/A * Graphics Virtual Address into a Physical Address. In addition to the normal 1450N/A * collateral associated with any va->pa translations GEN hardware also has a 1450N/A * portion of the GTT which can be mapped by the CPU and remain both coherent 1450N/A * and correct (in cases like swizzling). That region is referred to as GMADR in 1450N/A /* pte functions, mirroring the interface of the global gtt. */ 1450N/A /* This context had batch pending when hang was declared */ 1450N/A /* This context had batch active when hang was declared */ 1450N/A/* This must match up with the value previously used for execbuf2.rsvd1. */ 1450N/A /* lock - irqsave spinlock that protectects the work_struct and 1450N/A /* The below variables an all the rps hw state are protected by 1450N/A * Protects RPS/RC6 register access and PCU communication. 1450N/A * Must be taken after struct_mutex if nested. 1450N/A/* Power well structure for haswell */ 1450N/A /** Memory allocator for GTT stolen memory */ 1450N/A /** Memory allocator for GTT */ 1450N/A /** List of all objects in gtt_space. Used to restore gtt 1450N/A * List of objects which are not bound to the GTT (thus 1450N/A * are idle and not used by the GPU) but still have 1450N/A * (presumably uncached) pages still attached. 1450N/A /** Usable portion of the GTT for GEM */ 1450N/A /** PPGTT used for aliasing the PPGTT with the GTT */ 1450N/A * List of objects currently involved in rendering. 1450N/A * Includes buffers having the contents of their GPU caches 1450N/A * flushed, not necessarily primitives. last_rendering_seqno 1450N/A * represents when the rendering involved will be completed. 1450N/A * A reference is held on the buffer while on this list. 1450N/A * LRU list of objects which are not in the ringbuffer and 1450N/A * are ready to unbind, but are still in the GTT. 1450N/A * last_rendering_seqno is 0 while an object is in this list. 1450N/A * A reference is not held on the buffer while on this list, 1450N/A * as merely being GTT-bound shouldn't prevent its being 1450N/A * freed, and we'll pull it off the list in the free path. 1450N/A /** LRU list of objects with fence regs on them. */ 1450N/A * We leave the user IRQ off as much as possible, 1450N/A * but this means that requests will finish and never 1450N/A * be retired once the system goes idle. Set a timer to 1450N/A * fire periodically while the ring is running. When it 1450N/A * fires, go retire requests. 1450N/A * Are we in a non-interruptible section of code like 1450N/A * Flag if the X Server, and thus DRM, is not currently in 1450N/A * This is set between LeaveVT and EnterVT. It needs to be 1450N/A * replaced with a semaphore. It also needs to be 1450N/A * transitioned away from for kernel modesetting. 1450N/A /** Bit 6 swizzling required for X tiling */ 1450N/A /** Bit 6 swizzling required for Y tiling */ 1450N/A /* storage for physical objects */ 1450N/A /* accounting, useful for userland debugging */ 1450N/A /* For reset and error_state handling. */ 1450N/A /* Protected by the above dev->gpu_error.lock. */ 1450N/A * State variable and reset counter controlling the reset flow 1450N/A * Upper bits are for the reset counter. This counter is used by the 1450N/A * wait_seqno code to race-free noticed that a reset event happened and 1450N/A * that it needs to restart the entire ioctl (since most likely the 1450N/A * seqno it waited for won't ever signal anytime soon). 1450N/A * This is important for lock-free wait paths, where no contended lock 1450N/A * naturally enforces the correct ordering between the bail-out of the 1450N/A * waiter and the gpu reset work code. 1450N/A * Lowest bit controls the reset state machine: Set means a reset is in 1450N/A * progress. This state will (presuming we don't have any bugs) decay 1450N/A * into either unset (successful reset) or the special WEDGED value (hw 1450N/A * terminally sour). All waiters on the reset_queue will be woken when 1450N/A * Note that the code relies on 1450N/A * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG 1450N/A * Waitqueue to signal when the reset has completed. Used by clients 1450N/A * that wait for dev_priv->mm.wedged to settle. 1450N/A /* For gpu hang simulation. */ 1450N/A /** gt_fifo_count and the subsequent register write are synchronized 1450N/A * with dev->struct_mutex. */ 1450N/A /** forcewake_count is protected by gt_lock */ 1450N/A /** gt_lock is also taken in irq contexts. */ 1450N/A /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1450N/A * controller on different i2c buses. */ 1450N/A * Base address of the gmbus and gpio block. 1450N/A /* protects the irq masks */ 1450N/A /* DPIO indirect register protection */ 1450N/A /** Cached value of IMR to avoid reads in updating the bitfield */ 1450N/A /* indicates the reduced downclock for LVDS*/ 1450N/A /* ilk-only ips/rps state. Everything in here is protected by the global 1450N/A /* list of fbdev register on this device */ 1450N/A /* Old dri1 support infrastructure, beware the dragons ya fools entering 1450N/A/* Iterate over initialised rings */ 1450N/A /* Interface between the GEM object and its backing storage. 1450N/A * get_pages() is called once prior to the use of the associated set 1450N/A * of pages before to binding them into the GTT, and put_pages() is 1450N/A * called after we no longer need them. As we expect there to be 1450N/A * associated cost with migrating pages between the backing storage 1450N/A * and making them available for the GPU (e.g. clflush), we may hold 1450N/A * onto the pages after they are no longer referenced by the GPU 1450N/A * in case they may be used again shortly (for example migrating the 1450N/A * pages to a different memory domain within the GTT). put_pages() 1450N/A * will therefore most likely be called when the object itself is 1450N/A * being released or under memory pressure (where we attempt to 1450N/A * reap pages for the shrinker). 1450N/A /** Current space allocated to this object in the GTT, if any. */ 1450N/A /** Stolen memory for this object, instead of being backed by shmem. */ 1450N/A /** This object's place on eviction list */ 1450N/A * This is set if the object is on the active or flushing lists 1450N/A * (has pending rendering), and is not set if it's on inactive (ready 1450N/A * This is set if the object has been written to since last bound 1450N/A * Fence register bits (if any) for this object. Will be set 1450N/A * as needed when mapped into the GTT. 1450N/A * Protected by dev->struct_mutex. 1450N/A * Advice: are the backing pages purgeable? 1450N/A * Current tiling mode for the object. 1450N/A * Whether the tiling parameters for the currently associated fence 1450N/A * register have changed. Note that for the purposes of tracking 1450N/A * tiling changes we also treat the unfenced register, the register 1450N/A * slot that the object occupies whilst it executes a fenced 1450N/A * command (such as BLT on gen2/3), as a "fence". 1450N/A /** How many users have pinned this object in GTT space. The following 1450N/A * (via user_pin_count), execbuffer (objects are not allowed multiple 1450N/A * times for the same batchbuffer), and the framebuffer code. When 1450N/A * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1450N/A * bits with absolutely no headroom. So use 4 bits. */ 1450N/A * Is the object at the current location in the gtt mappable and 1450N/A * fenceable? Used to avoid costly recalculations. 1450N/A * Whether the current gtt mapping needs to be mappable (and isn't just 1450N/A * mappable by accident). Track pin and fault separate for a more 1450N/A * accurate mappable working set. 1450N/A * Is the GPU currently using a fence to access this buffer, 1450N/A * Used for performing relocations during execbuffer insertion. 1450N/A * Current offset of the object in GTT space. 1450N/A * This is the same as gtt_space->start 1450N/A * Fake offset for use by mmap(2) 1450N/A /** Breadcrumb of last rendering to the buffer. */ 1450N/A /** Breadcrumb of last fenced GPU access to the buffer. */ 1450N/A /** Current tiling mode for the object. */ 1450N/A /** Record of address bit 17 of each page at last unbind. */ 1450N/A /** User space pin count and filp owning the pin */ 1450N/A /** for phy allocated objects */ 1450N/A /** OSOL: for cursor objects */ 1450N/A * The request queue allows us to note sequence numbers that have been emitted 1450N/A * and may be associated with active buffers to be retired. 1450N/A * By keeping this list, we can avoid having to do questionable 1450N/A * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1450N/A * an emission time with seqnos for tracking how far ahead of the GPU we are. 1450N/A /** On Which ring this request was generated */ 1450N/A /** GEM sequence number associated with this request. */ 1450N/A /** Position in the ringbuffer of the start of the request */ 1450N/A /** Postion in the ringbuffer of the end of the request */ 1450N/A /** Context related to this request */ 1450N/A /** Batch buffer related to this request if any */ 1450N/A /** Time at which this request was emitted, in jiffies. */ 1450N/A /** global list entry for this request */ 1450N/A /** file_priv list entry for this request */ 1450N/A * The genX designation typically refers to the render engine, so render 1450N/A * capability related checks should use IS_GEN, while display and other checks 1450N/A * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1450N/A/* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1450N/A/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1450N/A * rows, which changed the alignment requirements and fence programming. 1450N/A/* dsparb controlled by hw only */ 1450N/A * RC6 is a special power stage which allows the GPU to enter an very 1450N/A * low-voltage mode when idle, using down to 0V while at this stage. This 1450N/A * stage is entered automatically when the GPU is idle when RC6 support is 1450N/A * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1450N/A * There are different RC6 modes available in Intel GPU, which differentiate 1450N/A * among each other with the latency required to enter and leave RC6 and 1450N/A * voltage consumed by the GPU in different states. 1450N/A * The combination of the following flags define which states GPU is allowed 1450N/A * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1450N/A * RC6pp is deepest RC6. Their support by hardware varies according to the 1450N/A * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1450N/A * which brings the most power savings; deeper states save more power, but 1450N/A * require higher latency to switch to and wake up. 1450N/A * Returns true if seq1 is later than seq2. 1450N/A/* On SNB platform, before reading ring registers forcewake bit 1450N/A * must be set to prevent GT core from power down and stale values being 1450N/A/* "Broadcast RGB" property */