Lines Matching refs:u32
46 volatile u32 *cpu_page;
47 u32 gtt_offset;
60 u32 invalidate_domains,
61 u32 flush_domains)
63 u32 cmd;
86 u32 invalidate_domains,
87 u32 flush_domains)
90 u32 cmd;
183 u32 scratch_addr = pc->gtt_offset + 128;
217 u32 invalidate_domains, u32 flush_domains)
219 u32 flags = 0;
221 u32 scratch_addr = pc->gtt_offset + 128;
287 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
310 u32 invalidate_domains, u32 flush_domains)
312 u32 flags = 0;
314 u32 scratch_addr = pc->gtt_offset + 128;
371 u32 value)
377 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
380 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
389 u32 addr;
403 u32 head;
514 pc->cpu_page = (u32*) obj->page_list[0];
625 u32 mmio_offset)
664 u32 mbox_reg = ring->signal_mbox[i];
679 u32 seqno)
695 u32 seqno)
698 u32 dw1 = MI_SEMAPHORE_MBOX |
747 u32 scratch_addr = pc->gtt_offset + 128;
792 static u32
803 static u32
810 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
815 static u32
823 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
944 u32 mmio = 0;
970 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
975 u32 reg = RING_INSTPM(ring->mmio_base);
989 u32 invalidate_domains,
990 u32 flush_domains)
1089 u32 pm_imr = I915_READ(GEN6_PMIMR);
1111 u32 pm_imr = I915_READ(GEN6_PMIMR);
1121 u32 offset, u32 length,
1144 u32 offset, u32 len,
1161 u32 cs_offset = obj->gtt_offset;
1196 u32 offset, u32 len,
1398 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1412 u32 seqno = 0;
1537 u32 seqno;
1608 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1634 u32 value)
1667 u32 invalidate, u32 flush)
1696 u32 offset, u32 len,
1717 u32 offset, u32 len,
1739 u32 invalidate, u32 flush)
1863 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)